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| REJ09B0146-0400O The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text. 32 SH7706 Group Hardware Manual Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family/SH7700 Series Rev.4.00 Revision Date: Mar. 22, 2004 Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. Rev. 4.00, 03/04, page ii of xlvi General Precautions on Handling of Product 1. Treatment of NC Pins Note: Do not connect anything to the NC pins. The NC (not connected) pins are either not connected to any of the internal circuitry or are they are used as test pins or to reduce noise. If something is connected to the NC pins, the operation of the LSI is not guaranteed. 2. Treatment of Unused Input Pins Note: Fix all unused input pins to high or low level. Generally, the input pins of CMOS products are high-impedance input pins. If unused pins are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur. 3. Processing before Initialization Note: When power is first supplied, the product's state is undefined. The states of internal circuits are undefined until full power is supplied throughout the chip and a low level is input on the reset pin. During the period where the states are undefined, the register settings and the output state of each pin are also undefined. Design your system so that it does not malfunction because of processing while it is in this undefined state. For those products which have a reset function, reset the LSI immediately after the power supply has been turned on. 4. Prohibition of Access to Undefined or Reserved Addresses Note: Access to undefined or reserved addresses is prohibited. The undefined or reserved addresses may be used to expand functions, or test registers may have been be allocated to these addresses. Do not access these registers; the system's operation is not guaranteed if they are accessed. Rev. 4.00, 03/04, page iii of xlvi Configuration of This Manual This manual comprises the following items: 1. General Precautions on Handling of Product 2. Configuration of This Manual 3. Preface 4. Contents 5. Overview 6. Description of Functional Modules CPU and System-Control Modules On-Chip Peripheral Modules The configuration of the functional description of each module differs according to the module. However, the generic style includes the following items: i) Feature ii) Input/Output Pin iii) Register Description iv) Operation v) Usage Note When designing an application system that includes this LSI, take notes into account. Each section includes notes in relation to the descriptions given, and usage notes are given, as required, as the final part of each section. 7. List of Registers 8. Electrical Characteristics 9. Appendix 10. Main Revisions and Additions in this Edition (only for revised versions) The list of revisions is a summary of points that have been revised or added to earlier versions. This does not include all of the revised contents. For details, see the actual locations in this manual. 11. Index Rev. 4.00, 03/04, page iv of xlvi Preface The SH7706 RISC (Reduced Instruction Set Computer) microcomputer includes a Renesas Technology-original RISC CPU as its core, and the peripheral functions required to configure a system. Target Users: This manual was written for users who will be using this LSI in the design of application systems. Users of this manual are expected to understand the fundamentals of electrical circuits, logical circuits, and microcomputers. Objective: This manual was written to explain the hardware functions and electrical characteristics of this LSI to the above users. Refer to the SH-3/SH-3E/SH3-DSP Programming Manual for a detailed description of the instruction set. Notes on reading this manual: * Product names The following products are covered in this manual. Product Classifications and Abbreviations Basic Classification SH7706 (176-pin plastic LQFP) SH7706 (208-pin plastic TFBGA) Product Code HD6417706F133 HD6417706BP133V * In order to understand the overall functions of the chip Read the manual according to the contents. This manual can be roughly categorized into parts on the CPU, system control functions, peripheral functions and electrical characteristics. * In order to understand the details of the CPU's functions Read the SH-3/SH-3E/SH3-DSP Programming Manual. Rev. 4.00, 03/04, page v of xlvi Rules: Register name: The following notation is used for cases when the same or a similar function, e.g. serial communication, is implemented on more than one channel: XXX_N (XXX is the register name and N is the channel number) The MSB (most significant bit) is on the left and the LSB (least significant bit) is on the right. Bit order: Number notation: Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx. Signal notation: Related Manuals: An overbar is added to a low-active signal: xxxx The latest versions of all related manuals are available from our web site. Please ensure you have the latest versions of all documents you require. http://www.renesas.com/eng/ SH7706 manuals: Document Title SH7706 Hardware Manual SH-3/SH-3E/SH3-DSP Programming Manual Document No. This manual ADE-602-096 Users manuals for development tools: Document Title SH Series C/C++ Compiler, Assembler, Optimizing Linkage Editor User's Manual SH Series Simulator/Debugger (for Windows) User's Manual SH Series Simulator/Debugger (for UNIX) User's Manual High-performance Embedded Workshop User's Manual SH Series High-performance Embedded Workshop, High-performance Debugging Interface Tutorial Document No. ADE-702-246 ADE-702-186 ADE-702-203 ADE-702-201 ADE-702-230 Rev. 4.00, 03/04, page vi of xlvi Abbreviations ACIA ADC AUD BSC CPG CMT DAC DMA DMAC DRAM ETU FIFO H-UDI INTC JEIDA JTAG LRU LSB MMU MSB PCMCIA PFC PLL RISC ROM RTC Asynchronous Communication Interface Adapter Analog to Digital Converter Advanced User Debugger Bus State Controller Clock Pulse Generator Compare Match Timer Digital to Analog Converter Direct Memory Access Direct Memory Access Controller Dynamic Random Access Memory Elementary Time Unit First-In First-Out User Debugging Interface Interrupt Controller Japan Electronic Industry Development Association Joint Test Action Group Least Recently Used Least Significant Bit Memory Management Unit Most Significant Bit Personal Computer Memory Card International Association Pin Function Controller Phase Locked Loop Reduced Instruction Set Computer Read Only Memory Realtime Clock Rev. 4.00, 03/04, page vii of xlvi SCI SCIF SRAM TLB TMU UART UBC WDT Serial Communication Interface Serial Communication Interface with FIFO Static Random Access Memory Translation Lookaside Buffer Timer Unit Universal Asynchronous Receiver/Transmitter User Break Controller Watchdog Timer Rev. 4.00, 03/04, page viii of xlvi Main Revisions and Additions in this Edition Item 1.2 Block Diagram Figure 1.1 Pin Assignment (TBP-208A) 1.4 Pin Function 6 to 12 Package name amended Number of Pins FP-176C 9 TBP-208A Pin Name Page 4 Revision (See Manual for Details) Figure 1.1 title amended Description amended Chip select 0 2.1.4 Control Registers 18 * Status Register (SR) Description of bit 29 amended Register bank bit Determines the bank of general registers R0 to R7 used in privileged mode. ... 2.3.2 Addressing Modes Table 2.2 Addressing Modes and Effective Addresses 26 Note amended Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed according to the operand size. This is done to clarify the operation of the LSI. Refer to the relevant assembler notation rules for the actual assembler descriptions. 2.4.1 Instruction Set Classified by Function Table 2.7 Logic Operation Instructions 38 Table 2.7 amended Instruction TAS.B @Rn* Operation If (Rn) is 0, 1 T; 1 MSB of (Rn)* Code 0100nnnn00011011 Privileged Mode Cycles T Bit -- 4 Test result Rev. 4.00, 03/04, page ix of xlvi Item 2.4.1 Instruction Set Classified by Function Table 2.10 System Control Instructions Page 41 to 43 Revision (See Manual for Details) Table 2.10 amended Privileged Instruction Operation Code Mode Cycles T Bit CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK 0 MACH, MACL 0S 0T Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm R0_BANK Rm R1_BANK Rm R2_BANK Rm R3_BANK Rm R4_BANK Rm R5_BANK Rm R6_BANK Rm R7_BANK (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) R0_BANK, Rm + 4 Rm (Rm) R1_BANK, Rm + 4 Rm (Rm) R2_BANK, Rm + 4 Rm (Rm) R3_BANK, Rm + 4 Rm (Rm) R4_BANK, Rm + 4 Rm (Rm) R5_BANK, Rm + 4 Rm (Rm) R6_BANK, Rm + 4 Rm (Rm) R7_BANK, Rm + 4 Rm (Rm) cache Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) Rn-4 Rn, SSR (Rn) Rn-4 Rn, SPC (Rn) PC SPC, SR SSR, imm TRA 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111 -- -- -- 1 1 1 5 3 3 3 3 3 3 3 3 3 3 3 3 7 5 5 5 5 5 5 5 5 -- -- 0 LSB -- -- -- -- -- -- -- -- -- -- -- -- LSB -- -- -- -- -- -- -- -- -- -- LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R2_BANK LDC.L @Rm+, R3_BANK LDC.L @Rm+, R4_BANK LDC.L @Rm+, R5_BANK LDC.L @Rm+, R6_BANK LDC.L @Rm+, R7_BANK PREF @Rm -- -- 0100mmmm10010111 0100mmmm10100111 0100mmmm10110111 0100mmmm11000111 5 5 5 5 -- -- -- -- 0100mmmm11010111 0100mmmm11100111 0100mmmm11110111 0000mmmm10000011 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 11000011iiiiiiii 2 2 2 2 2 2 8 -- -- -- -- -- -- -- STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn STC.L SPC,@-Rn TRAPA #imm -- 2.4.2 Instruction Code Map Table 2.11 Instruction Code Map 45 Table 2.11 amended Instruction Code MSB 0000 0000 0000 0000 0000 0000 0000 0000 0000 Rn Rn Rn Rn Rn Rn Rm Rm Rn Fx Fx LSB 0000 0001 SR,Rn SPC,Rn R0_BANK,Rn R4_BANK,Rn Rm @Rm Rm,@(R0,Rn) MOV.W Rm,@(R0,Rn) MOV.L Rm,@(R0,Rn) MUL.L Rm,Rn STC STC R1_BANK,Rn R5_BANK,Rn STC STC BRAF R2_BANK,Rn R6_BANK,Rn Rm STC STC R3_BANK,Rn R7_BANK,Rn STC GBR,Rn STC VBR,Rn STC SSR,Rn Fx: 0000 MD: 00 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 00MD 0010 STC 01MD 0010 STC 10MD 0010 STC 11MD 0010 STC 00MD 0011 BSRF 10MD 0011 PREF Rm 01MD MOV.B Rev. 4.00, 03/04, page x of xlvi Item 3.3.2 TLB Indexing Page 61 Revision (See Manual for Details) Description added The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits in PTEH 4 to 0 are used as the index number regardless of the page size. ... 3.5.2 TLB Protection Violation Exception 71 Description added Software (TLB Protection Violation Handler) Operations: Software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. Note that the RTE instruction should be issued after the two instructions following the LDTLB instruction. 3.6.3 Usage Examples 78 Description deleted Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. R0 specifies the write data and R1 specifies the address. 6.4.4 Interrupt Request Register 0 (IRR0) 8.3 Area Overview Figure 8.2 Corresponding to Logical Address Space and Physical Address Space 126 Bit 5 R/W amended (Before) R (After) R/W 163 Note amended Note: For logical address spaces P0 and P3, when the memory management unit (MMU) is on, it can optionally generate a physical address for the logical address. It can be applied when the MMU is off and when the MMU is on and each physical address for the logical address is equal except for upper three bits. See table 8.2, Physical Address Space Map, for information on converting logical addresses into user-defined physical addresses. 8.4.6 PCMCIA Control Register (PCR) 185 Bit table of bits 11, 7, 6 amended Bit* 13, 12 11 7 6 Bit Name -- A5TED2 A5TED1 A5TED0 Initial Value All 0 0 0 0 R/W R R/W R/W R/W 8.5.2 Description of Areas 197 Description added ... The number of bus cycles is selected between 0 and 10 wait cycles using the A0W2 to A0W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 10 according to the number of waits. Rev. 4.00, 03/04, page xi of xlvi Item 9.3 Register Description Page 246 Revision (See Manual for Details) Description added Channel 3 * DMA source address register 3 (SAR3) * DMA destination address register 3 (DAR3) * DMA transfer count register 3 (DMATCR3) * DMA channel control register 3 (CHCR3) Any Channel * DMA operation register (DMAOR) 9.5.3 Operation Figure 9.27 Counter Operation 10.1 Feature Figure 10.1 Block Diagram of Clock Pulse Generator 285 Figure 9.27 amended (Before) CMCNT0 value (After) CMCNT value (Before) CMCOR0 (After) CMCOR 292 Figure 10.1 amended Clock pulse generator CAP1 PLL circuit 1 (x 1, 2, 3, 4) CKIO Cycle = Bcyc CAP2 XTAL EXTAL Crystal oscillator PLL circuit 2 (x 1, 4) Divider 2 x1 x 1/2 x 1/3 x 1/4 x 1/6 Divider 1 x1 x 1/2 x 1/3 x 1/4 Internal clock (I) Cycle = Icyc Peripheral clock (P) Cycle = Pcyc Bus clock (B) Cycle = Bcyc 293 5. description amended 5. Divider 2: Divider 2 generates a clock at the operating frequency used by the bus clock (B) and peripheral clock (P). The operating frequency of the peripheral clock can be 1, 1/2, 1/3, 1/4, or 1/6 times the output frequency of PLL Circuit 1, as long as it stays at or below the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. Rev. 4.00, 03/04, page xii of xlvi Item Page Revision (See Manual for Details) Description amended Table 10.2 shows the relationship between the mode control pin (MD2 to MD0) combinations and the clock operating modes. Table 10.3 shows the usable frequency ranges in the clock operating modes and frequency ranges of the input clock (crystal oscillation). Operation cannot be guaranteed if settings other than those listed in table 10.3 are used. 10.3 Clock Operating Modes 294 297 Caution 4 amended 4. The frequency of the peripheral clock (P): * The frequency of the peripheral clock (P) is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2. Section 11 Watchdog Timer (WDT) Figure 11.1 Block Diagram of the WDT 303 Figure 11.1 amended WDT Standby cancellation Internal reset request Interrupt request Standby control Standby mode Peripheral clock Reset control Clock selection Overflow Divider Clock selector Interrupt control WTCSR Clock WTCNT Bus interface 11.2.1 Watchdog Timer Counter (WTCNT) 304 Description amended ... The WTCNT is initialized to H'00 only by a power-on reset through the RESETP pin. ... 11.2.2 Watchdog Timer Control/Status Register (WTCSR) 12.5.2 Status Flag Clear Timing Figure 12.9 Status Flag Clear Timing 304 Description amended ... The WTCSR is initialized to H'00 only by a power-on reset through the RESETP pin. ... 323 Figure 12.9 amended TCR write cycle T1 P Peripheral address bus UNF, ICPF TCR address T2 T3 13.3.9 Second Alarm Register (RSECAR) 333 Bit 7 R/W amended (Before) R (After) R/W Rev. 4.00, 03/04, page xiii of xlvi Item 13.4.2 Setting Time Figure 13.2 Setting the Time Page 341 Revision (See Manual for Details) Figure 13.2 amended To reset the divider circuit (RTC prescaler and R64CNT) and set the counter Stop clock, reset divider circuit Write 0 to START and 1 to RESET in the RCR2 register Set seconds, minutes, hour, day, day of the week, month and year Order is irrelevant Start clock Write 1 to START in the RCR2 register 13.4.3 Reading the Time Figure 13.3 Reading the Time 342 Figure 13.3 amended (a) To read the time without using interrupts Disable the carry interrupt Clear the carry flag Read counter register Yes Carry flag = 1? No Read RCR1 and check CF Write 0 to CIE in RCR1 Write 0 to CF in RCR1 Note: Set AF to 1 so that alarm flag is not cleared. 13.4.4 Alarm Function Figure 13.4 Using the Alarm Function 343 Figure 13.4 amended Set alarm time Always reset, since the flag may have been set while the alarm time was being set (AF bit in RCR1 is cleared). Clear alarm flag 14.1 Feature 347 Description added The SCI has the following features. * Selectable from asynchronous or clock synchronous as the serial communications mode Rev. 4.00, 03/04, page xiv of xlvi Item 14.4.3 Clock Synchronous Operation Figure 14.17 Data Format in Clock Synchronous Communication 17.1.6 Port F Control Register (PFCR) Page 389 Revision (See Manual for Details) Figure 14.17 amended LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care 470 Bit table amended Bit 15 Bit Name -- Initial Value 1/0 R/W R Description Reserved When ASEMD0 = 0, this bit is always read as 0 and must only be written with 0. When ASEMD0 = 1, this bit is always read as 1 and must only be written with 1. 14 -- 0 R Reserved This bit is always read as 0 and must only be written with 0. 13 12 PF6MD1 PF6MD0 1/0 0 R/W R/W PF6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 11 10 PF5MD1 PF5MD0 1/0 0 R/W R/W PF5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 471 Bit 9 8 Bit Name PF4MD1 PF4MD0 Initial Value 1/0 0 R/W R/W R/W Description PF4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PF3MD1 PF3MD0 1/0 0 R/W R/W PF3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 5 4 PF2MD1 PF2MD0 1/0 0 R/W R/W PF2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 3 2 PF1MD1 PF1MD0 1/0 0 R/W R/W PF1 Mode 1 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PF0MD1 PF0MD0 1/0 0 R/W R/W PF0 Mode 1 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page xv of xlvi Item 17.1.7 Port G Control Register (PGCR) Page 472 Revision (See Manual for Details) Bit table amended Bit 11 10 Bit Name PG5MD1 PG5MD0 Initial Value 1 0 9 8 7 6 5 4 3 2 473 Bit 1 0 PG4MD1 PG4MD0 PG3MD1 PG3MD0 PG2MD1 PG2MD0 PG1MD1 PG1MD0 Bit Name PG0MD1 PG0MD0 1/0 0 1/0 0 1/0 0 1/0 0 Initial Value 1/0 0 18.5.2 Port E Data Register (PEDR) 485 Description amended PEDR is initialized to H'00 by a power-on reset, after which the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains its previous value in standby mode and sleep mode, and in a manual reset. 19.3.2 A/D Control/Status Register (ADCSR) 499 Bit 7 R/W amended (Before) R/(W)* (After) R/(W)*1 500 Bit 4 description amended MULTI 0 0 1 1 SCN 0 1 0 1 :Single mode :Single mode :Multi mode :Scan mode Note *2 added Bit 3 Clock Select 0: Conversion time = 536 states (maximum) 1: Conversion time = 266 states (maximum)*2 Notes: 1. Only 0 can be written to clear the flag. 2 The CKS value should be set so that the A/D conversion time is 16 s (minimum). Rev. 4.00, 03/04, page xvi of xlvi Item 19.4 Bus Master Interface Figure 19.2 A/D Data Register Access Operation (Reading H'AA40) Page 502 Revision (See Manual for Details) Figure 19.2 amended Lower byte read CPU (H'40) Bus interface Module internal data bus TEMP (H'40) Upper byte of A/D data register (H'AA) Lower byte of A/D data register (H'40) 19.6.3 Scan Mode (MULTI = 507 1, SCN = 1) Figure 19.7 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) 19.6.4 Input Sampling and A/D Conversion Time 508 Figure 19.7 amended Set*1 Clear*1 ADDRC*2 ADDRD*2 ADDRA*2 ADDRB*2 Notes: 1. Downward arrows indicate instruction executed by software. 2. Data is ignored during conversion. Description deleted In multi mode and scan mode, the values given in table 19.3 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 512 states when CKS = 0 or 256 states when CKS = 1. 19.9.1 Setting Analog Input Voltage 511 Description amended * Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVSS ANn AVCC (n = 0 to 3). * AVCC, Avss, Input Voltage: AVcc and AVss should be related as follows: AVcc = VccQ 0.2 V and AVss = Vss. 21.3.3 Boundary Scan Register (SDBSR) Table 21.2 This LSI's Pins and Boundary Scan Register Bits 21.4.1 TAP Controller 522 Table 21.2 amended Bit 171 I/O (Before) (blank) (After) OUT Bit 160 I/O (Before) OUT (After) Control 525 Note amended Note: ... The TDO is at high impedance, except with shift-DR (shiftSR) and shift-IR states. When TRST = 0, there is a transition to testlogic-reset asynchronously with TCK. Rev. 4.00, 03/04, page xvii of xlvi Item Section 22 Power-Down Modes Table 22.1 Power-Down Modes Page 531 Revision (See Manual for Details) Table 22.1 amended Mode Transition Conditions Canceling Procedure 1. Clear MSTP bit to 0 2. Power-on reset Module standby Set MSTP bit of function STBCR to 1 22.3.3 Module Standby Function 539 * Transition to Module Standby Function Description amended Setting the standby control register MSTP8 to MSTP4, MSTP2 to MSTP0 bits to 1 halts the supply of clocks to the corresponding onchip supporting modules. This function can be used to reduce the power consumption in normal mode and sleep mode. * Clearing the Module Standby Function Description amended The module standby function can be cleared by clearing the MSTP8 to MSTP4, MSTP2 to MSTP0 bits to 0, or by a power-on reset or manual reset. 23.1 Register Address Map 548 Address of SDMR amended (Before) H'FFFFD000 to H'FFFFEFFE (After) H'FFFFD000 to H'FFFFEFFF 24.3.4 Basic Timing Figure 24.16 Basic Bus Cycle (No Wait) 585 Figure 24.16 amended tBSD tBSD *5 tDAKD1 DACKn tDAKD2 Rev. 4.00, 03/04, page xviii of xlvi Item Figure 24.18 Basic Bus Cycle (External Wait) Page 587 Revision (See Manual for Details) Figure 24.18 amended tRDS1 D31 to D0 (read) tAH tWED tWED tRWH tWDH3 tWDD1 D31 to D0 (write) tBSD tBSD tWDH1 WEn (write) BS tDAKD1 DACKn tWTS tWTH tWTS tWTH tDAKD2 WAIT 24.3.6 Synchronous DRAM Timing Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 1) 24.3.9 H-UDI, AUD Related Pin Timing Figure 24.57 H-UDI Data Transfer Timing 24.3.11 AC Characteristics Measurement Conditions 599 Figure 24.30 replaced 619 Figure 24.57 amended tTDOD TDO 622 Description amended I/O signal reference level: VccQ/2 (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V) * Input pulse level ... B.1 Pin Functions Table B.1 Pin States during Resets, Power-Down States, and Bus-Released State 630 Table B.1 amended Reset Category Data bus Pin D[15:0] D[23:16]/PTA[7:0] D[31:24]/PTB[7:0] Power-On Manual Reset Reset Z Z Z I IP* 3 Power-Down Standby Z ZK* 3 Sleep IO IOP* 3 Bus Released Z ZP* 3 IP*3 ZK*3 IOP*3 ZP*3 B.3 Processing of Unused Pins 637 Description amended When EXTAL pin is not used EXTAL: Pull up to VccQ or Vss Rev. 4.00, 03/04, page xix of xlvi Item B.4 Pin States in Access to Each Address Space Table B.8 Pin States (Synchronous DRAM/Big Endian) Page 647 Revision (See Manual for Details) Table B.8 amended 32-Bit Bus Width Byte Access (Address 4n) Byte Access (Address 4n + 1) Byte Access (Address 4n + 2) Byte Access (Address 4n + 3) Word Access (Address 4n) Word Access (Address 4n + 2) Pin Longword Access D23 to D16 D31 to D24 Invalid data Valid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Invalid data Valid data Rev. 4.00, 03/04, page xx of xlvi Contents Section 1 Overview........................................................................................... 1.1 1.2 1.3 1.4 Feature............................................................................................................................... Block Diagram .................................................................................................................. Pin Assignment ................................................................................................................. Pin Function ...................................................................................................................... 1 1 3 4 6 Section 2 CPU................................................................................................... 13 2.1 Register Description.......................................................................................................... 2.1.1 Privileged Mode and Banks ................................................................................. 2.1.2 General Registers ................................................................................................. 2.1.3 System Registers.................................................................................................. 2.1.4 Control Registers ................................................................................................. Data Formats ..................................................................................................................... 2.2.1 Data Format in Registers...................................................................................... 2.2.2 Data Format in Memory....................................................................................... Instruction Features........................................................................................................... 2.3.1 Execution Environment........................................................................................ 2.3.2 Addressing Modes ............................................................................................... 2.3.3 Instruction Formats .............................................................................................. Instruction Set ................................................................................................................... 2.4.1 Instruction Set Classified by Function ................................................................. 2.4.2 Instruction Code Map .......................................................................................... Processor States and Processor Modes.............................................................................. 2.5.1 Processor States ................................................................................................... 2.5.2 Processor Modes .................................................................................................. 13 13 15 16 17 20 20 20 21 21 23 27 30 30 46 49 49 50 2.2 2.3 2.4 2.5 Section 3 Memory Management Unit (MMU) ................................................. 51 3.1 3.2 Role of MMU.................................................................................................................... 3.1.1 This LSI's MMU .................................................................................................. Register Description.......................................................................................................... 3.2.1 Page Table Entry Register High (PTEH) ............................................................. 3.2.2 Page Table Entry Register Low (PTEL) .............................................................. 3.2.3 The Translation Table Base Register (TTB) ........................................................ 3.2.4 The TLB Exception Address Register (TEA) ...................................................... 3.2.5 MMU Control Register (MMUCR) ..................................................................... TLB Functions .................................................................................................................. 3.3.1 Configuration of the TLB .................................................................................... 3.3.2 TLB Indexing....................................................................................................... 3.3.3 TLB Address Comparison ................................................................................... 51 53 56 56 57 57 57 58 59 59 61 62 3.3 Rev. 4.00, 03/04, page xxi of xlvi 3.4 3.5 3.6 3.7 3.3.4 Page Management Information............................................................................ MMU Functions................................................................................................................ 3.4.1 MMU Hardware Management ............................................................................. 3.4.2 MMU Software Management .............................................................................. 3.4.3 MMU Instruction (LDTLB)................................................................................. 3.4.4 Avoiding Synonym Problems .............................................................................. MMU Exceptions.............................................................................................................. 3.5.1 TLB Miss Exception ............................................................................................ 3.5.2 TLB Protection Violation Exception ................................................................... 3.5.3 TLB Invalid Exception ........................................................................................ 3.5.4 Initial Page Write Exception ................................................................................ 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for CPU Address Error)................................................. Configuration of the Memory-Mapped TLB .................................................................... 3.6.1 Address Array ...................................................................................................... 3.6.2 Data Array............................................................................................................ 3.6.3 Usage Examples................................................................................................... Usage Note........................................................................................................................ 3.7.1 Use of Instructions Manipulating MD and BL Bits in SR ................................... 3.7.2 Use of TLB .......................................................................................................... 64 65 65 65 66 67 69 69 70 71 72 74 76 76 76 78 78 78 79 Section 4 Exception Processing......................................................................... 81 4.1 Exception Processing Function ......................................................................................... 4.1.1 Exception Processing Flow.................................................................................. 4.1.2 Exception Processing Vector Addresses.............................................................. 4.1.3 Acceptance of Exceptions.................................................................................... 4.1.4 Exception Codes .................................................................................................. 4.1.5 Exception Request and BL Bit............................................................................. 4.1.6 Returning from Exception Processing ................................................................. Register Description.......................................................................................................... 4.2.1 Exception Event Register (EXPEVT).................................................................. 4.2.2 Interrupt Event Register (INTEVT)..................................................................... 4.2.3 Interrupt Event Register 2 (INTEVT2)................................................................ 4.2.4 TRAPA Exception Register (TRA) ..................................................................... Operation .......................................................................................................................... 4.3.1 Reset .................................................................................................................... 4.3.2 Interrupts.............................................................................................................. 4.3.3 General Exceptions .............................................................................................. Individual Exception Operations....................................................................................... 4.4.1 Resets................................................................................................................... 4.4.2 General Exceptions .............................................................................................. 4.4.3 Interrupts.............................................................................................................. Usage Note........................................................................................................................ 81 81 82 83 85 86 86 87 87 87 88 88 89 89 89 90 90 90 91 94 96 4.2 4.3 4.4 4.5 Rev. 4.00, 03/04, page xxii of xlvi Section 5 Cache................................................................................................. 99 5.1 5.2 Feature............................................................................................................................... 5.1.1 Cache Structure.................................................................................................... Register Description.......................................................................................................... 5.2.1 Cache Control Register (CCR) ............................................................................ 5.2.2 Cache Control Register 2 (CCR2)........................................................................ Operation........................................................................................................................... 5.3.1 Searching the Cache............................................................................................. 5.3.2 Read Access ......................................................................................................... 5.3.3 Prefetch Operation ............................................................................................... 5.3.4 Write Access ........................................................................................................ 5.3.5 Write-Back Buffer ............................................................................................... 5.3.6 Coherency of Cache and External Memory ......................................................... Memory-Mapped Cache.................................................................................................... 5.4.1 Address Array ...................................................................................................... 5.4.2 Data Array............................................................................................................ 5.4.3 Usage Examples................................................................................................... 99 99 101 101 102 104 104 105 106 106 106 107 107 107 108 110 5.3 5.4 Section 6 Interrupt Controller (INTC) .............................................................. 111 6.1 6.2 6.3 Feature............................................................................................................................... Input/Output Pin................................................................................................................ Interrupt Sources ............................................................................................................... 6.3.1 NMI Interrupts ..................................................................................................... 6.3.2 IRQ Interrupt........................................................................................................ 6.3.3 IRL Interrupts....................................................................................................... 6.3.4 On-Chip Peripheral Module Interrupts ................................................................ 6.3.5 Interrupt Exception Processing and Priority ........................................................ Register Description.......................................................................................................... 6.4.1 Interrupt Priority Registers A to E (IPRA to IPRE)............................................. 6.4.2 Interrupt Control Register 0 (ICR0)..................................................................... 6.4.3 Interrupt Control Register 1 (ICR1)..................................................................... 6.4.4 Interrupt Request Register 0 (IRR0) .................................................................... 6.4.5 Interrupt Request Register 1 (IRR1) .................................................................... 6.4.6 Interrupt Request Register 2 (IRR2) .................................................................... Operation........................................................................................................................... 6.5.1 Interrupt Sequence ............................................................................................... 6.5.2 Multiple Interrupts ............................................................................................... Interrupt Response Time ................................................................................................... 111 113 113 113 114 115 116 117 121 121 122 123 125 127 128 129 129 131 132 6.4 6.5 6.6 Section 7 User Break Controller ....................................................................... 135 7.1 7.2 Feature............................................................................................................................... 135 Register Description.......................................................................................................... 137 7.2.1 Break Address Register A (BARA) ..................................................................... 137 Rev. 4.00, 03/04, page xxiii of xlvi 7.3 7.4 7.2.2 Break Address Mask Register A (BAMRA)........................................................ 7.2.3 Break Bus Cycle Register A (BBRA).................................................................. 7.2.4 Break Address Register B (BARB) ..................................................................... 7.2.5 Break Address Mask Register B (BAMRB) ........................................................ 7.2.6 Break Data Register B (BDRB) ........................................................................... 7.2.7 Break Data Mask Register B (BDMRB).............................................................. 7.2.8 Break Bus Cycle Register B (BBRB) .................................................................. 7.2.9 Break Control Register (BRCR) .......................................................................... 7.2.10 Execution Times Break Register (BETR)............................................................ 7.2.11 Branch Source Register (BRSR).......................................................................... 7.2.12 Branch Destination Register (BRDR).................................................................. 7.2.13 Break ASID Register A (BASRA)....................................................................... 7.2.14 Break ASID Register B (BASRB) ....................................................................... Operation .......................................................................................................................... 7.3.1 Flow of the User Break Operation ....................................................................... 7.3.2 Break on Instruction Fetch Cycle......................................................................... 7.3.3 Break by Data Access Cycle................................................................................ 7.3.4 Sequential Break .................................................................................................. 7.3.5 Value of Saved Program Counter ........................................................................ 7.3.6 PC Trace .............................................................................................................. 7.3.7 Usage Examples................................................................................................... Usage Note........................................................................................................................ 138 138 139 140 140 140 141 142 145 146 147 147 148 148 148 149 149 150 150 151 153 156 Section 8 Bus State Controller (BSC) ...............................................................159 8.1 8.2 8.3 8.4 Feature .............................................................................................................................. Input/Output Pin................................................................................................................ Area Overview .................................................................................................................. 8.3.1 PCMCIA Support ................................................................................................ Register Description.......................................................................................................... 8.4.1 Bus Control Register 1 (BCR1) ........................................................................... 8.4.2 Bus Control Register 2 (BCR2) ........................................................................... 8.4.3 Wait State Control Register 1 (WCR1)................................................................ 8.4.4 Wait State Control Register 2 (WCR2)................................................................ 8.4.5 Individual Memory Control Register (MCR) ...................................................... 8.4.6 PCMCIA Control Register (PCR)........................................................................ 8.4.7 Synchronous DRAM Mode Register (SDMR) .................................................... 8.4.8 Refresh Timer Control/Status Register (RTCSR)................................................ 8.4.9 Refresh Timer Counter (RTCNT)........................................................................ 8.4.10 Refresh Time Constant Register (RTCOR) ......................................................... 8.4.11 Refresh Count Register (RFCR) .......................................................................... Operation .......................................................................................................................... 8.5.1 Endian/Access Size and Data Alignment............................................................. 8.5.2 Description of Areas ............................................................................................ 159 161 162 165 169 169 172 174 177 180 185 188 188 191 191 192 192 192 197 8.5 Rev. 4.00, 03/04, page xxiv of xlvi 8.5.3 8.5.4 8.5.5 8.5.6 8.5.7 8.5.8 8.5.9 Basic Interface ..................................................................................................... Synchronous DRAM Interface............................................................................. Burst ROM Interface............................................................................................ PCMCIA Interface ............................................................................................... Waits between Access Cycles.............................................................................. Bus Arbitration..................................................................................................... Bus Pull-Up.......................................................................................................... 200 205 227 229 239 240 240 Section 9 Direct Memory Access Controller (DMAC) .................................... 243 9.1 9.2 9.3 Feature............................................................................................................................... Input/Output Pin................................................................................................................ Register Description.......................................................................................................... 9.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) ................................ 9.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3)........................ 9.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3)............... 9.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3)......................... 9.3.5 DMA Operation Register (DMAOR)................................................................... Operation........................................................................................................................... 9.4.1 DMA Transfer Flow............................................................................................. 9.4.2 DMA Transfer Requests ...................................................................................... 9.4.3 Channel Priority ................................................................................................... 9.4.4 DMA Transfer Types ........................................................................................... 9.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing .......................... 9.4.6 Source Address Reload Function ......................................................................... 9.4.7 DMA Transfer Ending Conditions....................................................................... Compare Match Timer (CMT).......................................................................................... 9.5.1 Feature ................................................................................................................. 9.5.2 Register Description............................................................................................. 9.5.3 Operation ............................................................................................................. Examples of Use ............................................................................................................... 9.6.1 Example of DMA Transfer between A/D Converter and External Memory (Address Reload on) ............................................................................................ 9.6.2 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address on) ........................................................................................... Cautions ............................................................................................................................ 243 245 245 246 246 247 247 253 255 255 257 259 262 274 278 280 282 282 283 285 287 287 288 290 9.4 9.5 9.6 9.7 Section 10 Clock Pulse Generator (CPG)......................................................... 291 10.1 10.2 10.3 10.4 Feature............................................................................................................................... Input/Output Pin................................................................................................................ Clock Operating Modes .................................................................................................... Register Description.......................................................................................................... 10.4.1 Frequency Control Register (FRQCR)................................................................. 10.5 Operation........................................................................................................................... 291 294 294 298 298 300 Rev. 4.00, 03/04, page xxv of xlvi 10.5.1 Changing the Multiplication Rate ........................................................................ 300 10.5.2 Changing the Division Ratio................................................................................ 300 10.6 Usage Note........................................................................................................................ 301 Section 11 Watchdog Timer (WDT) .................................................................303 11.1 Feature .............................................................................................................................. 11.2 Register Description.......................................................................................................... 11.2.1 Watchdog Timer Counter (WTCNT)................................................................... 11.2.2 Watchdog Timer Control/Status Register (WTCSR)........................................... 11.2.3 Notes on Register Access..................................................................................... 11.3 Operation .......................................................................................................................... 11.3.1 Canceling Software Standbys .............................................................................. 11.3.2 Changing the Frequency ...................................................................................... 11.3.3 Using Watchdog Timer Mode ............................................................................. 11.3.4 Using Interval Timer Mode ................................................................................. 303 304 304 304 306 307 307 307 308 308 Section 12 Timer Unit (TMU)...........................................................................309 12.1 Feature .............................................................................................................................. 12.2 Input/Output Pin................................................................................................................ 12.3 Register Description.......................................................................................................... 12.3.1 Timer Output Control Register (TOCR) .............................................................. 12.3.2 Timer Start Register (TSTR) ............................................................................... 12.3.3 Timer Control Registers 0 to 2 (TCR_0 to TCR_2) ............................................ 12.3.4 Timer Constant Registers 0 to 2 (TCOR_0 to TCOR_2)..................................... 12.3.5 Timer Counters 0 to 2 (TCNT_0 to TCNT_2)..................................................... 12.3.6 Input Capture Register 2 (TCPR_2) .................................................................... 12.4 Operation .......................................................................................................................... 12.4.1 Counter Operation................................................................................................ 12.4.2 Input Capture Function ........................................................................................ 12.5 Interrupts........................................................................................................................... 12.5.1 Status Flag Set Timing......................................................................................... 12.5.2 Status Flag Clear Timing ..................................................................................... 12.5.3 Interrupt Sources and Priorities ........................................................................... 12.6 Usage Note........................................................................................................................ 12.6.1 Writing to Registers ............................................................................................. 12.6.2 Reading Registers ................................................................................................ 309 311 311 312 313 314 317 318 318 319 319 322 323 323 323 324 324 324 324 Section 13 Realtime Clock (RTC).....................................................................325 13.1 Feature .............................................................................................................................. 13.2 Input/Output Pin................................................................................................................ 13.3 Register Description.......................................................................................................... 13.3.1 64-Hz Counter (R64CNT) ................................................................................... 13.3.2 Second Counter (RSECCNT) .............................................................................. Rev. 4.00, 03/04, page xxvi of xlvi 325 327 327 328 328 13.3.3 Minute Counter (RMINCNT) .............................................................................. 13.3.4 Hour Counter (RHRCNT).................................................................................... 13.3.5 Day of the Week Counter (RWKCNT)................................................................ 13.3.6 Date Counter (RDAYCNT) ................................................................................. 13.3.7 Month Counter (RMONCNT) ............................................................................. 13.3.8 Year Counter (RYRCNT) .................................................................................... 13.3.9 Second Alarm Register (RSECAR) ..................................................................... 13.3.10 Minute Alarm Register (RMINAR) ..................................................................... 13.3.11 Hour Alarm Register (RHRAR)........................................................................... 13.3.12 Day of the Week Alarm Register (RWKAR)....................................................... 13.3.13 Date Alarm Register (RDAYAR) ........................................................................ 13.3.14 Month Alarm Register (RMONAR) .................................................................... 13.3.15 RTC Control Register 1 (RCR1).......................................................................... 13.3.16 RTC Control Register 2 (RCR2).......................................................................... 13.4 RTC Operation.................................................................................................................. 13.4.1 Initial Settings of Registers after Power-On ........................................................ 13.4.2 Setting the Time................................................................................................... 13.4.3 Reading the Time................................................................................................. 13.4.4 Alarm Function .................................................................................................... 13.4.5 Crystal Oscillator Circuit ..................................................................................... 13.5 Usage Note........................................................................................................................ 13.5.1 Register Writing during RTC Count .................................................................... 13.5.2 Use of Realtime Clock (RTC) Periodic Interrupts ............................................... 13.5.3 Timing for Setting ADJ Bit in RCR2................................................................... 329 329 330 331 331 332 332 333 334 335 336 337 338 339 341 341 341 342 343 344 345 345 345 346 Section 14 Serial Communication Interface (SCI) ........................................... 347 14.1 Feature............................................................................................................................... 347 14.2 Input/Output Pin................................................................................................................ 351 14.3 Register Description.......................................................................................................... 351 14.3.1 Receive Shift Register (SCRSR).......................................................................... 352 14.3.2 Receive Data Register (SCRDR) ......................................................................... 352 14.3.3 Transmit Shift Register (SCTSR) ........................................................................ 352 14.3.4 Transmit Data Register (SCTDR)........................................................................ 352 14.3.5 Serial Mode Register (SCSMR)........................................................................... 353 14.3.6 Serial Control Register (SCSCR)......................................................................... 355 14.3.7 Serial Status Register (SCSSR)............................................................................ 359 14.3.8 SC Port Control Register (SCPCR)...................................................................... 364 14.3.9 SC Port Data Register (SCPDR) .......................................................................... 365 14.3.10 Bit Rate Register (SCBRR).................................................................................. 366 14.4 Operation........................................................................................................................... 372 14.4.1 Operation in Asynchronous Mode ....................................................................... 374 14.4.2 Multiprocessor Communication........................................................................... 382 14.4.3 Clock Synchronous Operation ............................................................................. 389 Rev. 4.00, 03/04, page xxvii of xlvi 14.5 SCI Interrupt Sources........................................................................................................ 396 14.6 Usage Note........................................................................................................................ 397 Section 15 Smart Card Interface........................................................................401 15.1 Feature .............................................................................................................................. 15.2 Input/Output Pin................................................................................................................ 15.3 Register Description.......................................................................................................... 15.3.1 Smart Card Mode Register (SCSCMR) ............................................................... 15.3.2 Serial Status Register (SCSSR)............................................................................ 15.4 Operation .......................................................................................................................... 15.4.1 Overview.............................................................................................................. 15.4.2 Pin Connections ................................................................................................... 15.4.3 Data Format ......................................................................................................... 15.4.4 Register Settings .................................................................................................. 15.4.5 Clock.................................................................................................................... 15.4.6 Data Transmission and Reception........................................................................ 15.5 Usage Note........................................................................................................................ 401 402 402 403 404 406 406 406 407 408 410 412 416 Section 16 Serial Communication Interface with FIFO (SCIF) ........................421 16.1 Feature .............................................................................................................................. 16.2 Input/Output Pin................................................................................................................ 16.3 Register Description.......................................................................................................... 16.3.1 Receive Shift Register 2 (SCRSR2)..................................................................... 16.3.2 Receive FIFO Data Register 2 (SCFRDR2) ........................................................ 16.3.3 Transmit Shift Register 2 (SCTSR2) ................................................................... 16.3.4 Transmit FIFO Data Register 2 (SCFTDR2) ....................................................... 16.3.5 Serial Mode Register 2 (SCSMR2)...................................................................... 16.3.6 Serial Control Register 2 (SCSCR2).................................................................... 16.3.7 Serial Status Register 2 (SCSSR2)....................................................................... 16.3.8 Bit Rate Register 2 (SCBRR2) ............................................................................ 16.3.9 FIFO Control Register 2 (SCFCR2) .................................................................... 16.3.10 FIFO Data Count Set Register 2 (SCFDR2) ........................................................ 16.3.11 SC Port Control Register (SCPCR) ..................................................................... 16.3.12 SC Port Data Register (SCPDR).......................................................................... 16.4 Operation .......................................................................................................................... 16.4.1 Serial Operation ................................................................................................... 16.4.2 SCIF Interrupts .................................................................................................... 16.5 Usage Notes ...................................................................................................................... 421 425 425 426 426 426 426 426 429 431 439 443 445 445 445 446 447 456 457 Section 17 Pin Function Controller (PFC) ........................................................459 17.1 Register Description.......................................................................................................... 462 17.1.1 Port A Control Register (PACR) ......................................................................... 463 17.1.2 Port B Control Register (PBCR).......................................................................... 464 Rev. 4.00, 03/04, page xxviii of xlvi 17.1.3 Port C Control Register (PCCR) .......................................................................... 17.1.4 Port D Control Register (PDCR).......................................................................... 17.1.5 Port E Control Register (PECR) .......................................................................... 17.1.6 Port F Control Register (PFCR)........................................................................... 17.1.7 Port G Control Register (PGCR).......................................................................... 17.1.8 Port H Control Register (PHCR).......................................................................... 17.1.9 Port J Control Register (PJCR) ............................................................................ 17.1.10 SC Port Control Register (SCPCR)...................................................................... 466 467 469 470 472 473 475 476 Section 18 I/O Ports .......................................................................................... 479 18.1 Port A................................................................................................................................ 18.1.1 Register Description............................................................................................. 18.1.2 Port A Data Register (PADR) .............................................................................. 18.2 Port B ................................................................................................................................ 18.2.1 Register Description............................................................................................. 18.2.2 Port B Data Register (PBDR) .............................................................................. 18.3 Port C ................................................................................................................................ 18.3.1 Register Description............................................................................................. 18.3.2 Port C Data Register (PCDR) .............................................................................. 18.4 Port D................................................................................................................................ 18.4.1 Register Description............................................................................................. 18.4.2 Port D Data Register (PDDR) .............................................................................. 18.5 Port E ................................................................................................................................ 18.5.1 Register Description............................................................................................. 18.5.2 Port E Data Register (PEDR)............................................................................... 18.6 Port F................................................................................................................................. 18.6.1 Register Description............................................................................................. 18.6.2 Port F Data Register (PFDR) ............................................................................... 18.7 Port G................................................................................................................................ 18.7.1 Register Description............................................................................................. 18.7.2 Port G Data Register (PGDR) .............................................................................. 18.8 Port H................................................................................................................................ 18.8.1 Register Description............................................................................................. 18.8.2 Port H Data Register (PHDR) .............................................................................. 18.9 Port J ................................................................................................................................. 18.9.1 Register Description............................................................................................. 18.9.2 Port J Data Register (PJDR)................................................................................. 18.10 SC Port.............................................................................................................................. 18.10.1 Register Description............................................................................................. 18.10.2 SC Port Data Register (SCPDR) .......................................................................... 479 479 479 480 481 481 482 482 482 483 484 484 485 485 485 486 487 487 488 488 488 489 490 490 491 491 492 493 493 493 Section 19 A/D Converter (ADC)..................................................................... 495 19.1 Features ............................................................................................................................. 495 Rev. 4.00, 03/04, page xxix of xlvi 19.2 Input/Output Pin................................................................................................................ 19.3 Register Description.......................................................................................................... 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) ............................................. 19.3.2 A/D Control/Status Register (ADCSR) ............................................................... 19.3.3 A/D Control Register (ADCR) ............................................................................ 19.4 Bus Master Interface ......................................................................................................... 19.5 Access Size of A/D Data Register .................................................................................... 19.5.1 Word Access ........................................................................................................ 19.5.2 Longword Access ................................................................................................ 19.6 Operation .......................................................................................................................... 19.6.1 Single Mode (MULTI = 0) .................................................................................. 19.6.2 Multi Mode (MULTI = 1, SCN = 0).................................................................... 19.6.3 Scan Mode (MULTI = 1, SCN = 1)..................................................................... 19.6.4 Input Sampling and A/D Conversion Time ......................................................... 19.6.5 External Trigger Input Timing............................................................................. 19.7 Interrupt Requests ............................................................................................................. 19.8 Definitions of A/D Conversion Accuracy......................................................................... 19.9 Usage Note........................................................................................................................ 19.9.1 Setting Analog Input Voltage .............................................................................. 19.9.2 Processing of Analog Input Pins.......................................................................... 19.9.3 Access Size and Read Data.................................................................................. 497 497 498 499 501 501 503 503 503 503 503 505 506 508 509 509 510 511 511 511 512 Section 20 D/A Converter (DAC) .....................................................................513 20.1 Feature .............................................................................................................................. 20.2 Input/Output Pin................................................................................................................ 20.3 Register Description.......................................................................................................... 20.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1)............................................ 20.3.2 D/A Control Register (DACR) ............................................................................ 20.4 Operation .......................................................................................................................... 513 514 514 514 515 516 Section 21 User Debugging Interface (H-UDI).................................................517 21.1 Feature .............................................................................................................................. 21.2 Input/Output Pin................................................................................................................ 21.3 Register Description.......................................................................................................... 21.3.1 Bypass Register (SDBPR) ................................................................................... 21.3.2 Instruction Register (SDIR) ................................................................................. 21.3.3 Boundary Scan Register (SDBSR) ...................................................................... 21.4 H-UDI Operations............................................................................................................. 21.4.1 TAP Controller .................................................................................................... 21.4.2 Reset Configuration ............................................................................................. 21.4.3 H-UDI Reset ........................................................................................................ 21.4.4 H-UDI Interrupt ................................................................................................... 21.4.5 Bypass.................................................................................................................. Rev. 4.00, 03/04, page xxx of xlvi 518 518 519 519 519 520 525 525 526 527 527 527 21.4.6 Using H-UDI to Recover from Sleep Mode........................................................ 21.5 Boundary Scan .................................................................................................................. 21.5.1 Supported Instructions ......................................................................................... 21.5.2 Notes for Boundary Scan ..................................................................................... 21.6 Usage Note........................................................................................................................ 21.7 Advanced User Debugger (AUD) ..................................................................................... 527 528 528 529 529 529 Section 22 Power-Down Modes ....................................................................... 531 22.1 Input/Output Pin................................................................................................................ 22.2 Register Description.......................................................................................................... 22.2.1 Standby Control Register (STBCR)..................................................................... 22.2.2 Standby Control Register 2 (STBCR2)................................................................ 22.3 Operation........................................................................................................................... 22.3.1 Sleep Mode .......................................................................................................... 22.3.2 Software Standby Mode....................................................................................... 22.3.3 Module Standby Function.................................................................................... 22.3.4 Timing of STATUS Pin Changes ........................................................................ 22.3.5 Hardware Standby Function................................................................................. 532 532 532 534 535 535 536 539 540 544 Section 23 List of Registers .............................................................................. 547 23.1 Register Address Map ....................................................................................................... 547 23.2 Register Bits...................................................................................................................... 553 23.3 Register States in Processing Mode .................................................................................. 564 Section 24 Electrical Characteristics ................................................................ 569 24.1 Absolute Maximum Ratings ............................................................................................. 24.2 DC Characteristics ............................................................................................................ 24.3 AC Characteristics ............................................................................................................ 24.3.1 Clock Timing ....................................................................................................... 24.3.2 Control Signal Timing ......................................................................................... 24.3.3 AC Bus Timing .................................................................................................... 24.3.4 Basic Timing........................................................................................................ 24.3.5 Burst ROM Timing .............................................................................................. 24.3.6 Synchronous DRAM Timing ............................................................................... 24.3.7 PCMCIA Timing ................................................................................................. 24.3.8 Peripheral Module Signal Timing........................................................................ 24.3.9 H-UDI, AUD Related Pin Timing ....................................................................... 24.3.10 A/D Converter Timing ......................................................................................... 24.3.11 AC Characteristics Measurement Conditions ...................................................... 24.3.12 Delay Time Variation Due to Load Capacitance ................................................. 24.4 A/D Converter Characteristics .......................................................................................... 24.5 D/A Converter Characteristics .......................................................................................... 569 571 574 574 580 583 585 588 591 608 615 618 620 622 623 624 624 Rev. 4.00, 03/04, page xxxi of xlvi Appendix A. B. .........................................................................................................625 625 629 629 633 637 638 653 654 C. D. Equivalent Circuits of I/O Buffer for Each Pin................................................................. Pin Functions .................................................................................................................... B.1 Pin Functions ....................................................................................................... B.2 Pin Specifications ................................................................................................ B.3 Processing of Unused Pins................................................................................... B.4 Pin States in Access to Each Address Space........................................................ Product Lineup.................................................................................................................. Package Dimensions ......................................................................................................... Index .........................................................................................................657 Rev. 4.00, 03/04, page xxxii of xlvi Figures Section 1 Figure 1.1 Figure 1.2 Figure 1.3 Section 2 Figure 2.1 Figure 2.2 Figure 2.3 Figure 2.4 Figure 2.5 Figure 2.6 Overview SH7706 Block Diagram ................................................................................................3 Pin Assignment (FP-176C)............................................................................................4 Pin Assignment (TBP-208A).........................................................................................5 CPU Register Configuration ................................................................................................14 General Registers.........................................................................................................15 System Registers .........................................................................................................16 Control Registers .........................................................................................................17 Data Format in Memory ..............................................................................................21 Processor State Transitions..........................................................................................49 Section 3 Memory Management Unit (MMU) Figure 3.1 MMU Functions ..........................................................................................................52 Figure 3.2 Virtual Address Space Mapping..................................................................................54 Figure 3.3 Overall Configuration of the TLB ...............................................................................59 Figure 3.4 Virtual Address and TLB Structure.............................................................................60 Figure 3.5 TLB Indexing (IX = 1) ................................................................................................61 Figure 3.6 TLB Indexing (IX = 0) ................................................................................................61 Figure 3.7 Objects of Address Comparison ..................................................................................63 Figure 3.8 Operation of LDTLB Instruction.................................................................................66 Figure 3.9 Synonym Problem .......................................................................................................68 Figure 3.10 MMU Exception Generation Flowchart ....................................................................73 Figure 3.11 MMU Exception Signals in Instruction Fetch ...........................................................74 Figure 3.12 MMU Exception Signals in Data Access ..................................................................75 Figure 3.13 Specifying Address and Data for Memory-Mapped TLB Access .............................77 Section 4 Exception Processing Figure 4.1 Vector Addresses.........................................................................................................82 Figure 4.2 Example of Acceptance Order of General Exceptions ................................................84 Section 5 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Section 6 Figure 6.1 Figure 6.2 Figure 6.3 Cache Cache Structure ...........................................................................................................99 Cache Search Scheme (Normal Mode)......................................................................105 Write-Back Buffer Configuration..............................................................................106 Specifying Address and Data for Memory-Mapped Cache Access...........................109 Interrupt Controller (INTC) INTC Block Diagram ................................................................................................112 Example of IRL Interrupt Connection.......................................................................115 Interrupt Operation Flowchart ...................................................................................130 Rev. 4.00, 03/04, page xxxiii of xlvi Figure 6.4 Example of Pipeline Operations when IRL Interrupt is Accepted ............................ 134 Section 7 User Break Controller Figure 7.1 Block Diagram of User Break Controller.................................................................. 136 Section 8 Bus State Controller (BSC) Figure 8.1 BSC Functional Block Diagram................................................................................ 160 Figure 8.2 Corresponding to Logical Address Space and Physical Address Space.................... 163 Figure 8.3 Physical Space Allocation ......................................................................................... 164 Figure 8.4 PCMCIA Space Allocation ....................................................................................... 166 Figure 8.5 Basic Timing of Basic Interface ................................................................................ 200 Figure 8.6 Example of 32-Bit Data-Width Static RAM Connection .......................................... 201 Figure 8.7 Example of 16-Bit Data-Width Static RAM Connection .......................................... 202 Figure 8.8 Example of 8-Bit Data-Width Static RAM Connection ............................................ 202 Figure 8.9 Basic Interface Wait Timing (Software Wait Only) .................................................. 203 Figure 8.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1).......................................... 204 Figure 8.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width)........... 206 Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) .............................. 207 Figure 8.13 Basic Timing for Synchronous DRAM Burst Read ................................................ 210 Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing ................................. 211 Figure 8.15 Basic Timing for Synchronous DRAM Single Read............................................... 212 Figure 8.16 Basic Timing for Synchronous DRAM Burst Write ............................................... 213 Figure 8.17 Basic Timing for Synchronous DRAM Single Write.............................................. 214 Figure 8.18 Burst Read Timing (No Precharge) ......................................................................... 216 Figure 8.19 Burst Read Timing (Same Row Address) ............................................................... 217 Figure 8.20 Burst Read Timing (Different Row Addresses) ...................................................... 218 Figure 8.21 Burst Write Timing (No Precharge) ........................................................................ 219 Figure 8.22 Burst Write Timing (Same Row Address)............................................................... 220 Figure 8.23 Burst Write Timing (Different Row Addresses) ..................................................... 221 Figure 8.24 Auto-Refresh Operation .......................................................................................... 222 Figure 8.25 Synchronous DRAM Auto-Refresh Timing............................................................ 223 Figure 8.26 Synchronous DRAM Self-Refresh Timing ............................................................. 224 Figure 8.27 Synchronous DRAM Mode Write Timing .............................................................. 226 Figure 8.28 Burst ROM Wait Access Timing............................................................................. 228 Figure 8.29 Burst ROM Basic Access Timing ........................................................................... 229 Figure 8.30 PCMCIA Space Allocation ..................................................................................... 230 Figure 8.31 Example of PCMCIA Interface ............................................................................... 231 Figure 8.32 Basic Timing for PCMCIA Memory Card Interface ............................................... 232 Figure 8.33 Wait Timing for PCMCIA Memory Card Interface ................................................ 233 Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access ......................... 234 Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access .......................... 235 Figure 8.36 Basic Timing for PCMCIA I/O Card Interface ....................................................... 236 Figure 8.37 Wait Timing for PCMCIA I/O Card Interface ........................................................ 237 Rev. 4.00, 03/04, page xxxiv of xlvi Figure 8.38 Figure 8.39 Figure 8.40 Figure 8.41 Figure 8.42 Section 9 Figure 9.1 Figure 9.2 Figure 9.3 Figure 9.4 Figure 9.5 Figure 9.6 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface ...............................238 Waits between Access Cycles .................................................................................239 Pins A25 to A0 Pull-Up Timing ..............................................................................240 Pins D31 to D0 Pull-Up Timing (Read Cycle) ........................................................241 Pins D31 to D0 Pull-Up Timing (Write Cycle) .......................................................241 Direct Memory Access Controller (DMAC) DMAC Block Diagram..............................................................................................244 DMAC Transfer Flowchart .......................................................................................256 Round-Robin Mode ...................................................................................................260 Changes in Channel Priority in Round-Robin Mode.................................................261 Operation in the Direct Address Mode in the Dual Address Mode ...........................263 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) .................................................................264 Figure 9.7 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) ..................................265 Figure 9.8 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary Memory)..............................265 Figure 9.9 Operation in the Indirect Address mode in the Dual Address Mode (When the External Memory Space has a 16-bit Width) ..........................................267 Figure 9.10 Example of Transfer Timing in the Indirect Address Mode in the Dual Address Mode.......................................................................................268 Figure 9.11 Data Flow in the Single Address Mode...................................................................269 Figure 9.12 Example of DMA Transfer Timing in the Single Address Mode............................270 Figure 9.13 Example of DMA Transfer Timing in the Single Address Mode (16- Byte Transfer, External Memory Space (Ordinary Memory) -> External Device with DACK) .................................................................................271 Figure 9.14 DMA Transfer Example in the Cycle-Steal Mode ..................................................271 Figure 9.15 DMA Transfer Example in the Burst Mode ............................................................272 Figure 9.16 Bus State when Multiple Channels are Operating (Priority Level is Round-robin Mode) ......................................................................274 Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) ........................................276 Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) ........................................276 Figure 9.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) ..................................................................................................................276 Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) ....277 Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) .........................................277 Figure 9.22 Burst Mode, Level Input..........................................................................................277 Figure 9.23 Burst Mode, Edge Input ..........................................................................................278 Figure 9.24 Source Address Reload Function Diagram..............................................................278 Rev. 4.00, 03/04, page xxxv of xlvi Figure 9.25 Figure 9.26 Figure 9.27 Figure 9.28 Figure 9.29 Figure 9.30 Section 10 Figure 10.1 Figure 10.2 Figure 10.3 Timing Chart of Source Address Reload Function.................................................. 279 CMT Block Diagram............................................................................................... 282 Counter Operation ................................................................................................... 285 Count Timing .......................................................................................................... 285 CMF Set Timing...................................................................................................... 286 Timing of CMF Clear by the CPU .......................................................................... 286 Clock Pulse Generator (CPG) Block Diagram of Clock Pulse Generator ............................................................... 292 Points for Attention when Using Crystal Oscillator ................................................ 301 Points for Attention when Using PLL Oscillator Circuit ........................................ 302 Section 11 Watchdog Timer (WDT) Figure 11.1 Block Diagram of the WDT .................................................................................... 303 Figure 11.2 Writing to WTCNT and WTCSR............................................................................ 306 Timer Unit(TMU) TMU Block Diagram............................................................................................... 310 Setting the Count Operation .................................................................................... 319 Auto-Reload Count Operation................................................................................. 320 Count Timing when Internal Clock Is Operating .................................................... 320 Count Timing when External Clock is Operating (Both Edges Detected) .............. 321 Count Timing when On-Chip RTC Clock Is Operating .......................................... 321 Operation Timing when Using the Input Capture Function (Using TCLK Rising Edge) ..................................................................................... 322 Figure 12.8 UNF Set Timing ...................................................................................................... 323 Figure 12.9 Status Flag Clear Timing......................................................................................... 323 Section 13 Figure 13.1 Figure 13.2 Figure 13.3 Figure 13.4 Figure 13.5 Figure 13.6 Section 14 Figure 14.1 Figure 14.2 Figure 14.3 Figure 14.4 Figure 14.5 Figure 14.6 Figure 14.7 Figure 14.8 Figure 14.9 Realtime Clock (RTC) RTC Block Diagram................................................................................................ 326 Setting the Time ...................................................................................................... 341 Reading the Time .................................................................................................... 342 Using the Alarm Function ....................................................................................... 343 Example of Crystal Oscillator Circuit Connection .................................................. 344 Using Periodic Interrupt Function ........................................................................... 345 Serial Communication Interface (SCI) SCI Block Diagram ................................................................................................. 348 SCPT[1]/SCK0 Pin.................................................................................................. 349 SCPT[0]/TxD0 Pin .................................................................................................. 350 SCPT[0]/RxD0 Pin.................................................................................................. 350 Data Format in Asynchronous Communication ...................................................... 374 Output Clock and Serial Data Timing (Asynchronous Mode) ................................ 376 Sample Flowchart for SCI Initialization.................................................................. 376 Sample Flowchart for Transmitting Serial Data ...................................................... 377 SCI Transmit Operation in Asynchronous Mode .................................................... 378 Section 12 Figure 12.1 Figure 12.2 Figure 12.3 Figure 12.4 Figure 12.5 Figure 12.6 Figure 12.7 Rev. 4.00, 03/04, page xxxvi of xlvi Figure 14.10 Figure 14.11 Figure 14.12 Figure 14.13 Figure 14.14 Figure 14.15 Figure 14.16 Figure 14.17 Figure 14.18 Figure 14.19 Figure 14.20 Figure 14.21 Figure 14.22 Figure 14.23 Figure 14.24 Sample Flowchart for Receiving Serial Data ........................................................379 SCI Receive Operation ..........................................................................................382 Communication Among Processors Using Multiprocessor Format ......................383 Sample Flowchart for Transmitting Multiprocessor Serial Data ...........................384 SCI Multiprocessor Transmit Operation................................................................385 Sample Flowchart for Receiving Multiprocessor Serial Data ...............................386 Example of SCI Receive Operation.......................................................................388 Data Format in Clock Synchronous Communication ............................................389 Sample Flowchart for SCI Initialization................................................................390 Sample Flowchart for Serial Transmitting.............................................................391 Example of SCI Transmit Operation .....................................................................392 Sample Flowchart for Serial Data Receiving ........................................................393 Example of SCI Receive Operation.......................................................................394 Sample Flowchart for Serial Data Transmitting/Receiving...................................395 Receive Data Sampling Timing in Asynchronous Mode ......................................398 Section 15 Smart Card Interface Figure 15.1 Smart Card Interface Block Diagram ......................................................................401 Figure 15.2 Pin Connection Diagram for the Smart Card Interface............................................407 Figure 15.3 Data Format for Smart Card Interface .....................................................................407 Figure 15.4 Waveform of Start Character...................................................................................409 Figure 15.5 Initialization Flowchart (Example)..........................................................................413 Figure 15.6 Transmission Flowchart ..........................................................................................414 Figure 15.7 Reception Flowchart (Example) ..............................................................................415 Figure 15.8 Receive Data Sampling Timing in Smart Card Mode .............................................417 Figure 15.9 Retransmission in SCI Receive Mode .....................................................................418 Figure 15.10 Retransmission in SCI Transmit Mode..................................................................419 Serial Communication Interface with FIFO (SCIF) SCIF Block Diagram ...............................................................................................422 SCPT[3]/SCK2 Pin..................................................................................................423 SCPT[2]/TxD2 Pin ..................................................................................................424 SCPT[2]/RxD2 Pin..................................................................................................424 Sample SCIF Initialization Flowchart .....................................................................449 Sample Serial Transmission Flowchart ...................................................................450 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) ..........................................................................................................452 Figure 16.8 Example of Operation Using Modem Control (CTS2)............................................452 Figure 16.9 Sample Serial Reception Flowchart (1)...................................................................453 Figure 16.10 Sample Serial Reception Flowchart (2) .................................................................454 Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) ........................................................................................................455 Figure 16.12 Example of Operation Using Modem Control (RTS2)..........................................455 Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode ......................................458 Rev. 4.00, 03/04, page xxxvii of xlvi Section 16 Figure 16.1 Figure 16.2 Figure 16.3 Figure 16.4 Figure 16.5 Figure 16.6 Figure 16.7 Section 18 I/O Ports Figure 18.1 Port A ...................................................................................................................... 479 Figure 18.2 Port B ...................................................................................................................... 480 Figure 18.3 Port C ...................................................................................................................... 482 Figure 18.4 Port D ...................................................................................................................... 483 Figure 18.5 Port E....................................................................................................................... 485 Figure 18.6 Port F....................................................................................................................... 486 Figure 18.7 Port G ...................................................................................................................... 488 Figure 18.8 Port H ...................................................................................................................... 489 Figure 18.9 Port J........................................................................................................................ 491 Figure 18.10 SC Port .................................................................................................................. 493 Section 19 Figure 19.1 Figure 19.2 Figure 19.3 Figure 19.4 Figure 19.5 Figure 19.6 A/D Converter (ADC) A/D Converter Block Diagram................................................................................ 496 A/D Data Register Access Operation (Reading H'AA40) ....................................... 502 Word Access Example ............................................................................................ 503 Longword Access Example..................................................................................... 503 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) ............ 504 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected) ...................................................... 506 Figure 19.7 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) ........................................................ 507 Figure 19.8 A/D Conversion Timing .......................................................................................... 508 Figure 19.9 External Trigger Input Timing ................................................................................ 509 Figure 19.10 Definitions of A/D Conversion Accuracy ............................................................. 510 Figure 19.11 Example of Analog Input Protection Circuit ......................................................... 511 Figure 19.12 Analog Input Pin Equivalent Circuit ..................................................................... 511 Section 20 D/A Converter (DAC) Figure 20.1 D/A Converter Block Diagram................................................................................ 513 Figure 20.2 Example of D/A Converter Operation..................................................................... 516 Section 21 Figure 21.1 Figure 21.2 Figure 21.3 Section 22 Figure 22.1 Figure 22.2 Figure 22.3 Figure 22.4 Figure 22.5 Figure 22.6 Figure 22.7 User Debugging Interface (H-UDI) H-UDI Block Diagram ............................................................................................ 517 TAP Controller State Transitions ............................................................................ 525 H-UDI Reset............................................................................................................ 527 Power-Down Modes Canceling Software Standby Mode with STBCR.STBY ........................................ 537 Power-On Reset STATUS Output........................................................................... 540 Manual Reset STATUS Output............................................................................... 540 Software Standby to Interrupt STATUS Output ..................................................... 541 Software Standby to Power-On Reset STATUS Output ......................................... 541 Software Standby to Manual Reset STATUS Output ............................................. 542 Sleep to Interrupt STATUS Output ......................................................................... 542 Rev. 4.00, 03/04, page xxxviii of xlvi Figure 22.8 Sleep to Power-On Reset STATUS Output.............................................................543 Figure 22.9 Sleep to Manual Reset STATUS Output .................................................................543 Figure 22.10 Hardware Standby Mode (When CA Goes Low in Normal Operation) ...............545 Figure 22.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation on Standby Mode Cancellation) ..546 Power-On Sequence......................................................................................................................570 Electrical Characteristics EXTAL Clock Input Timing ...................................................................................576 CKIO Clock Input Timing.......................................................................................576 CKIO Clock Output Timing ....................................................................................576 Power-On Oscillation Settling Time .......................................................................577 Oscillation Settling Time at Standby Return (Return by Reset)..............................577 Oscillation Settling Time at Standby Return (Return by NMI) ...............................577 Oscillation Settling Time at Standby Return (Return by IRQ or IRL) ...................578 PLL Synchronization Settling Time by Reset or NMI at the returning from Standby mode (Return by Reset or NMI).....................578 Figure 24.9 PLL Synchronization Settling Time at the returning from Standby mode (Return by IRQ/IRL Interrupt).................................................................................579 Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified .......................................................................................................579 Figure 24.11 Reset Input Timing ................................................................................................581 Figure 24.12 Interrupt Signal Input Timing................................................................................581 Figure 24.13 IRQOUT Timing ...................................................................................................581 Figure 24.14 Bus Release Timing...............................................................................................582 Figure 24.15 Pin Drive Timing at Standby .................................................................................582 Figure 24.16 Basic Bus Cycle (No Wait) ...................................................................................585 Figure 24.17 Basic Bus Cycle (One Wait)..................................................................................586 Figure 24.18 Basic Bus Cycle (External Wait)...........................................................................587 Figure 24.19 Burst ROM Bus Cycle (No Wait)..........................................................................588 Figure 24.20 Burst ROM Bus Cycle (Two Waits)......................................................................589 Figure 24.21 Burst ROM Bus Cycle (External Wait) .................................................................590 Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0)....591 Figure 24.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1)....592 Figure 24.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1)...................................................................593 Figure 24.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0)...................................................................594 Figure 24.26 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0) .............595 Figure 24.27 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1) .............596 Figure 24.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0) .............................................................................597 Section 24 Figure 24.1 Figure 24.2 Figure 24.3 Figure 24.4 Figure 24.5 Figure 24.6 Figure 24.7 Figure 24.8 Rev. 4.00, 03/04, page xxxix of xlvi Figure 24.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0) ............................................................................. 598 Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 1)........................................... 599 Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2)............................................ 600 Figure 24.32 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1) ...... 601 Figure 24.33 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1) ..... 602 Figure 24.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address) ......................................................................... 603 Figure 24.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0).................................... 604 Figure 24.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1).................................... 605 Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) ...................... 606 Figure 24.38 Synchronous DRAM Self-Refresh Cycle (TPC = 0)............................................. 606 Figure 24.39 Synchronous DRAM Mode Register Write Cycle ................................................ 607 Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) .............................. 608 Figure 24.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait).... 609 Figure 24.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait).......... 610 Figure 24.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3)................................................................................... 611 Figure 24.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait)....................................... 612 Figure 24.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) ............ 613 Figure 24.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing)................. 614 Figure 24.47 TCLK Input Timing .............................................................................................. 616 Figure 24.48 TCLK Clock Input Timing.................................................................................... 616 Figure 24.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on............................. 616 Figure 24.50 SCK Input Clock Timing....................................................................................... 616 Figure 24.51 SCI I/O Timing in Clock Synchronous Mode ....................................................... 617 Figure 24.52 I/O Port Timing ..................................................................................................... 617 Figure 24.53 DREQ Input Timing .............................................................................................. 617 Figure 24.54 DRAK Output Timing........................................................................................... 618 Figure 24.55 TCK Input Timing................................................................................................. 619 Figure 24.56 TRST Input Timing (Reset Hold).......................................................................... 619 Figure 24.57 H-UDI Data Transfer Timing ................................................................................ 619 Figure 24.58 ASEMD0 Input Timing......................................................................................... 620 Figure 24.59 AUD Timing.......................................................................................................... 620 Figure 24.60 External Trigger Input Timing .............................................................................. 621 Figure 24.61 A/D Conversion Timing ........................................................................................ 621 Figure 24.62 Output Load Circuit............................................................................................... 622 Rev. 4.00, 03/04, page xl of xlvi Figure 24.63 Load Capacitance vs. Delay Time .........................................................................623 Appendix Figure D.1 Package Dimensions (FP-176C)...............................................................................654 Figure D.2 Package Dimensions (TBP-208A)............................................................................655 Rev. 4.00, 03/04, page xli of xlvi Tables Section 2 Table 2.1 Table 2.2 Table 2.3 Table 2.4 Table 2.5 Table 2.6 Table 2.7 Table 2.8 Table 2.9 Table 2.10 Table 2.11 CPU Initial Register Values ................................................................................................ 15 Addressing Modes and Effective Addresses............................................................... 23 Instruction Formats ..................................................................................................... 27 Classification of Instructions ...................................................................................... 30 Data Transfer Instructions........................................................................................... 34 Arithmetic Instructions ............................................................................................... 36 Logic Operation Instructions ...................................................................................... 39 Shift Instructions......................................................................................................... 40 Branch Instructions ..................................................................................................... 41 System Control Instructions.................................................................................... 42 Instruction Code Map ............................................................................................. 46 Section 3 Memory Management Unit (MMU) Table 3.1 Access States Designated by D, C, and PR Bits ......................................................... 64 Section 4 Exception Processing Table 4.1 Exception Event Vectors............................................................................................. 82 Table 4.2 Exception Codes ......................................................................................................... 85 Table 4.3 Types of Reset ............................................................................................................ 91 Section 5 Cache Table 5.1 LRU and Way Replacement ..................................................................................... 100 Table 5.2 Way to be Replaced when Cache Miss Occurs during PREF Instruction Execution................................................................................................ 103 Table 5.3 Way to be Replaced when Cache Miss Occurs during Execution of Instruction other than PREF Instruction ................................................................... 103 Table 5.4 LRU and Way Replacement (when W2LOCK=1) ................................................... 103 Table 5.5 LRU and Way Replacement (when W3LOCK=1) ................................................... 104 Table 5.6 LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1)....................... 104 Section 6 Interrupt Controller (INTC) Table 6.1 Pin Configuration...................................................................................................... 113 Table 6.2 IRL3 to IRL0 Pins and Interrupt Levels ................................................................... 115 Table 6.3 Interrupt Exception Handling Sources and Priority (IRQ Mode) ............................. 117 Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode).............................. 119 Table 6.5 Interrupt Level and INTEVT Code........................................................................... 120 Table 6.6 Interrupt Request Sources and IPRA to IPRE........................................................... 121 Table 6.7 Interrupt Response Time........................................................................................... 132 Section 7 User Break Controller Table 7.1 Data Access Cycle Addresses and Operand Size Comparison Conditions............... 149 Rev. 4.00, 03/04, page xlii of xlvi Section 8 Table 8.1 Table 8.2 Table 8.3 Table 8.4 Table 8.5 Table 8.6 Table 8.7 Table 8.8 Table 8.9 Table 8.10 Table 8.11 Table 8.12 Table 8.13 Table 8.14 Table 8.15 Table 8.16 Table 8.17 Table 8.18 Bus State Controller (BSC) Pin Configuration......................................................................................................161 Physical Address Space Map ....................................................................................163 Correspondence between External Pins (MD4 and MD3) and Memory Size...........165 PCMCIA Interface Characteristics ...........................................................................166 PCMCIA Support Interface ......................................................................................166 Area 6 Wait Control..................................................................................................178 Area 5 Wait Control..................................................................................................179 Area 4 Wait Control..................................................................................................179 Area 0 Wait Control..................................................................................................180 Area 6 Wait Control..............................................................................................187 32-Bit External Device/Big Endian Access and Data Alignment .........................193 16-Bit External Device/Big Endian Access and Data Alignment .........................193 8-Bit External Device/Big Endian Access and Data Alignment ...........................194 32-Bit External Device/Little Endian Access and Data Alignment ......................195 16-Bit External Device/Little Endian Access and Data Alignment ......................195 8-Bit External Device/Little Endian Access and Data Alignment ........................196 Relationship between Bus Width, AMX, and Address Multiplex Output ............208 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width))....................................209 Section 9 Direct Memory Access Controller (DMAC) Table 9.1 Pin Configuration......................................................................................................245 Table 9.2 Selecting External Request Modes with the RS Bits ................................................257 Table 9.3 Selecting On-Chip Peripheral Module Request Modes with the RS Bit...................258 Table 9.4 Supported DMA Transfers........................................................................................262 Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category .........272 Table 9.6 Transfer Conditions and Register Settings for Transfer between On-Chip A/D converter and External Memory ............................287 Table 9.7 Values in the DMAC after the Fourth Transfer Ends ...............................................288 Table 9.8 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter...................................................................289 Section 10 Clock Pulse Generator (CPG) Table 10.1 Clock Pulse Generator Pins and Functions ...........................................................294 Table 10.2 Clock Operating Modes ........................................................................................294 Table 10.3 Available Combination of Clock Mode and FRQCR Values ...............................296 Section 12 Timer Unit(TMU) Table 12.1 Pin Configuration..................................................................................................311 Table 12.2 TMU Interrupt Sources .........................................................................................324 Section 13 Realtime Clock (RTC) Table 13.1 RTC Pin Configuration .........................................................................................327 Table 13.2 Recommended Oscillator Circuit Constants (Recommended Values)..................344 Rev. 4.00, 03/04, page xliii of xlvi Section 14 Serial Communication Interface (SCI) Table 14.1 SCI Pins ................................................................................................................ 351 Table 14.2 SCSMR Settings ................................................................................................... 366 Table 14.3 Bit Rates and SCBRR Settings in Asynchronous Mode ....................................... 367 Table 14.4 Bit Rates and SCBRR Settings in Clock Synchronous Mode............................... 369 Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator synchronous Mode)............................................................................................... 370 Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode)............ 371 Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) ... 371 Table 14.8 Serial Mode Register Settings and SCI Communication Formats ........................ 373 Table 14.9 SCSMR and SCSCR Settings and SCI Clock Source Selection ........................... 373 Table 14.10 Serial Communication Formats (Asynchronous Mode)........................................ 375 Table 14.11 Receive Error Conditions and SCI Operation....................................................... 381 Table 14.12 SCI Interrupt Sources............................................................................................ 396 Table 14.13 SCSSR Status Flags and Transfer of Receive Data .............................................. 397 Section 15 Smart Card Interface Table 15.1 Pin Configuration.................................................................................................. 402 Table 15.2 Register Settings for the Smart Card Interface...................................................... 408 Table 15.3 Relationship of n to CKS1 and CKS0................................................................... 410 Table 15.4 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0) ................................ 410 Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0) ................................ 411 Table 15.6 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) ..................... 411 Table 15.7 Register Set Values and SCK Pin ....................................................................... 412 Table 15.8 Smart Card Mode Operating State and Interrupt Sources..................................... 416 Section 16 Serial Communication Interface with FIFO (SCIF) Table 16.1 SCIF Pins .............................................................................................................. 425 Table 16.2 SCSMR2 Settings ................................................................................................. 439 Table 16.3 Bit Rates and SCBRR2 Settings ........................................................................... 440 Table 16.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode)........................................................ 442 Table 16.5 Maximum Bit Rates during External Clock Input (Asynchronous Mode)............ 443 Table 16.6 SCSMR2 Settings and SCIF Communication Formats......................................... 446 Table 16.7 SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection...................... 447 Table 16.8 Serial Communication Formats ............................................................................ 447 Table 16.9 SCIF Interrupt Sources ......................................................................................... 456 Section 17 Pin Function Controller (PFC) Table 17.1 List of Multiplexed Pins........................................................................................ 459 Section 18 I/O Ports Table 18.1 Read/Write Operation of the Port A Data Register (PADR)................................. 480 Table 18.2 Read/Write Operation of the Port B Data Register (PBDR) ................................ 481 Table 18.3 Read/Write Operation of the Port C Data Register (PCDR) ................................. 483 Rev. 4.00, 03/04, page xliv of xlvi Table 18.4 Table 18.5 Table 18.6 Table 18.7 Table 18.8 Table 18.9 Table 18.10 Read/Write Operation of the Port D Data Register (PDDR)................................484 Read/Write Operation of the Port E Data Register (PEDR) .................................486 Read/Write Operation of the Port F Data Register (PFDR) ..................................487 Read/Write Operation of the Port G Data Register (PGDR).................................489 Read/Write Operation of the Port H Data Register (PHDR).................................491 Read/Write Operation of the Port J Data Register (PJDR) ...................................492 Read/Write Operation of the SC Port Data Register (SCPDR).............................494 Section 19 A/D Converter (ADC) Table 19.1 A/D Converter Pins...................................................................................................497 Table 19.2 Analog Input Channels and A/D Data Registers...................................................498 Table 19.3 A/D Conversion Time (Single Mode)...................................................................509 Table 19.4 Analog Input Pin Ratings......................................................................................512 Table 19.5 Relationship between Access Size and Read Data................................................512 Section 20 D/A Converter (DAC) Table 20.1 D/A Converter Pins...............................................................................................514 Section 21 User Debugging Interface (H-UDI) Table 21.1 Pin Configuraiton..................................................................................................518 Table 21.2 This LSI's Pins and Boundary Scan Register Bits.................................................520 Table 21.3 Reset Configuration ..............................................................................................526 Section 22 Power-Down Modes Table 22.1 Power-Down Modes .............................................................................................531 Table 22.2 Pin Configuration..................................................................................................532 Table 22.3 Register States in Software Standby Mode ...........................................................536 Section 24 Electrical Characteristics Table 24.1 Absolute Maximum Ratings .................................................................................569 Table 24.2 DC Characteristics (Ta = -20 to 75C) .................................................................571 Table 24.3 Permitted Output Current Values (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C) ................................................................573 Table 24.4 Operating Frequency Range..................................................................................574 Table 24.5 Clock Timing ........................................................................................................574 Table 24.6 Control Signal Timing ..........................................................................................580 Table 24.7 Bus Timing (Clock Modes 0/1/2/7) .....................................................................583 Table 24.8 Peripheral Module Signal Timing.........................................................................615 Table 24.9 H-UDI, AUD Related Pin Timing ........................................................................618 Table 24.10 A/D Converter Timing ..........................................................................................620 Table 24.11 A/D Converter Characteristics (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C) ................................................................624 Table 24.12 D/A Converter Characteristics (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C) ................................................................624 Rev. 4.00, 03/04, page xlv of xlvi Appendix Table B.1 Table B.2 Table B.3 Table B.4 Table B.5 Table B.6 Table B.7 Table B.8 Table B.9 Table B.10 Pin States during Resets, Power-Down States, and Bus-Released State................... 629 Pin Specifications ..................................................................................................... 633 Pin States (Normal Memory/Little Endian) .............................................................. 638 Pin States (Normal Memory/Big Endian) ................................................................. 640 Pin States (Burst ROM/Little Endian) ...................................................................... 642 Pin States (Burst ROM/Big Endian) ......................................................................... 644 Pin States (Synchronous DRAM/Little Endian) ....................................................... 646 Pin States (Synchronous DRAM/Big Endian) .......................................................... 647 Pin States (PCMCIA/Little Endian).......................................................................... 648 Pin States (PCMCIA/Big Endian)......................................................................... 650 Rev. 4.00, 03/04, page xlvi of xlvi Section 1 Overview The SH7706 is a RISC microprocessor that integrates a Renesas Technology-original RISC-type SuperHTM architecture SH-3 CPU as its core that has peripheral functions required for system configuration. The CPU of this LSI has upper compatibility with the SH-1 and SH-2 at object code level. This LSI incorporates a memory management unit (MMU) that has a 128-entry 4-way set associative translation lookaside buffer (TLB). The LSI incorporates the following peripheral functions: an on-chip direct memory access controller (DMAC) that enables high-speed data transfer and a bus state controller (BSC) that enables direct connection to different types of memory. The LSI also incorporates a serial communication interface, an A/D converter, a D/A converter, a timer, and a realtime clock that enable system configuration at low cost. A built-in power management function enables dynamic control of power consumption. Thus, this LSI is optimum for portable electronic devices such as PDAs that require both high performance and low power. The SH7706 incorporates a user debugging interface (H-UDI) and an advanced user debugger (AUD) to support emulator functions such as E10A. This LSI also incorporates a user break controller (UBC) for self debugging. Note: * The SuperH is a trademark of Renesas Technology, Corp. 1.1 Feature * Original Renesas SuperH architecture * Object code level compatible with SH-1, SH-2 and SH-3 * 32-bit RISC-type instruction set Instruction length: 16-bit fixed length Improved code efficiency Load-store architecture Delayed branch instructions Instruction set oriented for C language * Five-stage pipeline * Instruction execution time: one instruction/cycle for basic instructions * General-register: Sixteen 32-bit general registers * Control-register: Eight 32-bit control registers * System-register: Four 32-bit system registers * 32-bit internal data bus * Logical address space: 4 Gbytes Rev. 4.00, 03/04, page 1 of 660 * Space identifier ASID: 8 bits, 256 logical address space * Abundant Peripheral Functions Memory Management Unit (MMU) User Break Controller (UBC) Bus state Controller (BSC) Direct Memory Access Controller (DMAC) Clock Pulse Generator (CPG) Watchdog Timer (WDT) Timer Unit (TMU) Realtime Clock (RTC) Serial Communication Interface (SCI) Smartcard Interface Serial Communication Interface with FIFO (SCIF) 10-bit A/D converter (ADC) 8-bit D/A converter (DAC) User Debugging Interface (H-UDI) Advanced User Debugger (AUD) Rev. 4.00, 03/04, page 2 of 660 1.2 Block Diagram MMU I bus 1 L bus CPU Peripheral bus 1 TLB SCI UBC CCN AUD CACHE BRIDGE TMU RTC BSC H-UDI I bus 2 SCIF DMAC Peripheral bus 2 INTC ADC CPG/WDT CMT DAC External bus interface I/O port Legend ADC : A/D converter AUD : Advanced user debugger BSC : Bus state controller CACHE : Cache memory CCN : Cache memory controller CMT : Compare match timer CPG/WDT : Clock pulse generator/watchdog timer CPU : Central processing unit DAC : D/A converter DMAC H-UDI INTC MMU RTC SCI SCIF TLB TMU UBC : Direct memory access controller : User debugging interface : Interrupt controller : Memory management unit : Realtime clock : Serial communication interface (with smart card interface) : Serial communication interface (with FIFO) : Address translation buffer : Timer unit : User break controller Figure 1.1 SH7706 Block Diagram Rev. 4.00, 03/04, page 3 of 660 1.3 Pin Assignment /PTF[6] TDO/PTF[5] /PTG[3] TMS/PTG[2] VCC TCK/PTG[1] VSS TDI/PTG[0] /PTF[4] AUDATA[3]/PTF[3] AUDATA[2]/PTF[2] AUDATA[1]/PTF[1] AUDATA[0]/PTF[0] DRAK1/PTE[3] DRAK0/PTE[2] DACK1/PTE[1] DACK0/PTE[0] /PTD[5] CKE/PTD[4] /PTD[3] /PTD[2] /PTD[1] /PTD[0] VCCQ /PTD[7] VSSQ /PTD[6] / /PTC[7] / /PTC[6] /PTC[5] 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 STATUS0/PTE[4] STATUS1/PTE[5] TCLK/PTE[6] /PTE[7] VSSQ CKIO VCCQ TxD0/SCPT[0] SCK0/SCPT[1] TxD2/SCPT[2] SCK2/SCPT[3] /SCPT[4] RxD0/SCPT[0] RxD2/SCPT[2] /IRQ5/SCPT[5] VSS VCC IRQ0/ /PTH[0] IRQ1/ /PTH[1] /PTH[2] IRQ2/ IRQ3/ /PTH[3] IRQ4/PTH[4] VSSQ NMI VCCQ AUDCK/PTG[4] /PTH[5] /PTH[6] /PTG[5] MD0 MD2 CA MD3 MD4 MD5 AVSS AN[0]/PTJ[0] AN[1]/PTJ[1] AN[2]/DA[1]/PTJ[2] AN[3]/DA[2]/PTJ[3] AVCC AVSS 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 EXTAL XTAL VSS MD1 VCC - PLL2 CAP2 VSS - PLL2 VSS - PLL1 CAP1 VCC - PLL1 /PTC[4] /PTC[3] VCCQ VSSQ RD/ / / / / /PTC[0] A25 A24 A23 VCC A22 VSS A21 A20 A19 A18 A17 A16 A15 VCCQ A14 VSSQ A13 A12 A11 A10 A9 A8 A7 A6 A5 VCCQ A4 VSSQ A3 A2 A1 A0 / / / /PTC[2] /PTC[1] SH-7706 FP-176C (Top view) INDEX MARK 1.9V VCC 1.9V GND 3.3V VCC 3.3V GND Rev. 4.00, 03/04, page 4 of 660 VCC - RTC XTAL2 EXTAL2 VSS - RTC D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VSSQ D25/PTB[1] VCCQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] VSS D19/PTA[3] VCC D18/PTA[2] D17/PTA[1] D16/PTA[0] VSSQ D15 VCCQ D14 D13 D12 D11 D10 D9 D8 D7 D6 VSSQ D5 VCCQ D4 D3 D2 D1 D0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Figure 1.2 Pin Assignment (FP-176C) A B C D E F G H J K L M N P R T U 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 INDEX MARK SH7706 TBP-208A (Top view) 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U Note: Section in the dotted lines are perspective view. Figure 1.3 Pin Assignment (TBP-208A) Rev. 4.00, 03/04, page 5 of 660 1.4 FP-176C 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Pin Function TBP-208A C3 C2 C1 D3 F4 F3 F2 F1 G4 G3 G2 G1 H4 H3 H2 H1 J4 J2 J1 J3 K1 K2 K3 K4 L1 L2 L3 L4 M1 Pin Name VCC-RTC* XTAL2 EXTAL2 VSS-RTC* 1 1 Number of Pins I/O -- O I -- I/O I/O I/O I/O I/O I/O -- I/O -- I/O I/O I/O I/O I/O -- I/O -- I/O I/O I/O -- I/O -- I/O I/O Description RTC power supply (1.9 V) On-chip RTC crystal oscillator pin On-chip RTC crystal oscillator pin RTC power supply (0 V) Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Data bus / input/output port B Input/output power supply (0 V) Data bus / input/output port B Input/output power supply (3.3 V) Data bus / input/output port B Data bus / input/output port A Data bus / input/output port A Data bus / input/output port A Data bus / input/output port A Internal power supply (0 V) Data bus / input/output port A Internal power supply (1.9 V) Data bus / input/output port A Data bus / input/output port A Data bus / input/output port A Input/output power supply (0 V) Data bus Input/output power supply (3.3 V) Data bus Data bus D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] VSSQ D25/PTB[1] VCCQ D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] VSS D19/PTA[3] VCC D18/PTA[2] D17/PTA[1] D16/PTA[0] VSSQ D15 VCCQ D14 D13 Rev. 4.00, 03/04, page 6 of 660 Number of Pins FP-176C 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 TBP-208A M2 M3 M4 N1 N2 N3 N4 P1 P2 P3 R1 R2 P4 T1 T2 U1 U2 R3 T3 U3 R4 T4 U4 P5 R5 T5 U5 P6 R6 T6 Pin Name D12 D11 D10 D9 D8 D7 D6 VSSQ D5 VCCQ D4 D3 D2 D1 D0 A0 A1 A2 A3 VSSQ A4 VCCQ A5 A6 A7 A8 A9 A10 A11 A12 I/O I/O I/O I/O I/O I/O I/O I/O -- I/O -- I/O I/O I/O I/O I/O O O O O -- O -- O O O O O O O O Description Data bus Data bus Data bus Data bus Data bus Data bus Data bus Input/output power supply (0 V) Data bus Input/output power supply (3.3 V) Data bus Data bus Data bus Data bus Data bus Address bus Address bus Address bus Address bus Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Address bus Rev. 4.00, 03/04, page 7 of 660 Number of Pins FP-176C 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 TBP-208A U6 P7 R7 T7 U7 P8 R8 T8 U8 P9 T9 U9 R9 U10 T10 P10 T11 R11 P11 U12 T12 R12 Pin Name A13 VSSQ A14 VCCQ A15 A16 A17 A18 A19 A20 A21 VSS A22 VCC A23 A24 A25 BS/PTC[0] RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTC[1] I/O O -- O -- O O O O O O O -- O -- O O O O / I/O O O O O/O/ O / I/O Description Address bus Input/output power supply (0 V) Address bus Input/output power supply (3.3 V) Address bus Address bus Address bus Address bus Address bus Address bus Address bus Internal power supply (0 V) Address bus Internal power supply (1.9 V) Address bus Address bus Address bus Bus cycle start signal / input/output port C Read strobe D7 to D0 select signal / DQM (SDRAM) D15 to D8 select signal / DQM (SDRAM) / write strobe (PCMCIA) D23 to D16 select signal / DQM (SDRAM) / PCMCIA input/output read / input/output port C D31 to D24 select signal / DQM (SDRAM) / PCMCIA input/output write / input/output port C Read/write 82 P12 WE3/DQMUU/ ICIOWR/PTC[2] O/O/ O / I/O 83 U13 RD/WR O Rev. 4.00, 03/04, page 8 of 660 Number of Pins FP-176C 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 TBP-208A R13 P13 U14 T14 R14 U17 T17 R15 R16 R17 P15 P16 P17 N14 N15 N16 N17 M14 M15 M16 M17 L14 L15 Pin Name VSSQ CS0 VCCQ CS2/PTC[3] CS3/PTC[4] CS4/PTC[5] CS5/CE1A/PTC[6] CS6/CE1B/PTC[7] CE2A/PTD[6] VSSQ CE2B/PTD[7] VCCQ RASL/PTD[0] RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] CKE/PTD[4] IOIS16/PTD[5] BACK BREQ WAIT DACK0/PTE[0] DACK1/PTE[1] I/O -- O -- O / I/O O / I/O O / I/O Description Input/output power supply (0 V) Chip select 0 Input/output power supply (3.3 V) Chip select 2 / input/output port C Chip select 3 / input/output port C Chip select 4 / input/output port C O / O / I/O Chip select 5 / CE1 (area 5 PCMCIA) / input/output port C O / O / I/O Chip select 6 / CE1 (area 6 PCMCIA) / input/output port C O / I/O -- O / I/O -- O / I/O O / I/O O / I/O O / I/O O / I/O I / I/O O I I O / I/O O / I/O Area 5 PCMCIA CE2 / input/output port D Input/output power supply (0 V) Area 6 PCMCIA CE2 / input/output port D Input/output power supply (3.3 V) Lower 32 Mbytes address RAS (SDRAM) / input/output port D Upper 32 Mbytes address RAS (SDRAM) / input/output port D Lower 32 Mbytes address CAS (SDRAM) / input/output port D Upper 32 Mbytes address CAS (SDRAM) / input/output port D CK enable (SDRAM) / input/output port D IOIS16 (PCMCIA) / input port D Bus acknowledge Bus request Hardware wait request DMA acknowledge 0 / input/output port E DMA acknowledge 1 / input/output port E Rev. 4.00, 03/04, page 9 of 660 Number of Pins FP-176C 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 TBP-208A L16 L17 K15 K16 K17 J14 J16 J17 J15 H17 H16 G16 G15 G14 F16 F15 E17 E16 E15 E14 D17 D16 C17 C16 B17 B16 Pin Name DRAK0/PTE[2] DRAK1/PTE[3] AUDATA[0]/PTF[0] AUDATA[1]/PTF[1] AUDATA[2]/PTF[2] AUDATA[3]/PTF[3] AUDSYNC/PTF[4] TDI/PTG[0] VSS TCK/PTG[1] VCC TMS/PTG[2] TRST/PTG[3] TDO/PTF[5] ASEBRKAK/PTF[6] ASEMD0* 3 2 I/O O / I/O O / I/O I/O I/O I/O I/O O / I/O I -- I -- I I O / I/O O / I/O I -- -- 2 2 Description DMA request acknowledge / input/output port E DMA request acknowledge / input/output port E AUD data / input/output port F AUD data / input/output port F AUD data / input/output port F AUD data / input/output port F AUD synchronous / input/output port F Data input (H-UDI) / input port G Internal power supply (0 V) Clock (H-UDI) / input port G Internal power supply (1.9 V) Mode select (H-UDI) / input port G Reset (H-UDI) / input port G Data output (H-UDI) / input/output port F ASE break acknowledge (H-UDI) / input/output port F ASE mode (H-UDI) PLL1 power supply (1.9 V) PLL1 external capacitance pin PLL1 power supply (0 V) PLL2 power supply (0 V) PLL2 external capacitance pin PLL2 power supply (1.9 V) Clock mode setting Internal power supply (0 V) Clock oscillator pin External clock / crystal oscillator pin VCC-PLL1* CAP1 VSS-PLL1* VSS-PLL2* CAP2 VCC-PLL2* MD1 VSS XTAL EXTAL -- -- -- 2 -- I -- O I Rev. 4.00, 03/04, page 10 of 660 Number of Pins FP-176C 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 TBP-208A A17 A16 C15 B15 A15 C14 B14 A14 D13 C13 B13 A13 D12 C12 B12 D11 C11 B11 A11 D10 C10 B10 A10 Pin Name STATUS0/PTE[4] STATUS1/PTE[5] TCLK/PTE[6] IRQOUT/PTE[7] VSSQ CKIO VCCQ TxD0/SCPT[0] SCK0/SCPT[1] TxD2/SCPT[2] SCK2/SCPT[3] RTS2/SCPT[4] RxD0/SCPT[0] RxD2/SCPT[2] CTS2/IRQ5/SCPT[5] VSS RESETM VCC IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] I/O O / I/O O / I/O I/O O / I/O -- I/O -- O I/O O I/O O / I/O I I I -- I -- I / I / I/O I / I / I/O I / I / I/O I / I / I/O I / I/O Description Processor status / input/output port E Processor status / input/output port E TMU or RTC clock input/output / input/output port E Interrupt request notification / input/output port E Input/output power supply (0 V) System clock input/output Input/output power supply (3.3 V) SCI transmit data 0 / SC port SCI clock 0 / SC port SCIF transmit data 2 / SC port SCIF clock 2 / SC port SCIF transmit request 2 / SC port SCI receive data 0 / SC port SCIF receive data 2 / SC port SCIF transmit clear / external interruption request / SC port Internal power supply (0 V) Manual reset request Internal power supply (1.9 V) External interrupt request / input/output port H External interrupt request / input/output port H External interrupt request / input/output port H External interrupt request / input/output port H External interrupt request / input/output port H Rev. 4.00, 03/04, page 11 of 660 Number of Pins FP-176C 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 TBP-208A D9 B9 A9 C9 A8 B8 C8 D8 B7 A6 B6 C6 D6 A5 B5 C5 D5 A4 B4 B3 B2 Pin Name VSSQ NMI VCCQ AUDCK/PTG[4] DREQ0/PTH[5] DREQ1/PTH[6] ADTRG/PTG[5] MD0 MD2 RESETP CA MD3 MD4 MD5 AVSS AN[0]/PTJ[0] AN[1]/PTJ[1] AN2[2]/DA[1]/PTJ[2] AN3[3]/DA[0]/PTJ[3] AVCC AVSS I/O -- I -- I I / I/O I / I/O I I I I I I I I -- I I I/O/I I/O/I -- -- Description Input/output power supply (0 V) Nonmaskable interrupt request Input/output power supply (3.3 V) AUD clock / input port G DMA request / input/output port H DMA request / input/output port H Analog trigger / input port G Clock mode setting Clock mode setting Power-on reset request Chip activate / hardware standby request Area 0 bus width setting Area 0 bus width setting Endian setting Analog power supply (0 V) A/D converter input / input port J A/D converter input / input port J A/D converter input / D/A converter output / input port J A/D converter input / D/A converter output / input port J Analog power supply (3.3 V) Analog power supply (0 V) Notes: Except in hardware standby mode, all VCC/VSS pins must be connected to the system power supply. (Supply power constantly.) In hardware standby mode, power must be supplied at least to VCC-RTC and VSS-RTC. If power is not supplied to VCC and VSS pins other than VCC-RTC and VSS-RTC, hold the CA pin low. In the TBP-208A package, the A1, A2, A3, A7, A12, B1, C4, C7, D1, D2, D4, D7, D14, D15, E1, E2, E3, E4, F14, F17, G17, H14, H15, K14, P14, R10, T13, T15, T16, U11, U15, and U16 pins must be connected to VSS. 1. Must be connected to the power supply even when the RTC is not used. 2. Must be connected to the power supply even when the on-chip PLL circuits are not used (except in hardware standby mode). 3. Must be high level when the user system is used independently without using the emulator or H-UDI. When this pin goes low or is open, the RESETP pin may be masked. (See section 21, User Debugging Interface (H-UDI).) Rev. 4.00, 03/04, page 12 of 660 Section 2 CPU 2.1 2.1.1 Register Description Privileged Mode and Banks Processor Modes: There are two processor modes: user mode and privileged mode. The SH7706 normally operates in user mode, and enters privileged mode when an exception occurs or an interrupt is accepted. There are three kinds of registers--general registers, system registers, and control registers--and the registers that can be accessed differ in the two processor modes. General Registers: There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers which are switched by a processor mode change. In privileged mode, the register bank bit (RB) in the status register (SR) defines which banked register set is accessed as general registers, and which set is accessed only through the load control register (LDC) and store control register (STC) instructions. When the RB bit is 1, BANK1 general registers R0_BANK1 to R7_BANK1 and non-banked general registers R8 to R15 function as the general register set, with BANK0 general registers R0_BANK0 to R7_BANK0 accessed only by the LDC/STC instructions. When the RB bit is 0, BANK0 general registers R0_BANK0 to R7_BANK0 and nonbanked general registers R8 to R15 function as the general register set, with BANK1 general registers R0_BANK1 to R7_BANK1 accessed only by the LDC/STC instructions. In user mode, the 16 registers comprising bank 0 general registers R0_BANK0 to R7_BANK0 and non-banked registers R8 to R15 can be accessed as general registers R0 to R15, and bank 1 general registers R0_BANK1 to R7_BANK1 cannot be accessed. Control Registers: Control registers comprise the global base register (GBR) and status register (SR) which can be accessed in both processor modes, and the saved status register (SSR), saved program counter (SPC), and vector base register (VBR) which can only be accessed in privileged mode. Some bits of the status register (such as the RB bit) can only be accessed in privileged mode. System Registers: System registers comprise the multiply and accumulate registers (MACL/MACH), the procedure register (PR), and the program counter (PC). Access to these registers does not depend on the processor mode. The register configuration in each mode is shown in figures 2.1. Switching between user mode and privileged mode is controlled by the processor mode bit (MD) in the status register. Rev. 4.00, 03/04, page 13 of 660 31 R0_BANK0*1 *2 R1_BANK0*2 R2_BANK0*2 R3_BANK0*2 R4_BANK0*2 R5_BANK0*2 R6_BANK0*2 R7_BANK0*2 R8 R9 R10 R11 R12 R13 R14 R15 SR 0 31 R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 0 31 R0_BANK0*1 *4 R1_BANK0*4 R2_BANK0*4 R3_BANK0*4 R4_BANK0*4 R5_BANK0*4 R6_BANK0*4 R7_BANK0*4 R8 R9 R10 R11 R12 R13 R14 R15 SR SSR GBR MACH MACL PR VBR PC SPC R0_BANK1*1 *3 R1_BANK1*3 R2_BANK1*3 R3_BANK1*3 R4_BANK1*3 R5_BANK1*3 R6_BANK1*3 R7_BANK1*3 c. Privileged mode register configuration (RB = 0) 0 GBR MACH MACL PR PC a. User mode register configuration b. Privileged mode register configuration (RB = 1) Notes: 1. 2. 3. 4. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. Banked register Banked register When the RB bit of the SR register is 1, the register can be accessed for general use. When the RB bit is 0, it can only be accessed with the LDC/STC instruction. Banked register When the RB bit of the SR register is 0, the register can be accessed for general use. When the RB bit is 1, it can only be accessed with the LDC/STC instruction. Figure 2.1 Register Configuration Rev. 4.00, 03/04, page 14 of 660 Register values after a reset are shown in table 2.1. Table 2.1 Type General registers Control registers Initial Register Values Registers R0 to R15 SR Initial Value* Undefined MD bit = 1, RB bit = 1, BL bit = 1, I3 to I0 = 1111 (H'F), reserved bits = 0, others undefined Undefined H'00000000 Undefined H'A0000000 GBR, SSR, SPC VBR System registers MACH, MACL, PR PC Note: * Initial value is set at power-on-reset or manual-reset. 2.1.2 General Registers There are 16 general registers, designated R0 to R15. General registers R0 to R7 are banked registers, with a different R0 to R7 register bank (R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1) being accessed according to the processor mode. For details, see figure 2.1. The general register configuration is shown in figure 2.2. General Registers 31 R0*1 *2 R1*2 R2*2 R3*2 R4*2 R5*2 R6*2 R7*2 R8 R9 R10 R11 R12 R13 R14 R15 0 Initialized to undefined by a reset. Notes: 1. R0 functions as an index register in the indexed register-indirect addressing mode and indexed GBR-indirect addressing mode. In some instructions, only R0 can be used as the source register or destination register. R0 to R7 are banked registers. In privileged mode, SR.RB specifies which banked registers are accessed as general registers (R0_BANK0 to R7_BANK0 or R0_BANK1 to R7_BANK1). 2. Figure 2.2 General Registers Rev. 4.00, 03/04, page 15 of 660 2.1.3 System Registers System registers can be accessed by the LDS and STS instructions. When an exception occurs, the contents of the program counter (PC) are saved in the saved program counter (SPC). The SPC contents are restored to the PC by the RTE instruction used at the end of the exception handling. There are three system registers, as follows. * Multiply and accumulate register (MAC) * Procedure register (PR) * Program counter (PC) The system register configuration is shown in figure 2.3. Multiply and Accumulate Register (MAC) 31 MACH MACL 0 Procedure Register (PR) 31 PR Program Counter (PC) 31 PC 0 0 Figure 2.3 System Registers 1. Multiply and Accumulate Register (MAC) Multiply and Accumulate register is consist of Higher part register (MACH) and Lower part register (MACL). Store the results of multiply-and-accumulate operations. Initialized to undefined by a reset. 2. Procedure Register (PR) Stores the return address for exiting a subroutine procedure. Initialized to undefined by a reset. 3. Program Counter (PC) Indicates the address four addresses (two instructions) ahead of the currently executing instruction. Initialized to H'A0000000 by a reset. Rev. 4.00, 03/04, page 16 of 660 2.1.4 Control Registers Control registers can be accessed in privileged mode using the LDC and STC instructions. The GBR register can also be accessed in user mode. There are five control registers, as follows: * Status register (SR) * Saved status register (SSR) * Saved program counter (SPC) * Global base register (GBR) * Vector base register (VBR) The control register configuration is shown in figure 2.4. Status Register (SR) 31 SR Saved Status Register (SSR) 31 SSR Saved Program Counter (SPC) 31 SPC 0 0 0 Global Base Register (GBR) 31 GBR 0 Vector Base Register (VBR) 31 VBR 0 Figure 2.4 Control Registers Rev. 4.00, 03/04, page 17 of 660 * Status Register (SR) The information of system status are set in this register. Bit 31 Bit Name Initial Value R/W 0 R Description Reserved These bits always read as 0, and the write value should always be 0. 30 MD 1 R/W Processor operation mode bit Indicates the processor operation mode. 0: User mode 1: Privileged mode MD is set to 1 when an exception or interruption is occurred. 29 RB 1 R/W Register bank bit Determines the bank of general registers R0 to R7 used in privileged mode. 1: R0_BANK1 to R7_BANK1 and R8 to R15 are general registers, and R0_BANK0 to R7_BANK0 can be accessed by LDC/STC instructions. 0: R0_BANK0 to R7_BANK0 and R8 to R15 are general registers, and R0_BANK1 to R7_BANK1 can be accessed by LDC/STC instructions. RB is set to 1 when an exception or interruption is occurred. 28 BL 1 R/W Block bit 0: Exceptions and interrupts are accepted. 1: Exceptions and interrupts are suppressed. See section 4, Exception Processing, for details. BL is set to 1 when an exception or interruption is occurred. 27 to 13 All 0 R Reserved These bits always read as 0, and the write value should always be 0. 12 CL 0 R/W Cache lock bit 0: Cache look function is disabled. 1: Cache look function is enabled. Rev. 4.00, 03/04, page 18 of 660 Bit 11, 10 Bit Name Initial Value R/W All 0 R Description Reserved These bits always read as 0, and the write value should always be 0. 9 8 7 6 5 4 3, 2 M Q I3 I2 I1 I0 1 1 1 1 All 0 R/W R/W R/W R/W R/W R/W R M bit Q bit Used by the DIV0S/U and DIV1 instructions. Interrupt mask bits 4-bit field indicating the interrupt request mask level. I3 to I0 do not change to the interrupt acceptance level when an interrupt is occurred. Reserved These bits always read as 0, and the write value should always be 0. 1 0 S T R/W R/W S bit Used by the MAC instruction. T bit Used by the MOVT, CMP/cond, TAS, TST, BT, BF, SETT, CLRT, and DT instructions to indicate true (1) or false (0). Used by the ADDV/C, SUBV/C, DIV0U/S, DIV1, NEGC, SHAR/L, SHLR/L, ROTR/L, and ROTCR/L instructions to indicate a carry, borrow, overflow, or underflow. Note: The M, Q, S and T bits can be set or cleared by special instructions in user mode. Their values are undefined after a reset. All other bits can be read or written in privileged mode. * Saved Status Register (SSR) Stores current SR value at time of exception to indicate processor status in return to instruction stream from exception handler. Initialized to undefined by a reset. * Saved Program Counter (SPC) Stores current PC value at time of exception to indicate return address at completion of exception handling. Initialized to undefined by a reset. Rev. 4.00, 03/04, page 19 of 660 * Global Base Register (GBR) Stores base address of GBR-indirect addressing mode. The GBR-indirect addressing mode is used for on-chip supporting module register area data transfers and logic operations. The GBR register can also be accessed in user mode. Initialized to undefined by a reset. * Vector Base Register (VBR) Stores base address of exception handling vector area. Initialized to H'0000000 by a reset. 2.2 2.2.1 Data Formats Data Format in Registers Register operands are always longwords (32 bits). When a memory operand is only a byte (8 bits) or a word (16 bits), the sign is extended to the longword, and stores into the register. 31 Longword 0 2.2.2 Data Format in Memory Memory data formats are classified into bytes, words, and longwords. Memory can be accessed in 8-bit byte, 16-bit word, or 32-bit longword form. A memory operand less than 32 bits in length is sign-extended before being stored in a register. A word operand must be accessed starting from a word boundary (even address of a 2-byte unit: address 2n), and a longword operand starting from a longword boundary (even address of a 4-byte unit: address 4n). An address error will result if this rule is not observed. A byte operand can be accessed from any address. Big-endian or little-endian byte order can be selected for the data format. The endian mode should be set with the MD5 external pin in a power-on reset. Big-endian mode is selected when the MD5 pin is low, and little-endian when high. The endian mode cannot be changed dynamically. Bit positions are numbered left to right from most-significant to least-significant. Thus, in a 32-bit longword, the leftmost bit, bit 31, is the most significant bit and the rightmost bit, bit 0, is the least significant bit. Rev. 4.00, 03/04, page 20 of 660 The data format in memory is shown in figure 2.5. Address A + 1 Address A 23 31 Address A Address A + 4 Address A + 8 Byte0 Address A + 3 Address A + 10 Address A + 8 Address A + 2 7 15 Byte2 0 Address A + 11 23 31 Byte3 Address A + 9 7 15 Byte1 0 Address A + 8 Address A + 4 Address A Byte1 Byte3 Byte2 Byte0 Word0 Word1 Longword Word1 Longword Word0 Big-endian mode Little-endian mode Figure 2.5 Data Format in Memory 2.3 2.3.1 Instruction Features Execution Environment Data Length: The instruction set is implemented with fixed-length 16-bit wide instructions executed in a pipelined sequence with single-cycle execution for most instructions. All operations are executed in 32-bit longword units. Memory can be accessed in 8-bit byte, 16-bit word, or 32bit longword units, with byte or word units sign-extended into 32-bit longwords. Literals are signextended in arithmetic operations (MOV, ADD, and CMP/EQ instructions) and zero-extended in logical operations (TST, AND, OR, and XOR instructions). Load/Store Architecture: The load-store architecture is used, so basic operations are executed by the registers. Operations requiring memory access are executed in registers following register loading, except for bit-manipulation operations such as logical AND functions, which are executed directly in memory. Delayed Branching: Unconditional branching is implemented as delayed branch operations. Pipeline disruptions due to branching are minimized by the execution of the instruction following the delayed branch instruction prior to branching. Conditional branch instructions are of two kinds, delayed and normal. BRA ADD TRGET R1, R0 ;ADD is executed prior to branching to TRGET Rev. 4.00, 03/04, page 21 of 660 T bit: The T bit in the status register (SR) is used to indicate the result of compare operations, and is read as a TRUE/FALSE condition determining if a conditional branch is taken or not. To improve processing speed, the T bit logic state is modified only by specific operations. An example of how the T bit may be used in a sequence of operations is shown below. ADD CMP/EQ BT #1, R0 R1, R0 TRGET ;T bit not modified by ADD operation ;T bit set to 1 when R0 = 0 ;branch taken to TRGET when T bit = 1 (R0 = 0) Literals: Byte-length literals are inserted directly into the instruction code as immediate data. To maintain the 16-bit fixed-length instruction code, word or longword literals are stored in a table in main memory rather than inserted directly into the instruction code. The memory table is accessed by the MOV instruction using PC-relative addressing with displacement, as follows: MOV.W @(disp, PC), R0 Absolute Addresses: As with word and longword literals, absolute addresses must also be stored in a table in main memory. The value of the absolute address is transferred to a register and the operand access is specified by indexed register-indirect addressing, with the absolute address loaded (like word and longword immediate data) during instruction execution. 16-Bit and 32-Bit Displacements: In the same way, 16-bit and 32-bit displacements also must be stored in a table in main memory. Exactly like absolute addresses, the displacement value is transferred to a register and the operand access is specified by indexed register-indirect addressing, loading the displacement (like word and longword immediate data) during instruction execution. Rev. 4.00, 03/04, page 22 of 660 2.3.2 Addressing Modes Addressing modes and effective address calculation methods are shown in table 2.2. Table 2.2 Addressing Mode Register direct Register indirect Register indirect with postincrement Addressing Modes and Effective Addresses Instruction Format Effective Address Calculation Method Rn @Rn Effective address is register Rn. (Operand is register Rn contents.) Effective address is register Rn contents. Rn Rn Calculation Formula -- Rn @Rn+ Effective address is register Rn contents. A constant is added to Rn after instruction execution: 1 for a byte operand, 2 for a word operand, 4 for a longword operand. Rn Rn + 1/2/4 1/2/4 + Rn Rn After instruction execution Byte: Rn + 1 Rn Word: Rn + 2 Rn Longword: Rn + 4 Rn Register indirect with predecrement @-Rn Effective address is register Rn contents, Byte: Rn - 1 Rn decremented by a constant beforehand: 1 for Word: Rn - 2 Rn a byte operand, 2 for a word operand, 4 for a Longword: Rn - 4 longword operand. Rn Rn (Instruction executed Rn - 1/2/4 1/2/4 - Rn - 1/2/4 with Rn after calculation) Rev. 4.00, 03/04, page 23 of 660 Addressing Mode Instruction Format Effective Address Calculation Method Effective address is register Rn contents with 4-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. Rn disp (zero-extended) x 1/2/4 + Rn + disp x 1/2/4 Calculation Formula Byte: Rn + disp Word: Rn + disp x 2 Longword: Rn + disp x 4 Register @(disp:4, indirect with Rn) displacement Indexed register indirect @(R0, Rn) Effective address is sum of register Rn and R0 contents. Rn + R0 Rn + R0 Rn + R0 GBR indirect @(disp:8, with GBR) displacement Effective address is register GBR contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 1 (byte), 2 (word), or 4 (longword), according to the operand size. GBR disp (zero-extended) x 1/2/4 + GBR + disp x 1/2/4 Byte: GBR + disp Word: GBR + disp x 2 Longword: GBR + disp x4 Indexed GBR @(R0, indirect GBR) Effective address is sum of register GBR and GBR + R0 R0 contents. GBR + R0 GBR + R0 Rev. 4.00, 03/04, page 24 of 660 Addressing Mode Instruction Format Effective Address Calculation Method Effective address is register PC contents with 8-bit displacement disp added. After disp is zero-extended, it is multiplied by 2 (word), or 4 (longword), according to the operand size. With a longword operand, the lower 2 bits of PC are masked. PC (for longword) & H'FFFFFFFC + disp (zero-extended) x 2/4 PC + disp x 2 or PC&H'FFFFFFFC + disp x 4 Calculation Formula Word: PC + disp x 2 Longword: PC & H'FFFF FFFC + disp x 4 PC-relative @(disp:8, with PC) displacement PC-relative disp:8 Effective address is register PC contents with PC + disp x 2 8-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) x 2 + PC + disp x 2 disp:12 Effective address is register PC contents with PC + disp x 2 12-bit displacement disp added after being sign-extended and multiplied by 2. PC disp (sign-extended) x 2 + PC + disp x 2 Rev. 4.00, 03/04, page 25 of 660 Addressing Mode PC-relative Instruction Format Effective Address Calculation Method Rn Effective address is sum of register PC and Rn contents. PC + R0 PC + R0 Calculation Formula PC + Rn Immediate #imm:8 #imm:8 #imm:8 8-bit immediate data imm of TST, AND, OR, or XOR instruction is zero-extended. 8-bit immediate data imm of MOV, ADD, or CMP/EQ instruction is sign-extended. -- -- 8-bit immediate data imm of TRAPA -- instruction is zero-extended and multiplied by 4. Note: For the addressing modes below that use a displacement (disp), the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed according to the operand size. This is done to clarify the operation of the LSI. Refer to the relevant assembler notation rules for the actual assembler descriptions. @ (disp:4, Rn) ; Register indirect with displacement @ (disp:8, Rn) ; GBR indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12; PC-relative Rev. 4.00, 03/04, page 26 of 660 2.3.3 Instruction Formats Table 2.3 explains the meaning of instruction formats and source and destination operands. The meaning of the operands depends on the operation code. The following symbols are used. xxxx: mmmm: nnnn: iiii: dddd: Table 2.3 Operation code Source register Destination register Immediate data Displacement Instruction Formats Source Operand 0 xxxx xxxx nnnn Instruction Format 0 format 15 xxxx xxxx Destination Operand -- nnnn: register direct nnnn: register direct Instruction Example NOP MOVT Rn STS MACH,Rn -- -- Control register or system register Control register or system register xxxx 0 xxxx n format 15 xxxx nnnn: register STC.L indirect with pre- SR,@-Rn decrement Control register or system register Control register or system register -- -- LDC Rm,SR LDC.L @Rm+,SR JMP @Rm BRAF Rm m format 15 xxxx mmmm xxxx xxxx 0 mmmm: register direct mmmm: register indirect with postincrement mmmm: register indirect mmmm: PCrelative using Rm Rev. 4.00, 03/04, page 27 of 660 Instruction Format nm format 15 xxxx nnnn mmmm xxxx Source Operand 0 mmmm: register direct Destination Operand nnnn: register direct nnnn: register indirect MACH,MACL Instruction Example ADD Rm,Rn MOV.L Rm,@Rn MAC.W @Rm+,@Rn+ mmmm: register indirect mmmm: register indirect with postincrement (multiply-andaccumulate operation) nnnn: * register indirect with postincrement (multiply-andaccumulate operation) mmmm: register indirect with postincrement mmmm: register direct mmmm: register direct md format nd4 format 15 xxxx 15 xxxx xxxx nnnn dddd nnnn: register direct MOV.L @Rm+,Rn nnnn: register MOV.L indirect with pre- Rm,@-Rn decrement nnnn: indexed register indirect R0 (register direct) MOV.L Rm,@(R0,Rn) MOV.B @(disp,Rm),R 0 MOV.B R0,@(disp,Rn) xxxx mmmm dddd 0 mmmmdddd: register indirect with displacement 0 R0 (register direct) nnnndddd: register indirect with displacement Rev. 4.00, 03/04, page 28 of 660 Instruction Format nmd format 15 xxxx nnnn mmmm dddd Source Operand 0 mmmm: register direct Destination Operand Instruction Example nnnndddd: MOV.L register indirect Rm,@(disp,Rn) with displacement nnnn: register direct R0 (register direct) MOV.L @(disp,Rm),Rn MOV.L @(disp,GBR),R 0 MOV.L R0,@(disp,GB R) MOVA @(disp,PC),R0 BF label mmmmdddd: register indirect with displacement d format 15 xxxx xxxx dddd dddd 0 dddddddd: GBR indirect with displacement R0 (register direct) dddddddd: GBR indirect with displacement dddddddd: PC-relative with displacement dddddddd: PC-relative d12 format nd8 format i format 15 xxxx 15 xxxx nnnn dddd dddd R0 (register direct) -- -- dddd dddd dddd 0 dddddddddddd: PC-relative 0 dddddddd: PC-relative with displacement BRA label (label = disp + PC) MOV.L @(disp,PC),Rn AND.B #imm, @(R0,GBR) AND #imm,R0 TRAPA #imm ADD #imm,Rn nnnn: register direct Indexed GBR indirect R0 (register direct) -- nnnn: register direct 15 xxxx xxxx iiii iiii 0 iiiiiiii: immediate iiiiiiii: immediate iiiiiiii: immediate ni format 15 xxxx nnnn iiii iiii 0 iiiiiiii: immediate Note: * In a multiply-and-accumulate instruction, nnnn is the source register. . Rev. 4.00, 03/04, page 29 of 660 2.4 2.4.1 Instruction Set Instruction Set Classified by Function The SH7706 instruction set includes 68 basic instruction types, as listed in table 2.4. Table 2.4 Classification of Instructions Operation Code MOV MOVA MOVT SWAP XTRCT Arithmetic operations 21 ADD ADDC ADDV CMP/cond DIV1 DIV0S DIV0U DMULS DMULU DT EXTS EXTU MAC Function Data transfer Effective address transfer T bit transfer Swap of upper and lower bytes Extraction of middle of linked registers Binary addition Binary addition with carry Binary addition with overflow check Comparison Division Initialization of signed division Initialization of unsigned division Signed double-precision multiplication Unsigned double-precision multiplication Decrement and test Sign extension Zero extension Multiply-and-accumulate operation, doubleprecision multiply-and-accumulate operation 33 No. of Instructions 39 Classification Types Data transfer 5 Rev. 4.00, 03/04, page 30 of 660 Classification Types Arithmetic operations 21 Operation Code Function MUL MULS MULU NEG NEGC SUB SUBC SUBV Signed multiplication (16 x 16 bits) Unsigned multiplication (16 x 16 bits) Negation Negation with borrow Binary subtraction Binary subtraction with borrow Binary subtraction with underflow check Logical AND Bit inversion Logical OR Memory test and bit set Logical AND and T bit set Exclusive OR One-bit left rotation One-bit right rotation One-bit left rotation with T bit One-bit right rotation with T bit One-bit arithmetic left shift One-bit arithmetic right shift One-bit logical left shift n-bit logical left shift One-bit logical right shift n-bit logical right shift Dynamic arithmetic shift Dynamic logical shift No. of Instructions Double-precision multiplication (32 x 32 bits) 33 Logic operations 6 AND NOT OR TAS TST XOR 14 Shift 12 ROTL ROTR ROTCL ROTCR SHAL SHAR SHLL SHLLn SHLR SHLRn SHAD SHLD 16 Rev. 4.00, 03/04, page 31 of 660 Classification Types Branch 9 Operation Code BF BT BRA BRAF BSR BSRF JMP JSR RTS Function Conditional branch, delayed conditional branch (T = 0) Conditional branch, delayed conditional branch (T = 1) Unconditional branch Unconditional branch Branch to subroutine procedure Branch to subroutine procedure Unconditional branch Branch to subroutine procedure Return from subroutine procedure MAC register clear Clear T bit Clear S bit Load to control register Load to system register Load PTE to TLB No operation Prefetch data to cache Return from exception handling Set S bit Set T bit Shift to power-down mode Store from control register Store from system register Trap exception handling No. of Instructions 11 System control 15 CLRMAC CLRT CLRS LDC LDS LDTLB NOP PREF RTE SETS SETT SLEEP STC STS TRAPA 75 Total: 68 188 Rev. 4.00, 03/04, page 32 of 660 The instruction codes are listed from tables 2.5 to 2.10. Those tables are described according to the following items. Item Instruction mnemonic Format OP.Sz SRC,DEST Explanation OP: Operation code Sz: Size SRC: Source DEST: Destination Rm: Source register Rn: Destination register imm: Immediate data disp: Displacement mmmm: Source register nnnn: Destination register 0000: R0 0001: R1 ........... 1111: R15 iiii: Immediate data dddd: Displacement* Direction of transfer Memory operand Flag bits in SR Logical AND of each bit Logical OR of each bit Exclusive OR of each bit Logical NOT of each bit n-bit shift Indicates whether privileged mode applies Value when no wait states are inserted The execution cycles listed in the table are minimums. The actual number of cycles may be increased in cases such as the followings: 1. When contention occurs between instruction fetches and data access 2. When the destination register of the load instruction (memory register) and the register used by the next instruction are the same T bit Value of T bit after instruction is executed --: No change Note: * Scaling (x1, x2, x4) is performed according to the instruction operand size. Instruction code MSB LSB Operation summary , (xx) M/Q/T & | ^ ~ < Privileged mode Execution cycles Rev. 4.00, 03/04, page 33 of 660 Table 2.5 lists the data transfer instructions Table 2.5 Instruction MOV #imm,Rn Data Transfer Instructions Operation imm Sign extension Rn (disp x 2 + PC) Sign extension Rn (disp x 4 + PC) Rn Rm Rn Rm (Rn) Rm (Rn) Rm (Rn) (Rm) Sign extension Rn (Rm) Sign extension Rn (Rm) Rn Rn-1 Rn, Rm (Rn) Rn-2 Rn, Rm (Rn) Rn-4 Rn, Rm (Rn) (Rm) Sign extension Rn, Rm + 1 Rm (Rm) Sign extension Rn, Rm + 2 Rm Code 1110nnnniiiiiiii Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOV.W @(disp,PC),Rn 1001nnnndddddddd MOV.L MOV MOV.B MOV.W MOV.L MOV.B @(disp,PC),Rn Rm,Rn Rm,@Rn Rm,@Rn Rm,@Rn @Rm,Rn 1101nnnndddddddd 0110nnnnmmmm0011 0010nnnnmmmm0000 0010nnnnmmmm0001 0010nnnnmmmm0010 0110nnnnmmmm0000 MOV.W @Rm,Rn 0110nnnnmmmm0001 MOV.L MOV.B MOV.W MOV.L MOV.B @Rm,Rn Rm,@-Rn Rm,@-Rn Rm,@-Rn @Rm+,Rn 0110nnnnmmmm0010 0010nnnnmmmm0100 0010nnnnmmmm0101 0010nnnnmmmm0110 0110nnnnmmmm0100 MOV.W @Rm+,Rn 0110nnnnmmmm0101 MOV.L MOV.B MOV.W MOV.L MOV.B MOV.W @Rm+,Rn R0,@(disp,Rn) R0,@(disp,Rn) Rm,@(disp,Rn) @(disp,Rm),R0 @(disp,Rm),R0 (Rm) Rn,Rm + 4 Rm 0110nnnnmmmm0110 R0 (disp + Rn) R0 (disp x 2 + Rn) Rm (disp x 4 + Rn) (disp + Rm) Sign extension R0 (disp x 2 + Rm) Sign extension R0 (disp x 4 + Rm) Rn Rm (R0 + Rn) 10000000nnnndddd 10000001nnnndddd 0001nnnnmmmmdddd 10000100mmmmdddd 10000101mmmmdddd MOV.L MOV.B @(disp,Rm),Rn Rm,@(R0,Rn) 0101nnnnmmmmdddd 0000nnnnmmmm0100 Rev. 4.00, 03/04, page 34 of 660 Instruction MOV.W MOV.L MOV.B Rm,@(R0,Rn) Rm,@(R0,Rn) @(R0,Rm),Rn Operation Rm (R0 + Rn) Rm (R0 + Rn) (R0 + Rm) Sign extension Rn (R0 + Rm) Sign extension Rn (R0 + Rm) Rn Code 0000nnnnmmmm0101 0000nnnnmmmm0110 0000nnnnmmmm1100 Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- MOV.W @(R0,Rm),Rn 0000nnnnmmmm1101 MOV.L MOV.B MOV.W MOV.L MOV.B @(R0,Rm),Rn 0000nnnnmmmm1110 11000000dddddddd 11000001dddddddd 11000010dddddddd 11000100dddddddd R0,@(disp,GBR) R0 (disp + GBR) R0,@(disp,GBR) R0 (disp x 2 + GBR) R0,@(disp,GBR) R0 (disp x 4 + GBR) @(disp,GBR),R0 (disp + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 2 + GBR) Sign extension R0 @(disp,GBR),R0 (disp x 4 + GBR) R0 @(disp,PC),R0 Rn disp x 4 + PC R0 T Rn Rm Swap the bottom two bytes REG Rm Swap two consecutive words Rn Rm: Middle 32 bits of Rn Rn MOV.W 11000101dddddddd MOV.L MOVA MOVT 11000110dddddddd 11000111dddddddd 0000nnnn00101001 0110nnnnmmmm1000 0110nnnnmmmm1001 SWAP.B Rm,Rn SWAP.W Rm,Rn XTRCT Rm,Rn 0010nnnnmmmm1101 Rev. 4.00, 03/04, page 35 of 660 Table 2.6 lists the arithmetic instructions. Table 2.6 Instruction ADD ADD ADDC Rm,Rn #imm,Rn Rm,Rn Arithmetic Instructions Operation Rn + Rm Rn Rn + imm Rn Rn + Rm + T Rn, Carry T Rn + Rm Rn, Overflow T If R0 = imm, 1 T If Rn = Rm, 1 T If Rn Rm with unsigned data, 1 T If Rn Rm with signed data, 1 T If Rn > Rm with unsigned data, 1 T If Rn > Rm with signed data, 1 T If Rn 0, 1 T If Rn > 0, 1 T If Rn and Rm have an equivalent byte, 1 T Single-step division (Rn/Rm) MSB of Rn Q, MSB of Rm M, M ^ Q T 0 M/Q/T Code 0011nnnnmmmm1100 0111nnnniiiiiiii 0011nnnnmmmm1110 Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- Carry Overflow Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Comparison result Calculation result Calculation result 0 ADDV CMP/EQ Rm,Rn #imm,R0 0011nnnnmmmm1111 10001000iiiiiiii CMP/EQ Rm,Rn 0011nnnnmmmm0000 CMP/HS Rm,Rn 0011nnnnmmmm0010 CMP/GE Rm,Rn 0011nnnnmmmm0011 CMP/HI Rm,Rn 0011nnnnmmmm0110 CMP/GT CMP/PZ Rm,Rn Rn 0011nnnnmmmm0111 0100nnnn00010001 CMP/PL Rn 0100nnnn00010101 CMP/STR Rm,Rn 0010nnnnmmmm1100 DIV1 Rm,Rn 0011nnnnmmmm0100 DIV0S Rm,Rn 0010nnnnmmmm0111 DIV0U 0000000000011001 Rev. 4.00, 03/04, page 36 of 660 Instruction DMULS.L Rm,Rn Operation Signed operation of Rn x Rm MACH, MACL 32 x 32 64 bits Unsigned operation of Rn x Rm MACH, MACL 32 x 32 64 bits Rn - 1 Rn, if Rn = 0, 1 T, else 0 T A byte in Rm is signextended Rn A word in Rm is signextended Rn A byte in Rm is zeroextended Rn A word in Rm is zeroextended Rn Code 0011nnnnmmmm1101 Privileged Mode Cycles -- T Bit 2 to (5)* -- DMULU.L Rm,Rn 0011nnnnmmmm0101 -- 2 to (5)* -- DT Rn 0100nnnn00010000 -- -- -- -- -- -- 1 1 1 1 1 Comparison result -- -- -- -- EXTS.B Rm,Rn EXTS.W Rm,Rn 0110nnnnmmmm1110 0110nnnnmmmm1111 EXTU.B Rm,Rn 0110nnnnmmmm1100 EXTU.W Rm,Rn 0110nnnnmmmm1101 MAC.L @Rm+,@Rn+ Signed operation of (Rn) 0000nnnnmmmm1111 x (Rm) + MAC MAC, Rn + 4 Rn, Rm + 4 Rm 32 x 32 + 64 64 bits Signed operation of (Rn) 0100nnnnmmmm1111 x (Rm) + MAC MAC, Rn + 2 Rn, Rm + 2 Rm 16 x 16 + 64 64 bits Rn x Rm MACL 32 x 32 32 bits Signed operation of Rn x Rm MACL 16 x 16 32 bits Unsigned operation of Rn x Rm MACL 16 x 16 32 bits 0-Rm Rn 0-Rm-T Rn, Borrow T 0000nnnnmmmm0111 0010nnnnmmmm1111 2 to (5)* -- MAC.W @Rm+,@Rn+ -- 2 to (5)* -- MUL.L Rm,Rn -- -- 2 to (5)* -- 1 to (3)* -- MULS.W Rm,Rn MULU.W Rm,Rn 0010nnnnmmmm1110 -- 1 to (3)* -- NEG NEGC Rm,Rn Rm,Rn 0110nnnnmmmm1011 0110nnnnmmmm1010 -- -- 1 1 -- Borrow Rev. 4.00, 03/04, page 37 of 660 Instruction SUB SUBC Rm,Rn Rm,Rn Operation Rn-Rm Rn Rn-Rm-T Rn, Borrow T Rn-Rm Rn, Underflow T Code 0011nnnnmmmm1000 0011nnnnmmmm1010 Privileged Mode Cycles T Bit -- -- -- 1 1 1 -- Borrow Underflow SUBV Rm,Rn 0011nnnnmmmm1011 Note: * The normal number of execution cycles is shown. The value in parentheses is the number of cycles required in case of contention with the preceding or following instruction. Table 2.7 lists the logic operation instructions. Table 2.7 Instruction AND AND Rm,Rn #imm,R0 Logic Operation Instructions Operation Rn & Rm Rn R0 & imm R0 (R0 + GBR) & imm (R0 + GBR) ~Rm Rn Rn | Rm Rn R0 | imm R0 (R0 + GBR) | imm (R0 + GBR) If (Rn) is 0, 1 T; 1 MSB of (Rn)* Rn & Rm; if the result is 0, 1 T R0 & imm; if the result is 0, 1 T (R0 + GBR) & imm; if the result is 0, 1 T Rn ^ Rm Rn R0 ^ imm R0 (R0 + GBR) ^ imm (R0 + GBR) Code 0010nnnnmmmm1001 11001001iiiiiiii 11001101iiiiiiii Privileged Mode Cycles T Bit -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 1 3 1 1 1 3 4 1 1 3 1 1 3 -- -- -- -- -- -- -- Test result Test result Test result Test result -- -- -- AND.B #imm,@(R0,GBR) NOT OR OR OR.B Rm,Rn Rm,Rn #imm,R0 #imm,@(R0,GBR) 0110nnnnmmmm0111 0010nnnnmmmm1011 11001011iiiiiiii 11001111iiiiiiii TAS.B @Rn* 0100nnnn00011011 TST Rm,Rn 0010nnnnmmmm1000 TST #imm,R0 11001000iiiiiiii 11001100iiiiiiii TST.B #imm,@(R0,GBR) XOR XOR Rm,Rn #imm,R0 0010nnnnmmmm1010 11001010iiiiiiii 11001110iiiiiiii XOR.B #imm,@(R0,GBR) Note: * The on-chip DMAC's bus cycle is not inserted between the read and write cycles of the TAS instruction. The bus authority is not released by the BREQ. Rev. 4.00, 03/04, page 38 of 660 Table 2.8 lists the shift instructions. Table 2.8 Instruction ROTL ROTR ROTCL ROTCR SHAD Rn Rn Rn Rn Rm,Rn Shift Instructions Operation T Rn MSB LSB Rn T T Rn T T Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [MSB Rn] T Rn 0 MSB Rn T Rn 0: Rn << Rm Rn Rn < 0: Rn >> Rm [0 Rn] T Rn 0 0 Rn T Rn << 2 Rn Rn >> 2 Rn Rn << 8 Rn Rn >> 8 Rn Rn << 16 Rn Rn >> 16 Rn Code 0100nnnn00000100 0100nnnn00000101 0100nnnn00100100 0100nnnn00100101 0100nnnnmmmm1100 Privileged Mode Cycles T Bit -- -- -- -- -- 1 1 1 1 1 MSB LSB MSB LSB -- SHAL SHAR SHLD Rn Rn Rm,Rn 0100nnnn00100000 0100nnnn00100001 0100nnnnmmmm1101 -- -- -- 1 1 1 MSB LSB -- SHLL SHLR SHLL2 SHLR2 SHLL8 SHLR8 Rn Rn Rn Rn Rn Rn 0100nnnn00000000 0100nnnn00000001 0100nnnn00001000 0100nnnn00001001 0100nnnn00011000 0100nnnn00011001 0100nnnn00101000 0100nnnn00101001 -- -- -- -- -- -- -- -- 1 1 1 1 1 1 1 1 MSB LSB -- -- -- -- -- -- SHLL16 Rn SHLR16 Rn Rev. 4.00, 03/04, page 39 of 660 Table 2.9 lists the branch instructions. Table 2.9 Instruction BF label Branch Instructions Operation If T = 0, disp x 2 + PC PC; if T = 1, nop (where label is disp + PC) Delayed branch, if T = 0, disp x 2 + PC PC; if T = 1, nop Delayed branch, if T = 1, disp x 2 + PC PC; if T = 0, nop If T = 1, disp x 2 + PC PC; if T = 0, nop Delayed branch, disp x 2 + PC PC Delayed branch, Rm + PC PC Delayed branch, PC PR, disp x 2 + PC PC Delayed branch, PC PR, Rm + PC PC Delayed branch, Rm PC Delayed branch, PC PR, Rm PC Delayed branch, PR PC Code 10001011dddddddd Privileged Mode -- Cycles 3/1* T Bit -- BF/S label 10001111dddddddd -- 2/1* -- BT label 10001001dddddddd -- 3/1* -- BT/S label 10001101dddddddd -- -- -- -- -- -- -- -- 2/1* 2 2 2 2 2 2 2 -- -- -- -- -- -- -- -- BRA label 1010dddddddddddd BRAF BSR Rm label 0000mmmm00100011 1011dddddddddddd BSRF Rm 0000mmmm00000011 JMP JSR @Rm @Rm 0100mmmm00101011 0100mmmm00001011 RTS 0000000000001011 Note:* One state when there is no branch. Rev. 4.00, 03/04, page 40 of 660 Table 2.10 lists the system control instructions. Table 2.10 System Control Instructions Privileged Instruction Operation Code Mode Cycles T Bit CLRMAC CLRS CLRT LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC LDC Rm,SR Rm,GBR Rm,VBR Rm,SSR Rm,SPC Rm,R0_BANK Rm,R1_BANK Rm,R2_BANK Rm,R3_BANK Rm,R4_BANK Rm,R5_BANK Rm,R6_BANK Rm,R7_BANK 0 MACH, MACL 0S 0T Rm SR Rm GBR Rm VBR Rm SSR Rm SPC Rm R0_BANK Rm R1_BANK Rm R2_BANK Rm R3_BANK Rm R4_BANK Rm R5_BANK Rm R6_BANK Rm R7_BANK (Rm) SR, Rm + 4 Rm (Rm) GBR, Rm + 4 Rm (Rm) VBR, Rm + 4 Rm (Rm) SSR, Rm + 4 Rm (Rm) SPC, Rm + 4 Rm (Rm) R0_BANK, Rm + 4 Rm (Rm) R1_BANK, Rm + 4 Rm (Rm) R2_BANK, Rm + 4 Rm (Rm) R3_BANK, Rm + 4 Rm 0000000000101000 0000000001001000 0000000000001000 0100mmmm00001110 0100mmmm00011110 0100mmmm00101110 0100mmmm00111110 0100mmmm01001110 0100mmmm10001110 0100mmmm10011110 0100mmmm10101110 0100mmmm10111110 0100mmmm11001110 0100mmmm11011110 0100mmmm11101110 0100mmmm11111110 0100mmmm00000111 0100mmmm00010111 0100mmmm00100111 0100mmmm00110111 0100mmmm01000111 0100mmmm10000111 -- -- -- 1 1 1 5 3 3 3 3 3 3 3 3 3 3 3 3 7 5 5 5 5 5 5 5 5 -- -- 0 LSB -- -- -- -- -- -- -- -- -- -- -- -- LSB -- -- -- -- -- -- -- -- -- -- LDC.L @Rm+,SR LDC.L @Rm+,GBR LDC.L @Rm+,VBR LDC.L @Rm+,SSR LDC.L @Rm+,SPC LDC.L @Rm+, R0_BANK LDC.L @Rm+, R1_BANK LDC.L @Rm+, R2_BANK LDC.L @Rm+, R3_BANK 0100mmmm10010111 0100mmmm10100111 0100mmmm10110111 Rev. 4.00, 03/04, page 41 of 660 Privileged Instruction Operation Code Mode Cycles T Bit LDC.L @Rm+, R4_BANK LDC.L @Rm+, R5_BANK LDC.L @Rm+, R6_BANK LDC.L @Rm+, R7_BANK LDS LDS LDS Rm,MACH Rm,MACL Rm,PR (Rm) R4_BANK, Rm + 4 Rm (Rm) R5_BANK, Rm + 4 Rm (Rm) R6_BANK, Rm + 4 Rm (Rm) R7_BANK, Rm + 4 Rm Rm MACH Rm MACL Rm PR (Rm) MACH, Rm + 4 Rm (Rm) MACL, Rm + 4 Rm (Rm) PR, Rm + 4 Rm PTEH/PTEL TLB No operation 0100mmmm11000111 -- -- -- -- -- -- 5 5 5 5 1 1 1 1 1 1 1 1 2 4 1 1 4* 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 1 -- -- -- -- -- -- -- -- -- -- 0100mmmm11010111 0100mmmm11100111 0100mmmm11110111 0100mmmm00001010 0100mmmm00011010 0100mmmm00101010 0100mmmm00000110 0100mmmm00010110 0100mmmm00100110 0000000000111000 0000000000001001 0000mmmm10000011 0000000000101011 0000000001011000 0000000000011000 0000000000011011 0000nnnn00000010 0000nnnn00010010 0000nnnn00100010 0000nnnn00110010 0000nnnn01000010 0000nnnn10000010 0000nnnn10010010 0000nnnn10100010 0000nnnn10110010 LDS.L @Rm+,MACH LDS.L @Rm+,MACL LDS.L @Rm+,PR LDTLB NOP PREF RTE SETS SETT SLEEP STC STC STC STC STC STC STC STC STC SR,Rn GBR,Rn VBR,Rn SSR,Rn SPC,Rn R0_BANK,Rn R1_BANK,Rn R2_BANK,Rn R3_BANK,Rn @Rm -- (Rm) cache Delayed branch, SSR/SPC SR/PC 1S 1T Sleep SR Rn GBR Rn VBR Rn SSR Rn SPC Rn R0_BANK Rn R1_BANK Rn R2_BANK Rn R3_BANK Rn -- -- -- -- Rev. 4.00, 03/04, page 42 of 660 Privileged Instruction Operation Code Mode Cycles T Bit STC STC STC STC R4_BANK,Rn R5_BANK,Rn R6_BANK,Rn R7_BANK,Rn R4_BANK Rn R5_BANK Rn R6_BANK Rn R7_BANK Rn Rn-4 Rn, SR (Rn) Rn-4 Rn, GBR (Rn) Rn-4 Rn, VBR (Rn) Rn-4 Rn, SSR (Rn) Rn-4 Rn, SPC (Rn) Rn-4 Rn, R0_BANK (Rn) Rn-4 Rn, R1_BANK (Rn) Rn-4 Rn, R2_BANK (Rn) Rn-4 Rn, R3_BANK (Rn) Rn-4 Rn, R4_BANK (Rn) Rn-4 Rn, R5_BANK (Rn) Rn-4 Rn, R6_BANK (Rn) Rn-4 Rn, R7_BANK (Rn) MACH Rn MACL Rn PR Rn Rn-4 Rn, MACH (Rn) Rn-4 Rn, MACL (Rn) Rn-4 Rn, PR (Rn) PC SPC, SR SSR, imm TRA 0000nnnn11000010 0000nnnn11010010 0000nnnn11100010 0000nnnn11110010 0100nnnn00000011 0100nnnn00010011 0100nnnn00100011 0100nnnn00110011 0100nnnn01000011 0100nnnn10000011 -- 1 1 1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- STC.L SR,@-Rn STC.L GBR,@-Rn STC.L VBR,@-Rn STC.L SSR,@-Rn STC.L SPC,@-Rn STC.L R0_BANK, @-Rn STC.L R1_BANK, @-Rn STC.L R2_BANK, @-Rn STC.L R3_BANK, @-Rn STC.L R4_BANK, @-Rn STC.L R5_BANK, @-Rn STC.L R6_BANK, @-Rn STC.L R7_BANK, @-Rn STS STS STS MACH,Rn MACL,Rn PR,Rn -- -- -- -- -- -- -- 0100nnnn10010011 0100nnnn10100011 0100nnnn10110011 0100nnnn11000011 0100nnnn11010011 0100nnnn11100011 0100nnnn11110011 0000nnnn00001010 0000nnnn00011010 0000nnnn00101010 0100nnnn00000010 0100nnnn00010010 0100nnnn00100010 11000011iiiiiiii STS.L MACH,@-Rn STS.L MACL,@-Rn STS.L PR,@-Rn TRAPA #imm Rev. 4.00, 03/04, page 43 of 660 Notes: * The number of cycles until the sleep state is entered. 1. The table shows the minimum number of execution cycles. The actual number of instruction execution cycles will increase in cases such as the followings: a. When there is contention between an instruction fetch and data access b. When the destination register in a load (memory-to-register) instruction is also used by the next instruction 2. With the addressing modes using displacement (disp) listed below, the assembler descriptions in this manual show the value before scaling (x1, x2, or x4) is performed. This is done to clarify the operation of the chip. For the actual assembler descriptions, refer to the individual assembler notation rules. @ (disp:4, Rn) ; Register-indirect with displacement @ (disp:8, Rn) ; GBR-indirect with displacement @ (disp:8, PC) ; PC-relative with displacement disp:8, disp:12 ; PC-relative Rev. 4.00, 03/04, page 44 of 660 2.4.2 Instruction Code Map Table 2.11 shows the instruction code map. Table 2.11 Instruction Code Map Instruction Code MSB 0000 0000 0000 0000 0000 0000 0000 0000 0000 Rn Rn Rn Rn Rn Rn Rm Rm Rn Fx Fx LSB 0000 0001 SR,Rn SPC,Rn R0_BANK,Rn R4_BANK,Rn Rm @Rm Rm,@(R0,Rn) MOV.W SETT SETS DIV0U Rm,@(R0,Rn) MOV.L CLRMAC Rm,@(R0,Rn) MUL.L LDTLB Rm,Rn STC STC R1_BANK,Rn R5_BANK,Rn STC STC BRAF R2_BANK,Rn R6_BANK,Rn Rm STC STC R3_BANK,Rn R7_BANK,Rn STC GBR,Rn STC VBR,Rn STC SSR,Rn Fx: 0000 MD: 00 Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 00MD 0010 STC 01MD 0010 STC 10MD 0010 STC 11MD 0010 STC 00MD 0011 BSRF 10MD 0011 PREF Rm 01MD MOV.B 0000 0000 00MD 1000 CLRT 0000 0000 01MD 1000 CLRS 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0010 0010 0010 0010 0011 0011 0011 0011 Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Rn Fx Fx Fx Fx Fx Fx Fx Rm Rm Rm Rm Rm Rm Rm Rm Rm Rm 1001 NOP 1010 1011 RTS 1000 1001 1010 STS 1011 11MD MOV.B disp MOV.L 00MD MOV.B 01MD MOV.B 10MD TST @(R0,Rm),Rn Rm,@(disp:4,Rn) Rm,@Rn Rm,@-Rn Rm,Rn MACH,Rn SLEEP RTE MOVT STS MACL,Rn STS Rn PR,Rn MOV.W @(R0,Rm),Rn MOV.L @(R0,Rm),Rn MAC.L @Rm+,@Rn+ MOV.W MOV.W AND XTRCT Rm,@Rn Rm,@-Rn Rm,Rn Rm,Rn MOV.L MOV.L XOR MULU.W CMP/HS Rm,@Rn Rm,@-Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn DIV0S OR MULSW CMP/GE CMP/GT SUBV ADDV Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn Rm,Rn 11MD CMP/STR Rm,Rn 00MD CMP/EQ 01MD DIV1 10MD SUB 11MD ADD Rm,Rn Rm,Rn Rm,Rn Rm,Rn DMULU.L Rm,Rn CMP/HI SUBC DMULS.L Rm,Rn ADDC Rev. 4.00, 03/04, page 45 of 660 Instruction Code MSB 0100 0100 0100 0100 0100 0100 Rn Rn Rn Rn Rn Rn Fx Fx Fx LSB 0000 SHLL 0001 SHLR 0010 STS.L Fx: 0000 MD: 00 Rn Rn MACH,@-Rn SR,@-Rn SPC,@-Rn R0_BANK,@-Rn STC.L DT CMP/PZ STS.L STC.L Fx: 0001 MD: 01 Rn Rn MACL,@-Rn GBR,@-Rn SHAL SHAR STS.L STC.L Fx: 0010 MD: 10 Rn Rn PR,@-Rn VBR,@-Rn Fx: 0011 to 1111 MD: 11 00MD 0011 STC.L 01MD 0011 STC.L 10MD 0011 STC.L STC.L SSR,@-Rn R1_BANK,@-Rn STC.L R2_BANK,@-Rn STC.L Rn R3_BANK,@- 0100 Rn 11MD 0011 STC.L R4_BANK,@-Rn STC.L R5_BANK,@-Rn STC.L R6_BANK,@-Rn STC.L Rn R7_BANK,@- 0100 0100 0100 0100 0100 0100 Rn Rn Rm Rm Rm Rm Fx Fx Fx 0100 ROTL 0101 ROTR 0110 LDS.L Rn Rn @Rm+,MACH @Rm+,SR @Rm+,SPC @Rm+,R0_BANK LDC.L @Rm+,R1_BANK CMP/PL LDS.L LDC.L Rn @Rm+,MACL @Rm+,GBR ROTCL ROTCR LDS.L LDC.L Rn Rn @Rm+,PR @Rm+,VBR LDC.L @Rm+,SSR 00MD 0111 LDC.L 01MD 0111 LDC.L 10MD 0111 LDC.L LDC.L @Rm+,R2_BANK LDC.L @Rm+,R3_B ANK 0100 Rm 11MD 0111 LDC.L @Rm+,R4_BANK LDC.L @Rm+,R5_BANK LDC.L @Rm+,R6_BANK LDC.L @Rm+,R7_B ANK 0100 0100 0100 0100 Rn Rn Rm Rm/ Rn Fx Fx Fx Fx 1000 SHLL2 1001 SHLR2 1010 LDS 1011 JSR Rn Rn Rm,MACH @Rm SHLL8 SHLR8 LDS TAS.B Rn Rn Rm,MACL @Rn SHLL16 SHLR16 LDS JMP Rn Rn Rm,PR @Rm 0100 0100 0100 0100 0100 0100 0100 0101 0110 0110 0110 0110 0111 Rn Rn Rm Rm Rm Rm Rn Rn Rn Rn Rn Rn Rn Rm Rm 1100 SHAD 1101 SHLD Rm,Rn Rm,Rn Rm,SR Rm,SPC Rm,R0_BANK Rm,R4_BANK @Rm+,@Rn+ @(disp:4,Rm),Rn @Rm,Rn @Rm+,Rn Rm,Rn Rm,Rn #imm:8,Rn MOV.W MOV.W SWAP.W EXTU.W @Rm,Rn @Rm+,Rn Rm,Rn Rm,Rn MOV.L MOV.L NEGC EXTS.B @Rm,Rn @Rm+,Rn Rm,Rn Rm,Rn MOV NOT NEG EXTS.W Rm,Rn Rm,Rn Rm,Rn Rm,Rn LDC LDC Rm,R1_BANK Rm,R5_BANK LDC LDC Rm,R2_BANK Rm,R6_BANK LDC LDC Rm,R3_BANK Rm,R7_BANK LDC Rm,GBR LDC Rm,VBR LDC Rm,SSR 00MD 1110 LDC 01MD 1110 LDC 10MD 1110 LDC 11MD 1110 LDC Rm Rm Rm Rm Rm Rm 1111 MAC.W disp MOV.L 00MD MOV.B 01MD MOV.B 10MD SWAP.B 11MD EXTU.B ADD imm Rev. 4.00, 03/04, page 46 of 660 Instruction Code MSB 1000 00MD Rn LSB disp MOV.B Fx: 0000 MD: 00 MOV.W Fx: 0001 MD: 01 Fx: 0010 MD: 10 Fx: 0011 to 1111 MD: 11 R0,@(disp:4,Rn) 1000 01MD Rm disp MOV.B @(disp:4,Rm),R0 1000 10MD 1000 11MD 1001 1010 1011 1100 00MD Rn imm/disp imm/disp disp disp disp imm/disp MOV.W BRA BSR MOV.B R0,@(disp:8,GBR) 1100 01MD disp MOV.B @(disp:8,GBR),R0 1100 10MD 1100 11MD imm imm TST TST.B #imm:8,@(R0,GBR) Rn 1101 1110 1111 Rn imm MOV #imm:8,Rn disp MOV.L @(disp:8,PC),Rn #imm:8,R0 @(DISP:8,PC),RN label:12 label:12 CMP/EQ #imm:8,R0 R0,@(disp:4,Rn) MOV.W @(disp:4,Rm),R0 BT BT/S label:8 label:8 BF BF/S label:8 label:8 MOV.W R0,@(disp:8,GBR) MOV.W @(disp:8,GBR),R0 AND AND.B #imm:8,@(R0,GBR) #imm:8,R0 MOV.L R0,@(disp:8,GBR) MOV.L @(disp:8,GBR),R0 XOR XOR.B #imm:8,@(R0,GBR) #imm:8,R0 TRAPA #imm:8 MOVA @(disp:8,PC),R0 OR OR.B #imm:8,@(R0,GBR) #imm:8,R0 ************ Note: See the SH-3/SH-3E/SH3-DSP Programming Manual for details. Rev. 4.00, 03/04, page 47 of 660 2.5 2.5.1 Processor States and Processor Modes Processor States The SH7706 has five processor states: the reset state, exception-handling state, bus-released state, program execution state, and power-down state. Reset State: In this state the CPU is reset. The CPU enters the power-on reset state if the RESETP pin is low, or the manual reset state if the RESETM pin is low. See section 4, Exception Processing, for more information on resets. In the power-on reset state, the internal states of the CPU and the on-chip supporting module registers are initialized. In the manual reset state, the internal states of the CPU and registers of onchip supporting modules other than the bus state controller (BSC) are initialized. Refer to the register descriptions in the relevant sections for further details. Exception-Handling State: This is a transient state during which the CPU's processor state flow is altered by a reset, general exception, or interrupt exception handling. In the case of a reset, the CPU branches to address H'A0000000 and starts executing the usercoded exception handling program. In the case of a general exception or interrupt, the program counter (PC) contents are saved in the saved program counter (SPC) and the status register (SR) contents are saved in the saved status register (SSR). The CPU branches to the start address of the user-coded exception service routine found from the sum of the contents of the vector base address and the vector offset. See section 4, Exception Processing, for more information on resets, general exceptions, and interrupts. Program Execution State: In this state the CPU executes program instructions in sequence. Power-Down State: In the power-down state, CPU operation halts and power consumption is reduced. There are three modes in the power-down state: sleep mode, software standby mode and hardware standby mode. The software standby mode and hardware standby mode are expressed by a generlc name, standby mode. See section 22, Power-Down Modes, for more information. Bus-Released State: In this state the CPU has released the bus to a device that requested it. Transitions between the states are shown in figure 2.6. Rev. 4.00, 03/04, page 48 of 660 From any state when RESETP = 0 From any state but hardware standby mode or bus-released state when RESETM = 0 Power-on reset state RESETP = 0 Manual reset state Reset state RESETP = 1 RESETM = 1 Exception-handling state req ue st e nc ara cle t es Exception Interrupt s Bu sr Bu eq u Bus-released state Bus cle reque ara nce st Bus req Program execution state ues t interrupt End of exception transition processing Interrupt Bus request Bus request clearance SLEEP instruction with STBY bit cleared SLEEP instruction with STBY bit set Sleep mode Software standby mode Hardware standby mode* Power-down state CA = 1, RESETP=0 Note: * The hardware standby mode is entered when the CA pin goes low level from any state. Figure 2.6 Processor State Transitions Rev. 4.00, 03/04, page 49 of 660 2.5.2 Processor Modes There are two processor modes: privileged mode and user mode. The processor mode is determined by the processor mode bit (MD) in the status register (SR). User mode is selected when the MD bit is 0, and privileged mode when the MD bit is 1. When the reset state or exception state is entered, the MD bit is set to 1. When exception handling ends, the MD bit is cleared to 0 and user mode is entered. There are certain registers and bits which can only be accessed in privileged mode. Rev. 4.00, 03/04, page 50 of 660 Section 3 Memory Management Unit (MMU) This LSI has an on-chip memory management unit (MMU) that implements address translation. This LSI's features a resident translation look-aside buffer (TLB) that caches information for usercreated address translation tables located in external memory. It enables high-speed translation of virtual addresses into physical addresses. Address translation uses the paging system and supports two page sizes (1 kbyte and 4 kbytes). The access right to virtual address space can be set for privileged and user modes to provide memory protection. 3.1 Role of MMU The MMU is a feature designed to make efficient use of physical memory. As shown in figure 3.1, if a process is smaller in size than the physical memory, the entire process can be mapped onto physical memory. However, if the process increases in size to the extent that it no longer fits into physical memory, it becomes necessary to partition the process and to map those parts requiring execution onto memory as occasion demands (figure 3.1(1)). Having the process itself consider this mapping onto physical memory would impose a large burden on the process. To lighten this burden, the idea of virtual memory was born as a means of performing en bloc mapping onto physical memory (figure 3.1(2)). In a virtual memory system, substantially more virtual memory than physical memory is provided, and the process is mapped onto this virtual memory. Thus a process only has to consider operation in virtual memory. Mapping from virtual memory to physical memory is handled by the MMU. The MMU is normally controlled by the operating system, switching physical memory to allow the virtual memory required by a process to be mapped onto physical memory in a smooth fashion. Switching of physical memory is carried out via secondary storage, etc. The virtual memory system that came into being in this way is particularly effective in a timesharing system (TSS) in which a number of processes are running simultaneously (figure 3.1(3)). If processes running in a TSS had to take mapping onto virtual memory into consideration while running, it would not be possible to increase efficiency. Virtual memory is thus used to reduce this load on the individual processes and so improve efficiency (figure 3.1(4)). In the virtual memory system, virtual memory is allocated to each process. The task of the MMU is to perform efficient mapping of these virtual memory areas onto physical memory. It also has a memory protection feature that prevents one process from inadvertently accessing another process's physical memory. When address translation from virtual memory to physical memory is performed using the MMU, it may occur that the relevant translation information is not recorded in the MMU, with the result that one process may inadvertently access the virtual memory allocated to another process. In this case, the MMU will generate an exception, change the physical memory mapping, and record the new address translation information. Rev. 4.00, 03/04, page 51 of 660 Although the functions of the MMU could also be implemented by software alone, the need for translation to be performed by software each time a process accesses physical memory would result in poor efficiency. For this reason, a buffer for address translation (translation look-aside buffer: TLB) is provided in hardware to hold frequently used address translation information. The TLB can be described as a cache for storing address translation information. Unlike cache memory, however, if address translation fails, that is, if an exception is generated, switching of address translation information is normally performed by software. This makes it possible for memory management to be performed flexibly by software. The MMU has two methods of mapping from virtual memory to physical memory: a paging method using fixed-length address translation, and a segment method using variable-length address translation. With the paging method, the unit of translation is a fixed-size address space (usually of 1 to 64 kbytes) called a page. In the following text, this LSI's address space in virtual memory is referred to as virtual address space, and address space in physical memory as physical memory space. Virtual memory Process 1 Physical memory Process 1 Physical memory Process 1 MMU Physical memory (1) (2) Process 1 Process 1 Physical memory Virtual memory MMU ;;; Process 2 Process 3 ;;;;;;;;;;;; ;;;;;;;;;;;; ;; ; ; ; ; ; ; ; ; ;;;;;;;;;;;; ; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ; Process 2 ;;;;;;;;;;; ;; ; ; ; ;;;;;;;;;;;; ; ;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ; ;;;;;;;;;;;; ; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;; ; Process 3 ;;;; Physical memory ;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ; ; ; ;; ;;;;;;;;;;;;; ;;;; ; ;; ; ;; ; ; ;;;;;;;;;;;;; ;;;;;;;;;;;; ; ;;; ;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;;;;;;;;;;;;; ;; ;;;;;;;;;; ;;;;;;;;;;;; ;; (3) (4) Figure 3.1 MMU Functions Rev. 4.00, 03/04, page 52 of 660 3.1.1 This LSI's MMU Virtual Address Map: This LSI uses 32-bit virtual addresses to access a 4-Gbyte virtual address space that is divided into several areas. Address space mapping is shown in figure 3.2. In the privileged mode, the virtual address space is divided into five areas. P0 and P3 areas are mapped to physical address spaces in page units according to the information in the address translation table. Write-back or write-through can be selected for write access by means of a cache control register (CCR) setting. Mapping of the P1 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P1 area, setting a virtual address MSBs (bit 31) to 0 generates the corresponding physical address. P1 area access can be cached, write-back or write-through can be selected according to the setting of CCR whether to cache or not. Mapping of the P2 area is fixed to physical address space (H'00000000 to H'1FFFFFFF). In the P2 area, setting the top three virtual address bits (bits 31, 30, and 29) to 0 generates the corresponding physical address. P2 area access cannot be cached. The P1 and P2 areas are not mapped by the address translation table, so the TLB is not used and no exceptions like TLB misses occur. Initialization of MMU-related registers, exception processing, and the like are located in the P1 and P2 areas. Because the P1 area is cached, handlers that require high-speed processing are placed there. A part of the control register in the peripheral module is allocated in P2 area. The P4 area is used for mapping on-chip control register addresses. Address spaces from H'E0000000 to H'EFFFFFFF and from H'F4000000 to H'FBFFFFFF are reserved. An operation of this LSI is not guaranteed when these address spaces are accessed. Address space from H'F0000000 to H'F1FFFFFF is assigned to the cache, and address space from H'F2000000 to H'F3FFFFFF is assigned to the TLB. Address space from H'FC000000 to H'FFFFFFFF is a space for control registers. However, an operation of this LSI is not guaranteed when an address space that is not assigned to any control register is accessed. In the user mode, 2 Gbytes of the virtual address space from H'00000000 to H'7FFFFFFF (area U0) can be accessed. U0 is mapped onto physical address space in page units. Write-back or writethrough mode can be selected for write accesses by means of CCR setting. 2 Gbytes of the virtual address space from H'80000000 to H'FFFFFFFF cannot be accessed in the user mode. Attempting to do so creates an CPU address error. Write-back or write-through can be selected for write access by means of the CCR setting. Rev. 4.00, 03/04, page 53 of 660 H'00000000 H'00000000 2-Gbyte virtual space, cacheable (write-back/write-through) Area P0 2-Gbyte virtual space, cacheable (write-back/write-through) Area U0 H'80000000 0.5-Gbyte fixed physical space, cacheable (write-back/write-through) H'A0000000 0.5-Gbyte fixed physical space, non-cacheable H'C0000000 0.5-Gbyte virtual space, cacheable (write-back/write-through) H'E0000000 0.5-Gbyte control space, non-cacheable H'FFFFFFFF Privileged mode Area P4 Area P3 Area P2 Area P1 H'80000000 CPU Address error H'FFFFFFFF User mode Figure 3.2 Virtual Address Space Mapping Rev. 4.00, 03/04, page 54 of 660 Physical Address Space: This LSI supports a 32-bit physical address space, but the upper 3 bits are actually ignored and treated as a shadow. See section 8, Bus State Controller (BSC), for details. Address Translation: When the MMU is enabled, the virtual address space is divided into units called pages. Physical addresses are translated in page units. Address translation tables in external memory hold information such as the physical address that corresponds to the virtual address and memory protection codes. When an access to areas P1 or P2 occurs, there is no TLB access and the physical address is defined uniquely by hardware. If it belongs to area P0, P3 or U0, the TLB is searched by virtual address and, if that virtual address is registered in the TLB, the access hits the TLB. The corresponding physical address and the page control information are read from the TLB and the physical address is determined. If the virtual address is not registered in the TLB, a TLB miss exception occurs and processing will shift to the TLB miss handler. In the TLB miss handler, the TLB address translation table in external memory is searched and the corresponding physical address and the page control information are registered in the TLB. After returning from the handler, the instruction that caused the TLB miss is re-executed. When the MMU is enabled, address translation information that results in a physical address space of H'80000000 to H'FFFFFFFF should not be registered in the TLB. When the MMU is disabled, the virtual address is used directly as the physical address. As this LSI supports a 29-bit address space as the physical address space, the top 3 bits of the physical address are ignored, and constitute a shadow space. For example, addresses H'00001000 in the P0 area, H'80001000 in the P1 area, H'A0001000 in the P2 area, and H'C0001000 in the P3 area are all mapped onto the same physical address. When access to these addresses is performed with the cache enabled, an address with the top 3 bits of the physical address masked to 0 is stored in the cache address array to ensure data congruity. Single Virtual Memory Mode and Multiple Virtual Memory Mode: There are two virtual memory modes: single virtual memory mode and multiple virtual memory mode. In single virtual memory mode, multiple processes run in parallel using the virtual address space exclusively and the physical address corresponding to a given virtual address is specified uniquely. In multiple virtual memory mode, multiple processes run in parallel sharing the virtual address space, so a given virtual address may be translated into different physical addresses depending on the process. By the value set to the MMU control register (MMUCR), either single or multiple virtual mode is selected. In terms of operation, the only difference between single virtual memory mode and multiple virtual memory mode is the TLB address comparison method. Rev. 4.00, 03/04, page 55 of 660 Address Space Identifier (ASID): In multiple virtual memory mode, the address space identifier (ASID) is used to differentiate between processes running in parallel and sharing virtual address space. The ASID is 8 bits in length and can be set by software setting of the ASID of the currently running process in page table entry register high (PTEH) within the MMU. When the process is switched using the ASID, the TLB does not have to be purged. In single virtual memory mode, the ASID is used to provide memory protection for processes running simulataneously and using the virtual address space exclusively. 3.2 Register Description There are five registers for MMU processing. These are located in address space area P4 and can only be accessed from privileged mode by specifying the address. These registers for MMU processing are shown below. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Page table entry register high (PTEH) * Page table entry register low (PTEL) * Translation table base register (TTB) * TLB exception address register (TEA) * MMU control register (MMUCR) 3.2.1 Page Table Entry Register High (PTEH) The page table entry register high (PTEH) consists of a virtual page number (VPN) and ASID. The VPN is set the VPN of the virtual address at which the exception is generated in case of an MMU exception or CPU address error exception. When the page size is 4 kbytes, the VPN is the upper 20 bits of the virtual address, but in this case the upper 22 bits of the virtual address are set. The VPN can also be modified by software. As the ASID, software sets the number of the currently executing process. The VPN and ASID are recorded in the TLB by the LDTLB instruction. Bit 31 to 10 9, 8 Bit Name VPN Initial Value R/W All 0 R/W R Description Virtual page number Reserved These bits are always read as 0. The write value should always be 0. 7 to 0 ASID R/W Address space identifier Rev. 4.00, 03/04, page 56 of 660 3.2.2 Page Table Entry Register Low (PTEL) The page table entry register low register (PTEL) is used to store the physical page number and page management information to be recorded in the TLB by the LDTLB instruction. The contents of this register are only modified by a software command. Bit 31 to 10 9 8 7 6, 5 4 3 2 1 0 Bit Name PPN V PR SZ C D SH Initial Value R/W 0 0 0 R/W R R/W R R/W R/W R/W R/W R/W R Description Physical page number Page management information Refer to section 3.3 TLB Functions. 3.2.3 The Translation Table Base Register (TTB) The translation table base register (TTB) is a 32-bit register. TTB is used to store the base address of the current page table. The contents of this register are only modified in response to a software command. TTB is available to use by software for general purposes. 3.2.4 The TLB Exception Address Register (TEA) The TLB exception address register (TEA) is a 32-bit register. TEA is used to store the virtual address corresponding to a MMU or CPU address error exception after these exceptions has occurred. This value remains valid until the next exception or interrupt occurs. Rev. 4.00, 03/04, page 57 of 660 3.2.5 MMU Control Register (MMUCR) The MMU control register (MMUCR) makes the MMU settings. Any program that modifies MMUCR should reside in the P1 or P2 area. Bit Bit Name Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 SV R/W Single virtual memory mode 0: multiple virtual memory mode 1: single virtual memory mode 7, 6 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5, 4 RC All 0 R/W Random counter A 2-bit random counter, automatically updated by hardware according to the following rules in the event of an MMU exception. When a TLB miss exception occurs, all TLB entry ways corresponding to the virtual address at which the exception occurred are checked, and if all ways are valid, 1 is added to RO; if there is one or more invalid ways, they are set by priority from way 0, in the order: way 0, way 1, way 2, way 3. In the event of an MMU exception other than a TLB miss exception, the way which caused the exception is set in RC. 3 0 R Reserved This bit is always read as 0. The write value should always be 0. 2 TF 0 R/W TLB flush When 1 is set, all valid bits of TLB are cleared to 0 (flush). This bit is always reads as 0. 1 IX 0 R/W Index mode When 0, VPN bits 16 to 12 are used as the TLB index number. When 1, the value obtained by EX-ORing ASID bits 4 to 0 in PTEH and VPN bits 16 to 12 are used as the TLB index number. 0 AT 0 R/W Address translation Enables (valid) or disables (invalid) the MMU. 0: MMU disabled 1: MMU enabled 31 to 9 Rev. 4.00, 03/04, page 58 of 660 3.3 3.3.1 TLB Functions Configuration of the TLB The TLB caches address translation table information located in the external memory. The address translation table stores the physical page number translated from the virtual page number and the control information for the page, which is the unit of address translation. Figure 3.3 shows the overall TLB configuration. The TLB is 4-way set associative with 128 entries. There are 32 entries for each way. Figure 3.4 shows the configuration of virtual addresses and TLB entries. Ways 0 to 3 Ways 0 to 3 Entry 0 Entry 1 VPN(31-17) VPN(11-10) ASID(7-0) V Entry 0 Entry 1 PPN(31-10) PR(1-0) SZ C D SH Entry 31 Address array Entry 31 Data array Figure 3.3 Overall Configuration of the TLB Rev. 4.00, 03/04, page 59 of 660 31 VPN 10 9 Offset 0 Virtual address (1-kbyte page) 31 VPN Virtual address (4-kbyte page) (15) VPN (31-17) (2) VPN (11-10) (8) ASID (1) V (22) PPN (2) (1) (1) (1) (1) PR SZ C D SH 12 11 Offset 0 TLB entry Legend VPN: Virtual page number. Top 22 bits of virtual address for a 1-kbyte page, or top 20 bits of virtual address for a 4-kbyte page. Since VPN bits 16-12 are used as the index number, they are not stored in the TLB entry. ASID: Address space identifier. Indicates the process that can access a virtual page. In single virtual memory mode and user mode, or in multiple virtual memory mode, if the SH bit is 0, the address is compared with the ASID in PTEH when address comparison is performed. SH: Share status bit 0 = Page not shared between processes 1 = Page shared between processes SZ: Page-size bit 0 = 1-kbyte page 1 = 4-kbyte page V: Valid bit. Indicates whether entry is valid. 0 = Invalid 1 = Valid Cleared to 0 by a power-on reset. Not affected by a manual reset. PPN: Physical page number. Top 22 bits of physical address. PPN bits 11-10 are not used in case of a 4-kbyte page. Attention must be paid to the synonym problem in case of a 1kbyte page (see section 3.4.4 Avoiding Synonym Problems). PR: Set the most significant bit to 0. Protection key field. 2-bit field encoded to define the access rights to the page. 00: Reading only is possible in privileged mode. 01: Reading/writing is possible in privileged mode. 10: Reading only is possible in privileged/user mode. 11: Reading/writing is possible in privileged/user mode. C: Cacheable bit. Indicates whether the page is cacheable. 0: Non-cacheable 1: Cacheable D: Dirty bit. Indicates whether the page has been written to. 0 = Not written to 1 = Written to Figure 3.4 Virtual Address and TLB Structure Rev. 4.00, 03/04, page 60 of 660 3.3.2 TLB Indexing The TLB uses a 4-way set associative scheme, so entries must be selected by index. VPN bits 16 to 12 and ASID bits in PTEH 4 to 0 are used as the index number regardless of the page size. The index number can be generated in two different ways depending on the setting of the IX bit in MMUCR. 1. When IX = 0, VPN bits 16 to 12 alone are used as the index number 2. When IX = 1, VPN bits 16 to 12 are EX-ORed with ASID bits 4 to 0 to generate a 5-bit index number The second method is used to prevent lowered TLB efficiency that results when multiple processes run simultaneously in the same virtual address space (multiple virtual memory) and a specific entry is selected by indexing of each process. Figures 3.5 and 3.6 show the indexing schemes. Virtual address 31 PTEH register 31 VPN Exclusive-OR Index Ways 0 to 3 ASID(4 to 0) 17 16 12 11 0 10 0 7 ASID 0 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(3-0) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.5 TLB Indexing (IX = 1) Virtual address 31 17 16 12 11 0 Index Ways 0 to 3 0 VPN(31-17) VPN(11-10) ASID(7-0) V PPN(31-10) PR(1-0) SZ C D SH 31 Address array Data array Figure 3.6 TLB Indexing (IX = 0) Rev. 4.00, 03/04, page 61 of 660 3.3.3 TLB Address Comparison The results of address comparison determine whether a specific virtual page number is registered in the TLB. The virtual page number of the virtual address that accesses external memory is compared to the virtual page number of the indexed TLB entry. The ASID within the PTEH is compared to the ASID of the indexed TLB entry. All four ways are searched simultaneously. If the compared values match, and the indexed TLB entry is valid (V bit = 1), the hit is registered. It is necessary to have software ensure that TLB hits do not occur simultaneously in more than one way, as hardware operation is not guaranteed if this occurs. For example, if there are two identical TLB entries with the same VPN and a setting is made such that a TLB hit is made only by a process with ASID = H'FF when one is in the shared state (SH = 1) and the other in the non-shared state (SH = 0), then if the ASID in PTEH is set to H'FF, there is a possibility of simultaneous TLB hits in both these ways. It is therefore necessary to ensure that this kind of setting is not made by software. The object compared varies depending on the page management information (SZ, SH) in the TLB entry. It also varies depending on whether the system supports multiple virtual memory or single virtual memory. The page-size information determines whether VPN (11, 10) is compared. VPN (11, 10) is compared for 1-kbyte pages (SZ = 0) but not for 4-kbyte pages (SZ = 1). The sharing information (SH) determines whether the PTEH.ASID and the ASID in the TLB entry are compared. ASIDs are compared when there is no sharing between processes (SH = 0) but not when there is sharing (SH = 1). When single virtual memory is supported (MMUCR.SV = 1) and privileged mode is engaged (SR.MD = 1), all process resources can be accessed. This means that ASIDs are not compared when single virtual memory is supported and privileged mode is engaged. The objects of address comparison are shown in figure 3.7. Rev. 4.00, 03/04, page 62 of 660 SH = 1 or (SR.MD = 1 and MMUCR.SV = 1)? Yes No No (4 kbytes) SZ = 0? Yes (1 kbyte) SZ = 0? No (4 kbytes) Yes (1 kbyte) Bits compared: VPN (31 to 17) VPN (11 to 10) Bits compared: VPN (31 to 17) Bits compared: VPN (31 to 17) VPN (11 to 10) ASID (7 to 0) Bits compared: VPN (31 to 17) ASID (7 to 0) Figure 3.7 Objects of Address Comparison Rev. 4.00, 03/04, page 63 of 660 3.3.4 Page Management Information In addition to the SH and SZ bits, the page management information of TLB entries also includes D, C, and PR bits. The D bit of a TLB entry indicates whether the page is dirty (i.e., has been written to). If the D bit is 0, an attempt to write to the page results in an initial page write exception. For physical page swapping between secondary memory and main memory, for example, pages are controlled so that a dirty page is paged out of main memory only after that page is written back to secondary memory. To record that there has been a write to a given page in the address translation table in memory, an initial page write exception is used. The C bit in the entry indicates whether the referenced page resides in a cacheable or noncacheable area of memory. The PR field specifies the access rights for the page in privileged and user modes and is used to protect memory. Attempts at nonpermitted accesses result in TLB protection violation exceptions. Access states designated by the D, C, and PR bits are shown in table 3.1. Table 3.1 Access States Designated by D, C, and PR Bits Privileged Mode Reading D bit 0 1 C bit 0 1 PR bit 00 01 10 11 Permitted Permitted Permitted (no caching) Permitted (with caching) Permitted Permitted Permitted Permitted Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection violation exception Permitted TLB protection violation exception Permitted Reading Permitted Permitted Permitted (no caching) Permitted (with caching) User Mode Writing Initial page write exception Permitted Permitted (no caching) Permitted (with caching) TLB protection TLB protection violation exception violation exception TLB protection TLB protection violation exception violation exception Permitted Permitted TLB protection violation exception Permitted Rev. 4.00, 03/04, page 64 of 660 3.4 3.4.1 MMU Functions MMU Hardware Management There are two kinds of MMU hardware management as follows: 1. The MMU decodes the virtual address accessed by a process and performs address translation by controlling the TLB in accordance with the MMUCR settings. 2. In address translation, the MMU receives page management information from the TLB, and determines the MMU exception and whether the cache is to be accessed (using the C bit). For details of the determination method and the hardware processing, see section 3.5, MMU Exceptions. 3.4.2 MMU Software Management There are three kinds of MMU software management, as follows. 1. MMU register setting. MMUCR setting, in particular, should be performed in areas P1 and P2 for which address translation is not performed. Also, since SV and IX bit changes constitute address translation system changes, in this case, TLB flushing should be performed by simultaneously writing 1 to the TF bit also. Since MMU exceptions are not generated in the MMU disabled state with the AT bit cleared to 0, use in the disabled state must be avoided with software that does not use the MMU. 2. TLB entry recording, deletion, and reading. TLB entry recording can be done in two ways by using the LDTLB instruction, or by writing directly to the memory-mapped TLB. For TLB entry deletion and reading, the memory allocation TLB can be accessed. See section 3.4.3, MMU Instruction (LDTLB), for details of the LDTLB instruction, and section 3.6, Configuration of the Memory-Mapped TLB, for details of the memory-mapped TLB. 3. MMU exception processing. When an MMU exception is generated, it is handled on the basis of information set from the hardware side. See section 3.5, MMU Exceptions, for details. When single virtual memory mode is used, it is possible to create a state in which physical memory access is enabled in the privileged mode only by clearing the share status bit (SH) to 0 to specify recording of all TLB entries. This strengthens inter-process memory protection, and enables special access levels to be created in the privileged mode only. Recording a 1-kbyte page TLB entry may result in a synonym problem. See section 3.4.4, Avoiding Synonym Problems. Rev. 4.00, 03/04, page 65 of 660 3.4.3 MMU Instruction (LDTLB) The load TLB instruction (LDTLB) is used to record TLB entries. When the IX bit in MMUCR is 0, the LDTLB instruction changes the TLB entry in the way specified by the RC bit in MMUCR to the value specified by PTEH and PTEL, using VPN bits 16 to 12 specified in PTEH as the index number. When the IX bit in MMUCR is 1, the EX-OR of VPN bits 16 to 12 specified in PTEH and ASID bits 4 to 0 in PTEH are used as the index number. Figure 3.8 shows the case where the IX bit in MMUCR is 0. When an MMU exception occurs, the virtual page number of the virtual address that caused the exception is set in PTEH by hardware. The way is set in the RC bit of MMUCR for each exception according to the rules described in section 3.2.5 MMU Control Register (MMUCR). Consequently, if the LDTLB instruction is issued after setting only PTEL in the MMU exception processing routine, TLB entry recording is possible. Any TLB entry can be updated by software rewriting of PTEH and the RC bits in MMUCR. As the LDTLB instruction changes address translation information, there is a risk of destroying address translation information if this instruction is issued in the P0, U0, or P3 area. Make sure, therefore, that this instruction is issued in the P1 or P2 area. Also, an instruction associated with an access to the P0, U0, or P3 area (such as the RTE instruction) should be issued at least two instructions after the LDTLB instruction. MMUCR 31 0 Index PTEH register 31 VPN 9 0 SV 0 0 RC 0 TF IX AT Way selection PTEL register 31 10 PPN 17 12 10 VPN Write 0 8 ASID 0 0 0 V 0 PR SZ C D SH 0 Write Ways 0 to 3 0 VPN(31 to17) VPN(11 to 10) ASID(7 to 0) V PPN(31 to 10) PR(1 to 0) SZ C D SH 31 Address array Data array Figure 3.8 Operation of LDTLB Instruction Rev. 4.00, 03/04, page 66 of 660 3.4.4 Avoiding Synonym Problems When a 1-kbyte page is recorded in a TLB entry, a synonym problem may arise. If a number of virtual addresses are mapped onto a single physical address, the same physical address data will be recorded in a number of cache entries, and it will not be possible to guarantee data congruity. The reason why this problem only occurs when using a 1-kbyte page is explained below with reference to figure 3.9. To achieve high-speed operation of the SH7706 cache, an index number is created using virtual address bits 11 to 4. When a 4-kbyte page is used, virtual address bits 11 to 4 are included in the offset, and since they are not subject to address translation, they are the same as physical address bits 11 to 4. In cache-based address comparison and recording in the address array, since the cache tag address is a physical address, physical address bits 31 to 10 are recorded. When a 1-kbyte page is used, also, a cache index number is created using virtual address bits 11 to 4. However, in case of a 1-kbyte page, virtual address bits (11, 10) are subject to address translation and therefore may not be the same as physical address bits 11 and 10. Consequently, the physical address is recorded in a different entry from that of the index number indicated by the physical address in the cache address array. For example, assume that, with 1-kbyte page TLB entries, TLB entries for which the following translation has been performed are recorded in two TLBs: Virtual address 1 H'00000000 physical address H'00000C00 Virtual address 2 H'00000C00 physical address H'00000C00 Virtual address 1 is recorded in cache entry H'00, and virtual address 2 in cache entry H'C0. Since two virtual addresses are recorded in different cache entries despite the fact that the physical addresses are the same, memory inconsistency will occur as soon as a write is performed to either virtual address. Therefore, when recording a 1-kbyte TLB entry, if the physical address is the same as a physical address already used in another TLB entry, it should be recorded in such a way that physical address bits (11, 10) are the same. Rev. 4.00, 03/04, page 67 of 660 When using a 4-kbyte page Virtual address 31 VPN 12 11 10 Offset 0 Physical address 31 PPN 12 11 10 Virtual address (11 to 4) 0 Offset Cache address array Physical address (31 to 10) When using a 1-kbyte page Virtual address 31 VPN 11 10 9 Offset 0 Virtual address (11 to 4) Physical address 31 PPN 11 10 9 Offset 0 Cache address array Physical address (31 to 10) Figure 3.9 Synonym Problem Rev. 4.00, 03/04, page 68 of 660 3.5 MMU Exceptions There are four MMU exceptions: TLB miss, TLB protection violation, TLB invalid, and initial page write. 3.5.1 TLB Miss Exception A TLB miss results when the virtual address and the address array of the selected TLB entry are compared and no match is found. TLB miss exception processing includes both hardware and software operations. Hardware Operations: In a TLB miss, this LSI's hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the save program counter (SPC). If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of the status register (SR) at the time of the exception are written to the save status register (SSR). 6. The mode (MD) bit in SR is set to 1, and switched to the privileged mode. 7. The block (BL) bit in SR is set to 1 to mask any further exception requests. 8. The register bank (RB) bit in SR is set to 1. 9. The RC field in the MMUCR is incremented by 1 when all entries indexed are valid. When some entries indexed are invalid, the smallest way number of them is set in RC. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000400 to invoke the user-written TLB miss exception handler. Rev. 4.00, 03/04, page 69 of 660 Software (TLB Miss Handler) Operations: The software searches the page tables in external memory and allocates the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the value of the physical page number (PPN) field and the protection key (PR), page size (SZ), cacheable (C), dirty (D), share status (SH), and valid (V) bits of the page table entry recorded in the address translation table in the external memory into the PTEL register in this LSI. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the return from exception handler (RTE) instruction to terminate the handler routine and return to the instruction stream. 3.5.2 TLB Protection Violation Exception A TLB protection violation exception results when the virtual address and the address array of the selected TLB entry are compared and a valid entry is found to match, but the type of access is not permitted by the access rights specified in the PR field. TLB protection violation exception processing includes both hardware and software operations. Hardware Operations: In a TLB protection violation exception, this LSI's hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Either exception code H'0A0 for a load access, or H'0C0 for a store access, is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written into SPC (if the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written into SPC). 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1, and switched to the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The RB bit in SR is set to 1. 9. The way that generated the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the TLB protection violation exception handler. Rev. 4.00, 03/04, page 70 of 660 Software (TLB Protection Violation Handler) Operations: Software resolves the TLB protection violation and issues the RTE (return from exception handler) instruction to terminate the handler and return to the instruction stream. Note that the RTE instruction should be issued after the two instructions following the LDTLB instruction. 3.5.3 TLB Invalid Exception A TLB invalid exception results when the virtual address is compared to a selected TLB entry address array and a match is found but the entry is not valid (the V bit is 0). TLB invalid exception processing includes both hardware and software operations. Hardware Operations: In a TLB invalid exception, this LSI's hardware executes a set of prescribed operations, as follows: 1. The VPN number of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. The way number causing the exception is written to RC in MMUCR. 4. Either exception code H'040 for a load access, or H'060 for a store access, is written to the EXPEVT register. 5. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the delayed branch instruction is written to the SPC. 6. The contents of SR at the time of the exception are written into SSR. 7. The MD bit in SR is set to 1, and switched to the privileged mode. 8. The BL bit in SR is set to 1 to mask any further exception requests. 9. The RB bit in SR is set to 1. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100, and the TLB protection violation exception handler starts. Software (TLB Invalid Exception Handler) Operations: The software searches the page tables in external memory and assigns the required page table entry. Upon retrieving the required page table entry, software must execute the following operations: 1. Write the values of the PPN, PR, SZ, C, D, SH, and V of the page table entry recorded in the external memory to the PTEL register. 2. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 3. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 4. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Rev. 4.00, 03/04, page 71 of 660 3.5.4 Initial Page Write Exception An initial page write exception results in a write access when the virtual address and the address array of the selected TLB entry are compared and a valid entry with the appropriate access rights is found to match, but the D (dirty) bit of the entry is 0 (the page has not been written to). Initial page write exception processing includes both hardware and software operations. Hardware Operations: In an initial page write exception, this LSI's hardware executes a set of prescribed operations, as follows: 1. The VPN field of the virtual address causing the exception is written to the PTEH register. 2. The virtual address causing the exception is written to the TEA register. 3. Exception code H'080 is written to the EXPEVT register. 4. The PC value indicating the address of the instruction in which the exception occurred is written to the SPC. If the exception occurred in a delay slot, the PC value indicating the address of the related delayed branch instruction is written to the SPC. 5. The contents of SR at the time of the exception are written to SSR. 6. The MD bit in SR is set to 1, and switched to the privileged mode. 7. The BL bit in SR is set to 1 to mask any further exception requests. 8. The RB bit in SR is set to 1. 9. The way that caused the exception is set in the RC field in MMUCR. 10. Execution branches to the address obtained by adding the value of the VBR contents and H'00000100 to invoke the user-written initial page write exception handler. Software (Initial Page Write Handler) Operations: The software must execute the following operations: 1. Retrieve the required page table entry from external memory. 2. Set the D bit of the page table entry in the external memory to 1. 3. Write the value of the PPN field and the PR, SZ, C, D, SH, and V bits of the page table entry in the external memory to the PTEL register. 4. If using software for way selection for entry replacement, write the desired value to the RC field in MMUCR. 5. Issue the LDTLB instruction to load the contents of PTEH and PTEL into the TLB. 6. Issue the RTE instruction to terminate the handler and return to the instruction stream. The RTE instruction should be issued after two LDTLB instructions. Figure 3.10 shows the flowchart for MMU exceptions. Rev. 4.00, 03/04, page 72 of 660 Start No SH = 0 and (MMUCR.SV = 0 or SR.MD = 0)? Yes No VPNs match? No Yes VPNs and ASIDs match? Yes No V = 1? TLB miss exception TLB invalid exception Yes User mode User or privileged? Privileged mode PR check 00/01 W R/W? R R/W? R No D = 1? 10 11 W W R/W? R 01/11 PR check 00/10 W R/W? R Yes TLB protection violation exception No (noncacheable) Yes (cacheable) TLB protection violation Initial page write exception C = 1? Memory access Cache access Figure 3.10 MMU Exception Generation Flowchart Rev. 4.00, 03/04, page 73 of 660 3.5.5 Processing Flow in Event of MMU Exception (Same Processing Flow for CPU Address Error) Figure 3.11 shows the MMU exception signals in the instruction fetch mode. IF ID EX ID MA EX ID WB MA EX WB MA NOP NOP WB Handler transition processing MMU exception handler IF ID EX MA WB : Exception source stage IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation Figure 3.11 MMU Exception Signals in Instruction Fetch Rev. 4.00, 03/04, page 74 of 660 Figure 3.12 shows the MMU exception signals in the data access mode. IF ID IF EX ID IF MA EX ID WB MA EX ID WB MA EX ID WB MA EX ID WB MA EX WB MA NOP NOP MMU exception handler IF ID EX MA WB WB Handler transition processing : Exception source stage : Stage cancellation for instruction that has begun execution IF ID EX MA WB NOP = Instruction fetch = Instruction decode = Instruction execution = Memory access = Write back = No operation Figure 3.12 MMU Exception Signals in Data Access Rev. 4.00, 03/04, page 75 of 660 3.6 Configuration of the Memory-Mapped TLB In order for TLB operations to be managed by software, TLB contents can be read or written to in the privileged mode using the MOV instruction. The TLB is assigned to the P4 area in the virtual address space. The TLB address array (VPN, V bit, and ASID) is assigned to H'F2000000 to H'F2FFFFFF, and the data array (PPN, PR, SZ, C, D, and SH bits) to H'F3000000 to H'F3FFFFFF. The V bit in the address array can also be accessed from the data array. Only longword access is possible for both the address array and the data array. 3.6.1 Address Array The address array is assigned to H'F2000000 to H'F2FFFFFF. To access an address array, the 32-bit address field (for read/write operations) and 32-bit data field (for write operations) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the VPN, V bit and ASID to be written to the address array (figure 3.13 (1)). In the address field, specify the entry address for selecting the entry (bits 16 to 12), W for selecting the way (bits 9, 8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3) and H'F2 to indicate address array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR is taken of the entry address and ASID. When writing, the write is performed to the entry selected with the index address and way. When reading, the VPN, V bit, and ASID of the entry selected with the index address and way in the format of the data field in figure 3.13 without comparing addresses. 0 is written to data field bits 16 to 12. To invalidate a specific entry, specify the entry and way, and write 0 to the corresponding V bit. 3.6.2 Data Array The data array is assigned to H'F3000000 to H'F3FFFFFF. To access a data array, the 32-bit address field (for read/write operations), and 32-bit data field (for write operations) must be specified. These are specified in the general register. The address section specifies information for selecting the entry to be accessed; the data section specifies the longword data to be written to the data array (figure 3.13 (2)). In the address section, specify the entry address for selecting the entry (bits 16 to 12), W for selecting the way (bits 9, 8: 00 is way 0, 01 is way 1, 10 is way 2, 11 is way 3), and H'F3 to indicate data array access (bits 31 to 24). The IX bit in MMUCR indicates whether an EX-OR is taken of the entry address and ASID. Both reading and writing use the longword of the data array specified by the entry address and way number. The access size of the data array is fixed at longword. Rev. 4.00, 03/04, page 76 of 660 (1) TLB Address Array Access Read access 31 Address field 31 Data field VPN 11110010 24 23 * 17 16 * 17 16 0 12 11 10 9 8 7 VPN **W 6 0 * 0 ASID 0* 12 11 10 9 8 7 0 VPN 0 V Write access 31 Address field 31 Data field VPN 11110010 24 23 * 17 16 * 17 16 * 12 11 10 9 8 7 VPN ** W 6 0 * 0 ASID 0* 12 11 10 9 8 7 * VPN * V Legend VPN: Virtual page number ASID: Address space identifier V: Valid bit * : Don't care W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) (2) TLB Data Array Access Read/write access 31 Address field 31 Data field 11110011 29 28 PPN 24 23 * 17 16 * 12 11 10 9 8 7 VPN ** W * 3 2 1 0 * 0 10 9 8 7 6 5 4 000 X V X PR SZ C D SH X Legend PPN: Physical page number V: Valid bit PR: Protection key field SZ: Page-size bit C: Cacheable bit D: Dirty bit SH: Share status bit * : Don't care VPN: Virtual page number X: 0 for read, don't care bit for write W: Way (00: Way 0, 01: Way 1, 10: Way 2, 11: Way 3) Figure 3.13 Specifying Address and Data for Memory-Mapped TLB Access Rev. 4.00, 03/04, page 77 of 660 3.6.3 Usage Examples Invalidating Specific Entries: Specific TLB entries can be invalidated by writing 0 to the entry's V bit. R0 specifies the write data and R1 specifies the address. ; R0=H'1547 381C ; MMUCR.IX=0 ; VPN(31-17)=B'000 1010 1010 0011 VPN(11-10)=B'10 ASID=B'0001 1100 R1=H'F201 3000 ; corresponding entry association is made from the entry selected by ; the VPN(16-12)=B'1 0011 index, the V bit of the hit way is cleared to ; 0,achieving invalidation. MOV.L R0,@R1 Reading the Data of a Specific Entry: This example reads the data section of a specific TLB entry. The bit order indicated in the data field in figure 3.14 (2) is read. R0 specifies the address and the data section of a selected entry is read to R1. ; R0=H'F300 4300 ; MOV.L @R0,R1 VPN(16-12)=B'0 0100 Way 3 3.7 3.7.1 Usage Note Use of Instructions Manipulating MD and BL Bits in SR Instructions that manipulate the MD or BL bit in register SR (the LDC Rm, SR instruction, LDC @Rm+, SR instruction, and RTE instruction) and the following instruction, or the LDTLB instruction, should be used with the TLB disabled or in a fixed physical address space (the P1 or P2 space). Rev. 4.00, 03/04, page 78 of 660 3.7.2 Use of TLB An erroneous value is set in the RC bit in MMUCR when all of the following conditions are satisfied. 1. MMU is on (AT bit in MMUCR is 1) 2. Same VPN exists in more than one ways in a single entry in a TLB address array 3. TLB exception is generated VPN is not initialized by a power-on reset or a manual reset. Therefore, two or more VPNs have the same values in a single entry. When an entry in this state is registered to way 3, for example, the state of that entry in the TLB address array becomes as shown below. As a result, the same VPN exists in both way 0 and way 3, and condition 2 above is satisfied. After reset WAY VPN 0 12345 3 12345 After registered to way 3 WAY VPN V 0 12345 0 3 12345 1 V 0 0 A condition may also be satisfied when the TLB is handled by software. For example, if an entry in the TLB address array is registered to way 3 after way 0 is disabled (V bit is changed from 1 to 0), the state of that entry becomes as shown below. Similar to the above case, the same VPN exists in both way 0 and way 3, and condition 2 above is satisfied. After way 0 is disabled WAY VPN V 0 12345 0 3 11111 0 After registered to way 3 WAY VPN V 0 12345 0 3 12345 1 To avoid this failure, take the following two countermeasures. 1. After a reset, initialize the upper four bits in VPN to 1 for all entries in the TLB address array until the AT bit in MMUCR is set to 1. 2. When disabling a way in the TLB address array, in addition to clearing the V bit to 0, initialize the upper four bits in VPN to 1. These countermeasures will prevent VPN from being a target of address translation. Accordingly, condition 3 is not satisfied, and this failure can be avoided. Rev. 4.00, 03/04, page 79 of 660 Rev. 4.00, 03/04, page 80 of 660 Section 4 Exception Processing 4.1 Exception Processing Function Exception processing is separate from normal program processing, and is performed by a routine separate from the normal program. In response to an exception processing request due to abnormal termination of the executing instruction, control is passed to a user-written exception handler. However, in response to an interrupt request, normal program execution continues until the end of the executing instruction. Here, all exceptions other than resets and interrupts will be called general exceptions. There are thus three types of exceptions: resets, general exceptions, and interrupts. 4.1.1 Exception Processing Flow In exception processing, the contents of the program counter (PC) and status register (SR) are saved in the saved program counter (SPC) and saved status register (SSR), respectively, and execution of the exception handler is invoked from a vector address. The return from exception handler (RTE) instruction is issued by the exception handler routine at the completion of the routine, restoring the contents of the PC and SR to return to the processor state at the point of interruption and the address where the exception occurred. A basic exception processing sequence consists of the following operations: 1. The contents of the PC and SR are saved in the SPC and SSR, respectively. 2. The block (BL) bit in SR is set to 1, masking any subsequent exceptions. 3. The mode (MD) bit in SR is set to 1 to place the SH7706 in the privileged mode. 4. The register bank (RB) bit in SR is set to 1. 5. An exception code identifying the exception event is written to bits 11 to 0 of the exception event (EXPEVT) or interrupt event (INTEVT and INTEVT2) register. 6. Instruction execution jumps to the designated exception processing vector address to invoke the handler routine. Rev. 4.00, 03/04, page 81 of 660 4.1.2 Exception Processing Vector Addresses The reset vector address is fixed at H'A0000000. The other three events are assigned offsets from the vector base address by software. Translation look-aside buffer (TLB) miss exceptions have an offset from the vector base address of H'00000400. The vector address offset for general exception events other than TLB miss exceptions is H'00000100. The interrupt vector address offset is H'00000600. The vector base address is loaded into the vector base register (VBR) by software. The vector base address should reside in P1 or P2 fixed physical address space. Figure 4.1 shows the relationship between the vector base address, the vector offset, and the vector table. VBR (Vector base address) + Vector offset H'A000 0000 Vector address Figure 4.1 Vector Addresses In table 4.1, exceptions and their vector addresses are listed by exception type, instruction completion state, relative acceptance priority, relative order of occurrence within an instruction execution sequence and vector address for exceptions and their vector addresses. Table 4.1 Exception Type Reset Exception Event Vectors Current Instruction Aborted Exception Event Power-on Manual reset H-UDI reset Priority*1 1 1 1 2 2 Exception Order -- -- -- 1 2 3 Vector Address H'A00000000 H'A00000000 H'A00000000 -- -- -- Vector Offset -- -- -- H'00000100 H'00000400 H'00000100 General exception events Aborted and retried CPU Address error (instruction access) TLB miss (instruction access) TLB invalid (instruction 2 access) Rev. 4.00, 03/04, page 82 of 660 Exception Type General exception events Current Instruction Aborted and retried Exception Event TLB protection violation (instruction access) Exception Priority*1 Order 2 4 5 5 6 7 Vector Address -- -- -- -- -- Vector Offset H'00000100 H'00000100 H'00000100 H'00000100 H'00000400 General illegal instruction 2 exception Illegal slot instruction exception CPU Address error (data access) TLB miss (data access not in repeat loop) 2 2 2 TLB invalid (data access) 2 TLB protection violation (data access) Initial page write Completed Unconditional trap (TRAPA instruction) User breakpoint trap DMA address error General interrupt requests Completed Nonmaskable interrupt External hardware interrupt H-UDI interrupt 2 2 2 2 2 3 4* 3 8 9 10 5 n*2 12 -- -- -- -- -- -- -- -- -- -- -- -- H'00000100 H'00000100 H'00000100 H'00000100 H'00000100 H'00000100 H'00000600 H'00000600 H'00000600 4*3 Notes: 1. Priorities are indicated from high to low, 1 being highest and 4 being lowest. 2. The user defines the break point traps. 1 is a break point before instruction execution and 11 is a break point after instruction execution. For an operand break point, use 11. 3. Use software to specify relative priorities of external hardware interrupts and peripheral module interrupts (see section 6, Interrupt Controller (INTC)). 4.1.3 Acceptance of Exceptions Processor resets and interrupts are asynchronous events unrelated to the instruction stream. All exception events are prioritized to establish an acceptance order whenever two or more exception events occur simultaneously. If a power-on reset and manual reset occur simultaneously, the power-on reset takes precedence. Rev. 4.00, 03/04, page 83 of 660 All general exception events occur in a relative order in the execution sequence of an instruction (i.e. execution order), but are handled at priority level 2 in instruction-stream order (i.e. program order), where an exception detected in a preceding instruction is accepted prior to an exception detected in a subsequent instruction. Three general exception events (reserved instruction code exception, unconditional trap, and illegal slot instruction exception) are detected in the decode stage (ID stage) of different instructions and are mutually exclusive events in the instruction pipeline. They have the same execution priority. Figure 4.2 shows the order of general exception acceptance. Pipeline Sequence: Instruction n IF ID EX MA WB TLB miss (data access) Instruction n + 1 IF ID EX MA WB TLB miss (instruction access) Instruction n + 2 Detection Order: TLB miss (instruction n+1) IF ID EX MA WB RIE (reserved instruction exception) TLB miss (instruction n) and RIE (instruction n + 2) = simultaneous detection Handling Order: TLB miss (instruction n) 1 Re-execution of instruction n Program Order: TLB miss (instruction n + 1) 2 Re-execution of instruction n + 1 RIE (instruction n + 2) Legend IF = Instruction fetch ID = Instruction decode EX = Instruction execution MA = Memory access WB = Write back 3 Figure 4.2 Example of Acceptance Order of General Exceptions Rev. 4.00, 03/04, page 84 of 660 All exceptions other than a reset are detected in the pipeline ID stage, and accepted on instruction boundaries. However, an exception is not accepted between a delayed branch instruction and the delay slot. A re-execution type exception detected in a delay slot is accepted before execution of the delayed branch instruction. A completion type exception detected in a delayed branch instruction or delay slot is accepted after execution of the delayed branch instruction. The delay slot here refers to the next instruction after a delayed unconditional branch instruction, or the next instruction when a delayed conditional branch instruction is true. 4.1.4 Exception Codes Table 4.2 lists the exception codes written to bits 11 to 0 of the EXPEVT register for reset or general exceptions or the INTEVT and INTEVT2 registers for general interrupt requests to identify each specific exception event. An additional exception register, the TRAPA (TRA) register, is used to hold the 8-bit immediate data in an unconditional trap (TRAPA instruction). Table 4.2 Exception Codes Exception Event Power-on reset Manual reset H-UDI reset General exception events TLB miss/invalid exception (load) TLB miss/invalid exception (store) Initial page write exception TLB protection exception (load) TLB protection exception (store) CPU Address error (load) CPU Address error (store) Unconditional trap (TRAPA instruction) Reserved instruction code exception Illegal slot instruction exception User breakpoint trap DMA address error Exception Code H'000 H'020 H'000 H'040 H'060 H'080 H'0A0 H'0C0 H'0E0 H'100 H'160 H'180 H'1A0 H'1E0 H'5C0 Exception Type Reset Rev. 4.00, 03/04, page 85 of 660 Exception Type General interrupt requests Exception Event Nonmaskable interrupt H-UDI interrupt External hardware interrupts: IRL3-IRL0 = 0000 IRL3-IRL0 = 0001 IRL3-IRL0 = 0010 IRL3-IRL0 = 0011 IRL3-IRL0 = 0100 IRL3-IRL0 = 0101 IRL3-IRL0 = 0110 IRL3-IRL0 = 0111 IRL3-IRL0 = 1000 IRL3-IRL0 = 1001 IRL3-IRL0 = 1010 IRL3-IRL0 = 1011 IRL3-IRL0 = 1100 IRL3-IRL0 = 1101 IRL3-IRL0 = 1110 Exception Code H'1C0 H'5E0 H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Note: Exception codes H'120, H'140, and H'3E0 are reserved. 4.1.5 Exception Request and BL Bit If a general exception event occurs when the BL bit in SR is 1, the CPU's internal registers are set to their post-reset state, other module registers retain their contents prior to the general exception, and a branch is made to the same address (H'A0000000) as for a reset. If a general interrupt occurs when BL = 1, the request is masked (held pending) and not accepted until the BL bit is cleared to 0 by software. For reentrant exception processing, the SPC and SSR must be saved and the BL bit in SR cleared to 0. 4.1.6 Returning from Exception Processing The RTE instruction is used to return from exception processing. When RTE is executed, the SPC value is set in the PC, and the SSR value in SR, and the return from exception processing is performed by branching to the SPC address. If the SPC and SSR have been saved in the external memory, set the BL bit in SR to 1, then restore the SPC and SSR, and issue an RTE instruction. Rev. 4.00, 03/04, page 86 of 660 4.2 Register Description There are four registers related to exception processing. These are peripheral module registers, and therefore reside in area P4. They can be accessed by specifying the address in the privileged mode only. There are following four registers related to exception processing. Registers with undefined initial values (TRAPA exception register, Interrupt event register, and Interrupt event register 2) should be initialized by software. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Exception event register (EXPEVT) * Interrupt event register (INTEVT) * Interrupt event register 2 (INTEVT2) * TRAPA exception register (TRA) 4.2.1 Exception Event Register (EXPEVT) The exception event register (EXPEVT) contains a 12-bit exception code. The exception code set in EXPEVT is that for a reset or general exception event. The exception code is set automatically by hardware when an exception occurs. EXPEVT can also be modified by software. Bit 31 to 12 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 * R/W 12-bit exception code Note:* H'0000 is set in a power-on reset, and H'020 in a manual reset. 4.2.2 Interrupt Event Register (INTEVT) The interrupt event register (INTEVT) contains a 12-bit interrupt exception code or a code indicating the interrupt priority. Which is set when an interrupt occurs depends on the interrupt source (refer to section 6, Interrupt Controller (INTC)). The exception code or interrupt priority code is set automatically by hardware when an exception occurs. INTEVT can also be modified by software. Rev. 4.00, 03/04, page 87 of 660 Bit 31 to 12 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 R/W 12-bit interrupt exception code or a code indicating the interrupt priority 4.2.3 Interrupt Event Register 2 (INTEVT2) The interrupt event register 2 (INTEVT2) contains a 12-bit exception code. The exception code set in INTEVT2 is that for an interrupt request. The exception code is set automatically by hardware when an exception occurs. Bit 31 to 12 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 R/W 12-bit exception code 4.2.4 TRAPA Exception Register (TRA) The TRAPA exception register (TRA) contains 8-bit immediate data (imm) for the TRAPA instruction. TRA is set automatically by hardware when a TRAPA instruction is executed. TRA can also be modified by software. Bit 31 to 10 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 8-bit immediate data Reserved These bits are always read as 0. The write value should always be 0. 9 to 2 1, 0 imm All 0 R/W R Rev. 4.00, 03/04, page 88 of 660 4.3 4.3.1 Operation Reset The reset sequence is used to power up or restart the SH7706 from the initialization state. The RESETP signal and RESETM signal are sampled every clock cycle, and in the case of a power-on reset, all processing being executed (excluding the RTC) is suspended, all unfinished events are canceled, and reset processing is executed immediately. In the case of a manual reset, however, reset processing is executed after memory access in progress is completed. The reset sequence consists of the following operations: 1. The MD bit in SR is set to 1 to place the SH7706 in privileged mode. 2. The BL bit in SR is set to 1, masking any subsequent exceptions. 3. The RB bit in SR is set to 1. 4. An encoded value of H'000 in a power-on reset or H'020 in a manual reset is written to bits 11 to 0 of the EXPEVT register to identify the exception event. 5. Instruction execution jumps to the user-written exception handler at address H'A0000000. 4.3.2 Interrupts An interrupt processing request is accepted on completion of the current instruction. The interrupt acceptance sequence consists of the following operations: 1. The contents of the PC and SR are saved in SPC and SSR, respectively. 2. The BL bit in SR is set to 1, masking any subsequent exceptions. 3. The MD bit in SR is set to 1 to place the SH7706 in privileged mode. 4. The RB bit in SR is set to 1. 5. An encoded value identifying the exception event is written to bits 11 to 0 of the INTEVT and INTEVT2 registers. 6. Instruction execution jumps to the vector location designated by the sum of the value of the contents of the VBR and H'00000600 to invoke the exception handler. Rev. 4.00, 03/04, page 89 of 660 4.3.3 General Exceptions When the SH7706 encounters any exception condition other than a reset or interrupt request, it executes the following operations: 1. The contents of the PC and SR are saved in the SPC and SSR, respectively. 2. The BL bit in SR is set to 1, masking any subsequent exceptions. 3. The MD bit in SR is set to 1 to place the SH7706 in privileged mode. 4. The RB bit in SR is set to 1. 5. An encoded value identifying the exception event is written to bits 11 to 0 of the EXPEVT register. 6. Instruction execution jumps to the vector location designated by either the sum of the vector base address and offset H'00000400 in the vector table in a TLB miss trap, or by the sum of the vector base address and offset H'00000100 for exceptions other than TLB miss traps, to invoke the exception handler. 4.4 Individual Exception Operations This section describes the conditions for specific exception processing, and the processor operations. 4.4.1 Resets * Power-On Reset Conditions: RESETP low Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting modules are initialized. For details, refer to section 23, List of Registers. A power-on reset must always be performed when powering on. A high level is output from the STATUS0 and STATUS1 pins. * Manual Reset Conditions: RESETM low Operations: EXPEVT set to H'020, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB, and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting modules are initialized. For details, refer to section 23, List of Registers. A high level is output from the STATUS0 and STATUS1 pins. Rev. 4.00, 03/04, page 90 of 660 * H-UDI Reset Conditions: H-UDI reset command input (see section 21, User Debugging Interface (HUDI)) Operations: EXPEVT set to H'000, VBR and SR initialized, branch to PC = H'A0000000. Initialization sets the VBR register to H'0000000. In SR, the MD, RB and BL bits are set to 1 and the interrupt mask bits (I3 to I0) are set to B'1111. The CPU and on-chip supporting modules are initialized. For details, refer to section 23, List of Registers. Table 4.3 Types of Reset Conditions for Transition to Reset State RESETP = Low RESETM = Low H-UDI reset command input Internal State CPU Initialized Initialized Initialized On-Chip Supporting Modules (See register configuration in relevant sections) Type Power-on reset Manual reset H-UDI reset 4.4.2 General Exceptions * TLB miss exception Conditions: Comparison of TLB addresses shows no address match Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The RC bit in MMUCR is incremented by one when all ways are valid, or way-0 is set to the RC with top priority when there is invalid way. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0400. To speed up TLB miss processing, the offset differs from other exceptions. * TLB invalid exception Conditions: Comparison of TLB addresses shows address match but V = 0. Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. The PC and SR of the instruction that generated the exception are saved in the SPC and SSR, respectively. If the exception occurred during a read, H'040 is set in EXPEVT; if the exception occurred during a write, H'060 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. Rev. 4.00, 03/04, page 91 of 660 * Initial page write exception Conditions: A hit occurred to the TLB for a store access, but D = 0. (This occurs for initial writes to the page registered by the load.) Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bit in MMUCR. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. H'080 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs in PC = VBR + H'0100. * TLB protection exception Conditions: When a hit access violates the TLB protection information (PR bits) shown below: PR 00 01 10 11 Privileged mode Only read enabled Read/write enabled Only read enabled Read/write enabled User mode No access No access Only read enabled Read/write enabled Operations: The virtual address (32 bits) that caused the exception is set in TEA and the corresponding virtual page number (22 bits) is set in PTEH (31 to 10). The ASID of PTEH indicates the ASID at the time the exception occurred. The way that generated the exception is set in the RC bits in MMUCR. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'0A0 is set in EXPEVT; if the exception occurred during a write, H'0C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * Address error Conditions: When corresponded to the following items. A. Instruction fetch from odd address (4n + 1, 4n + 3) B. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) C. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) D. Virtual space accessed in user mode in the area H'80000000 to H'FFFFFFFF. Rev. 4.00, 03/04, page 92 of 660 Operations: The virtual address (32 bits) that caused the exception is set in TEA. The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. If the exception occurred during a read, H'0E0 is set in EXPEVT; if the exception occurred during a write, H'100 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. Refer to section 3.5.5, Processing Flow in Event of MMU Exception (Same Processing Flow for CPU Address Error). * Unconditional trap Conditions: TRAPA instruction executed Operations: The exception is a processing-completion type, so the PC of the instruction after the TRAPA instruction is saved to the SPC. SR from the time when the TRAPA instruction was executing is saved to SSR. The 8-bit immediate value in the TRAPA instruction is quadrupled and set in TRA (9 to 0). H'160 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. * General illegal instruction exception Conditions: When corresponded to the following items. A. When undefined code not in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'Fxxx.(In the case of SR.CL = 1, the value should be B'111111xxxxxxxxxx.) B. When a privileged instruction not in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. Operations: The PC and SR of the instruction that generated the exception are saved to the SPC and SSR, respectively. H'180 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed. * Illegal slot instruction exception Conditions: When corresponded to the following items. A. When undefined code in a delay slot is decoded Delay branch instructions: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT/S, BF/S Undefined instruction: H'Fxxx. (In the case of SR.CL = 1, the value should be B'111111xxxxxxxxxx.) B. When an instruction that rewrites the PC in a delay slot is decoded Instructions that rewrite the PC: JMP, JSR, BRA, BRAF, BSR, BSRF, RTS, RTE, BT, BF, BT/S, BF/S, TRAPA, LDC Rm, SR, LDC.L @Rm+, SR C. When a privileged instruction in a delay slot is decoded in user mode Privileged instructions: LDC, STC, RTE, LDTLB, SLEEP; instructions that access GBR with LDC/STC are not privileged instructions. Rev. 4.00, 03/04, page 93 of 660 Operations: The PC of the previous delay branch instruction is saved to the SPC. SR of the instruction that generated the exception is saved to SSR. H'1A0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. When an undefined instruction other than H'Fxxx is decoded, operation cannot be guaranteed. * User break point trap Conditions: When a break condition set in the user break point controller is satisfied Operations: When a post-execution break occurs, the PC of the instruction immediately after the instruction that set the break point is set in the SPC. If a pre-execution break occurs, the PC of the instruction that set the break point is set in the SPC. SR when the break occurs is set in SSR. H'1E0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. See section 7, User Break Controller, for more information. * DMA Address error Conditions: When corresponded to the following items. A. Word data accessed from addresses other than word boundaries (4n + 1, 4n + 3) B. Longword accessed from addresses other than longword boundaries (4n + 1, 4n + 2, 4n + 3) Operations: The PC of the instruction immediately after the instruction executed before the exception occurs is saved to the SPC. SR when the exception occurs is saved to SSR. H'5C0 is set in EXPEVT. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to PC = VBR + H'0100. 4.4.3 * NMI Conditions: NMI pin edge detection Operations: The PC and SR after the instruction that receives the interrupt are saved to the SPC and SSR, respectively. H'01C0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to PC = VBR + H'0600. This interrupt is not masked by SR.IMASK and received with top priority when the SR's BL bit in SR is 0. When the BL bit is 1, the interrupt is masked. When BLMSK in ICRI is a logic zero and not masked when BLMSK in ICRI is a logic one. See section 6, Interrupt Controller (INTC), for more information. Interrupts Rev. 4.00, 03/04, page 94 of 660 * IRL Interrupts Conditions: The value of the interrupt mask bits in SR is lower than the IRL3 to IRL0 level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. SR at the time the interrupt is accepted is saved to SSR. The code corresponding to the IRL3 to IRL0 level is set in INTEVT and INTEVT2. The corresponding code is given as H'200 + B' (IRL3-IRL0) x H'20. See table 6.4 for the corresponding code. The BL, MD, and RB bits in SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set in the interrupt mask bit of SR. See section 6, Interrupt Controller (INTC), for more information. * IRQ Pin Interrupts Conditions: IRQ pin is asserted and the interrupt mask bit of SR is lower than the IRQ priority level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR + H'0600. The received level is not set to the interrupt mask bit of SR. See section 6, Interrupt Controller (INTC), for more information. * On-Chip Peripheral Module Interrupts Conditions: The interrupt mask bit of SR is lower than the on-chip peripheral module (TMU, RTC, SCI0, SCI2, A/D, LCDC, PCC, DMAC, WDT, REF) interrupt level and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The SR at the point the interrupt is accepted is saved to the SSR. The code corresponding to the interrupt source is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC), for more information. * H-UDI Interrupt Conditions: H-UDI interrupt command is input (see section 21.4.4, H-UDI Interrupt) and the interrupt mask bit of SR is lower than 15 and the BL bit in SR is 0. The interrupt is accepted at an instruction boundary. Operations: The PC after the instruction that accepts the interrupt is saved to the SPC. The SR at the point the interrupt is accepted is saved to the SSR. H'5E0 is set to INTEVT and INTEVT2. The BL, MD, and RB bits of the SR are set to 1 and a branch occurs to VBR + H'0600. See section 6, Interrupt Controller (INTC), for more information. Rev. 4.00, 03/04, page 95 of 660 4.5 Usage Note * Return from exception processing Check the BL bit in SR with software. When the SPC and SSR have been saved to external memory, set the BL bit in SR to 1 before restoring them. Issue an RTE instruction. Set the SPC in the PC and SSR in SR with the RTE instruction, branch to the SPC address, and return from exception processing. * Operation when exception or interrupt occurs while SR.BL = 1 Interrupt: Acceptance is suppressed until the BL bit in SR is set to 0 by software. If there is a request and the reception conditions are satisfied, the interrupt is accepted after the execution of the instruction that sets the BL bit in SR to 0. During the sleep or standby mode, however, the interrupt will be accepted even when the BL bit in SR is 1. NMI is accepted when BLMSK in ICR1 is 1. Exception: No user break point trap will occur even when the break conditions are met. When one of the other exceptions occurs, a branch is made to the fixed address of the reset (H'A0000000). In this case, the values of the EXPEVT, SPC, and SSR registers are undefined. Differently from general reset processing, no signal is output from STATUS0 and STATUS1. * SPC when an Exception Occurs: The PC saved to the SPC when an exception occurs is as shown below: Re-executing-type exceptions: The PC of the instruction that caused the exception is set in the SPC and re-executed after return from exception processing. If the exception occurred in a delay slot, however, the PC of the immediately prior delayed branch instruction is set in the SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. Completed-type exceptions and interrupts: The PC of the instruction after the one that caused the exception is set in the SPC. If the exception was caused by a delayed conditional instruction, however, the branch destination PC is set in SPC. If the condition of the conditional delayed branch instruction is not satisfied, the delay slot PC is set in SPC. * Initial register values after reset Undefined registers R0_BANK0/1 to R7_BANK0/1, R8 to R15, GBR, SPC, SSR, MACH, MACL, PR Initialized registers VBR = H'00000000 SR.MD = 1, SR.BL = 1, SR.RB = 1, SR.I3 to SR.I0 = H'F, SR.CL = 0. Other SR bits are undefined. PC = H'A0000000 Rev. 4.00, 03/04, page 96 of 660 * Ensure that an exception is not generated at an RTE instruction delay slot, as operation is not guaranteed in this case. * When the BL bit in the SR register is set to 1, ensure that a TLB-related exception or address error does not occur at an LDC instruction that updates the SR register and the following instruction. This occurrence will be identified as multiple exceptions, and may initiate reset processing. Rev. 4.00, 03/04, page 97 of 660 Rev. 4.00, 03/04, page 98 of 660 Section 5 Cache 5.1 Feature * Instruction/data mixed, 16-byte cache * 256 entries/way, 4-way set associative, 16-byte block * Write-back/write-through selectable * LRU replacing algorithm * 1-stage write-back buffer * A maximum of two ways lockable 5.1.1 Cache Structure The cache uses a 4-way set associative system. It is composed of four ways (banks), each of which is divided into an address section and a data section. Each of the address and data sections is divided into 256 entries. The data section of the entry is called a line. Each line consists of 16 bytes (4 bytes x 4). The data capacity per way is 4 kbytes (16 bytes x 256 entries), with a total of 16 kbytes in the cache as a whole (4 ways). Figure 5.1 shows the cache structure. Address array (ways 0 to 3) Data array (ways 0 to 3) LRU Entry 0 Entry 1 V U Tag address 0 1 LW0 LW1 LW2 LW3 0 1 . . . . . . . . . . . . . . . . . . Entry 255 24 (1 + 1 + 22) bits 255 128 (32 x 4) bits LW0 to LW3: Longword data 0 to 3 255 6 bits Figure 5.1 Cache Structure Rev. 4.00, 03/04, page 99 of 660 Address Array: The V bit indicates whether the entry data is valid. When the V bit is 1, data is valid; when 0, data is not valid. The U bit indicates whether the entry has been written to in writeback mode. When the U bit is 1, the entry has been written to; when 0, it has not. The address tag holds the physical address used in the external memory access. It is composed of 22 bits (address bits 31 to 10) used for comparison during cache searches. In the SH7706, the top three of 32 physical address bits are used as shadow bits (see section 8, Bus State Controller (BSC)), and therefore in a normal replace operation the top three bits of the tag address are cleared to 0. The V and U bits are initialized to 0 by a power-on reset, but are not initialized by a manual reset. The tag address is not initialized by either a power-on or manual reset. Data Array: Holds a 16-byte instruction or data. Entries are registered in the cache in line units (16 bytes). The data array is not initialized by a power-on or manual reset. LRU: With the 4-way set associative system, up to four instructions or data with the same entry address (address bits 11 to 4) can be registered in the cache. When an entry is registered, the LRU bits show which of the four ways it is recorded in. There are six LRU bits, controlled by hardware. A least recently used (LRU) algorithm, which selects the way that has been used least recently, is used to select the way. The LRU bits also indicate the way to be replaced when a cache miss occurs. Table 5.1 shows the relationship between the LRU bits and the way to be replaced when cache locking mechanism is disabled. (For details on the case when cache locking mechanism is enabled, see section 5.2.2, Cache Control Register 2 (CCR2)). If a bit pattern other than those listed in table 5.1 is set in the LRU bits by software, the cache will not function correctly. When modifying the LRU bits by software, set one of the patterns listed in table 5.1. The LRU bits are initialized to B'000000 by a power on reset, but are not initialized by a manual reset. Table 5.1 LRU (5 to 0) 000000, 000100, 010100, 100000, 110000, 110100 000001, 000011, 001011, 100001, 101001, 101011 000110, 000111, 001111, 010110, 011110, 011111 111000, 111001, 111011, 111100, 111110, 111111 LRU and Way Replacement Way to be Replaced (when cache locking mechanism is disabled) 3 2 1 0 Rev. 4.00, 03/04, page 100 of 660 5.2 Register Description The cache includes the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Cache control register (CCR) * Cache control register 2 (CCR2) 5.2.1 Cache Control Register (CCR) The cache is enabled or disabled using the CE bit of the cache control register (CCR). CCR also has a CF bit (which invalidates all cache entries), and a WT and CB bits (which select either writethrough mode or write-back mode). Programs that change the contents of the CCR register should be placed in address space that is not cached. Bit Bit Name Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 3 CF 0 R Cache Flash When 1 is set, the V, U and LRU bits of all cache entries are cleared to 0 (flush). This bit is always read as 0. Write-back to external memory is not performed when the cache is flushed. 2 CB 0 R/W Cache Write-back Indicates the cache's operating mode for area P1. 0: Write-through mode 1: Write-back mode 1 WT 0 R/W Write through Indicates the cache's operating mode for area P0, U0, and P3. 0: Write-back mode 1: Write-through mode 0 CE 0 R/W Cache enable Indicates whether to use the cache function. 0: Cache not used 1: Cache used 31 to 4 Rev. 4.00, 03/04, page 101 of 660 5.2.2 Cache Control Register 2 (CCR2) Cache control register 2 (CCR2) enables or disables the cache locking mechanism. This register setting is valid only in cache locking mode. Cache locking mode is enabled when the cache locking bit (bit 12) of the status register (SR) is set to 1, and disabled when it is cleared to 0. If a cache miss occurs during prefetch instruction (PREF) execution in cache locking mode, one line size of data pointed by Rn is loaded into the cache according to the W3LOAD, W3LOCK, W2LOAD, and W2LOCK bit settings of CCR2 (bits 9, 8, 1, and 0). Table 5.2 shows the relationship between each bit setting and the way to be replaced when the prefetch instruction is executed. On the other hand, if a cache hit occurs during prefetch instruction (PREF) execution, no data is loaded into the cache and entries that have been valid in the cache are maintained. For instance, if one line size of data pointed by Rn exists at way 0, and if the prefetch instruction is executed while the cache lock, W3LOAD, and W3LOCK are set to 1s, a cache hit occurs and data is not brought to way 3. When a cache is accessed by other than the prefetch instruction in cache locking mode, the ways to be replaced are controlled by the W3LOCK and W2LOCK bit settings. Table 5.3 shows the relationship between CCR2 bit settings and the way to be replaced. A program to modify the CCR2 contents should be placed at an address area whose data is not cached. Bit 31 to 10 Bit Name Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 W3LOAD W3LOCK 0 W W W3LOAD: Way 3 load W3LOCK: Way 3 Lock When W3LOACK = 1 & W3LOAD = 1 & SR.CL is 1, the prefetched data will always be loaded into Way3. In all other conditions, the prefetched data will be loaded into the way pointed by LRU. 7 to 2 All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 W2LOAD W2LOCK 0 W W W3LOAD: Way 2 load W3LOCK: Way 2 Lock When W3LOACK = 1 & W3LOAD = 1 & SR.CL is 1, the prefetched data will always be loaded into Way2. In all other conditions, the prefetched data will be loaded into the way pointed by LRU. Note: Do not set 1 into W2LOAD and W3LOAD at the same time. Rev. 4.00, 03/04, page 102 of 660 Whenever CCR2 bit 8 (W3LOCK) or bit 0 (W2LOCK) is high level the cache is locked. The locked data will not be overwritten unless W3LOCK bit and W2LOCK bit are reset or the PREF condition during cache locking mode watches. During cache locking mode, the LRU in table 5.1 will be replaced by tables 5.4 to 5.6. Table 5.2 CL bit 0 1 1 1 1 1 1 Way to be Replaced when Cache Miss Occurs during PREF Instruction Execution W3LOAD * * * 0 0 0 1 W3LOCK * 0 0 1 1 * 1 W2LOAD * * 0 * 0 1 0 W2LOCK * 0 1 0 1 1 * Way to be Replaced According to LRU (table 5.1) According to LRU (table 5.1) According to LRU (table 5.4) According to LRU (table 5.5) According to LRU (table 5.6) Way 2 Way 3 Note: Do not set 1 into W2LOAD and W3LOAD at the same time. * Don't care Table 5.3 CL bit 0 1 1 1 1 Way to be Replaced when Cache Miss Occurs during Execution of Instruction other than PREF Instruction W3LOAD * * * * * W3LOCK * 0 0 1 1 W2LOAD * * * * * W2LOCK * 0 1 0 1 Way to be Replaced According to LRU (table 5.1) According to LRU (table 5.1) According to LRU (table 5.4) According to LRU (table 5.5) According to LRU (table 5.6) Note: Do not set 1 into W2LOAD and W3LOAD at the same time. * Don't care Table 5.4 LRU (5 to 0) LRU and Way Replacement (when W2LOCK=1) Way to be Replaced 3 1 0 000000, 000001, 000100, 010100, 100000, 100001, 110000, 110100 000011, 000110, 000111, 001011, 001111, 010110, 011110, 011111 101001, 101011, 111000, 111001, 111011, 111100, 111110, 111111 Rev. 4.00, 03/04, page 103 of 660 Table 5.5 LRU (5 to 0) LRU and Way Replacement (when W3LOCK=1) Way to be Replaced 2 1 0 000000, 000001, 000011, 001011, 100000, 100001, 101001, 101011 000100, 000110, 000111, 001111, 010100, 010110, 011110, 011111 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 Table 5.6 LRU (5 to 0) LRU and Way Replacement (when W2LOCK=1 and W3LOCK=1) Way to be Replaced 1 0 000000, 000001, 000011, 000100, 000110, 000111, 001011, 001111, 010100, 010110, 011110, 011111 100000, 100001, 101001, 101011, 110000, 110100, 111000, 111001, 111011, 111100, 111110, 111111 5.3 5.3.1 Operation Searching the Cache If the cache is enabled, whenever instructions or data in memory are accessed the cache will be searched to see if the desired instruction or data is in the cache. Figure 5.2 illustrates the method by which the cache is searched. The cache is a physical cache and holds physical addresses in its address section. Entries are selected using bits 11 to 4 of the address (virtual) of the access to memory and the address tag of that entry is read. In parallel to reading of the address tag, the virtual address is translated to a physical address in the MMU. The physical address after translation and the physical address read from the address section are compared. The address comparison uses all four ways. When the comparison shows a match and the selected entry is valid (V = 1), a cache hit occurs. When the comparison does not show a match or the selected entry is not valid (V = 0), a cache miss occurs. Rev. 4.00, 03/04, page 104 of 660 Virtual address 31 12 11 4 3 210 Entry selection Longword (LW) selection Ways 0 to 3 Ways 0 to 3 MMU 0 1 V U Tag address LW0 LW1 LW2 LW3 255 Physical address CMP0 CMP1 CMP2 CMP3 Legend CMP0: Comparison circuit 0 CMP1: Comparison circuit 1 CMP2: Comparison circuit 2 CMP3: Comparison circuit 3 Hit signal 1 Figure 5.2 Cache Search Scheme (Normal Mode) 5.3.2 Read Access Read Hit: In a read access, instructions and data are transferred from the cache to the CPU. The LRU is updated. Read Miss: An external bus cycle starts and the entry is updated. The way replaced is shown in table 5.3. Entries are updated in 16-byte units. When the desired instruction or data that caused the miss is loaded from external memory to the cache, the instruction or data is transferred to the CPU in parallel with being loaded to the cache. When it is loaded in the cache, the U bit is cleared to 0 and the V bit is set to 1. Rev. 4.00, 03/04, page 105 of 660 5.3.3 Prefetch Operation Prefetch Hit: LRU is updated so that the way that has been hit to be the latest. Other contents of the cache are not updated. Instruction or data is not transferred to the CPU. Prefetch Miss: Instruction or data is not transferred to the CPU. The way to be replaced is listed in table 5.2. Other operations are same as those in read miss. 5.3.4 Write Access Write Hit: In a write access in the write-back mode, the data is written to the cache and the U bit of the entry written is set to 1. Writing occurs only to the cache; no external memory write cycle is issued. In the write-through mode, the data is written to the cache and an external memory write cycle is issued. Write Miss: In the write-back mode, an external write cycle starts when a write miss occurs, and the entry is updated. The way to be replaced is shown in table 5.3. When the U bit of the entry to be replaced is 1, the cache fill cycle starts after the entry is transferred to the write-back buffer. The write-back unit is 16 bytes. Data is written to the cache and the U bit and V bit are set to 1. After the cache completes its fill cycle, the write-back buffer writes back the entry to the memory. In the write-through mode, no write to cache occurs in a write miss; the write is only to the external memory. 5.3.5 Write-Back Buffer When the U bit of the entry to be replaced in the write-back mode is 1, it must be written back to the external memory. To increase performance, the entry to be replaced is first transferred to the write-back buffer and fetching of new entries to the cache takes priority over writing back to the external memory. After fetching of new entries to the cache is completed, the data in the writeback buffer is write back to the external memory. During the write back cycles, the cache can be accessed. The write-back buffer can hold one line of the cache data (16 bytes) and its physical address. Figure 5.3 shows the configuration of the write-back buffer. PA (31 to 4) Longword 0 Longword 1 Longword 2 Longword 3 PA (31 to 4): Physical address written to external memory Longword 0 to 3: The line of cache data to be written to external memory Figure 5.3 Write-Back Buffer Configuration Rev. 4.00, 03/04, page 106 of 660 5.3.6 Coherency of Cache and External Memory Use software to ensure coherency between the cache and the external memory. To allocate memory shared by this LSI and the external device to an address area to be cached, invalidate the entries by operating the memory allocating cache as required. If necessary, for the memory shared by the CPU and the direct memory access controller in this LSI, invalidation must also be performed in the same way as described above. 5.4 Memory-Mapped Cache To allow software management of the cache, cache contents can be read and written by means of MOV instructions in the privileged mode. The cache is mapped onto the P4 area in virtual address space. The address array is mapped onto addresses H'F0000000 to H'F0FFFFFF, and the data array onto addresses H'F1000000 to H'F1FFFFFF. Only longword can be used as the access size for the address array and data array, and instruction fetches cannot be performed. 5.4.1 Address Array The address array is mapped onto H'F0000000 to H'F0FFFFFF. To access an address array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the tag address, V bit, U bit, and LRU bits to be written to the address array (figure 5.4 (1)). In the address field, specify the entry address for selecting the entry (bits 11 to 4), W for selecting the way (bits 13 and 12: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), A for selecting the associative operation (bit 3), and H'F0 to indicate address array access (bits 31 to 24). In data field, specify the tag address (bits 31 to 10), LRU bits (bits 9 to 4), U bit (bit 1), and V bit (bit 0). Upper three bits of the tag address (bits 31 to 29) should always be 0. The following three operations are enabled for the address array. Address Array Read: Read the tag address, LRU bits, U bit, and V bit of the entry specified by the entry address and the way number. When reading, no associative operation is performed regardless of the value of the associative bit (bit A) specified in the address. Address Array Write (without associative operation): Write the tag address, LRU bits, U bit, and V bit specified in the data field to the entry specified by the entry address and the way number. The associative bit (bit A) should be 0. If data is written to the cache line in which U and V bits are set to 1, the cache line is written back, and then the tag address, LRU bits, U bit, and V bit specified in the data field are written to. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. Rev. 4.00, 03/04, page 107 of 660 Address Array Write (with associative operation): When writing while the associative bit (bit A) is 1, the addresses of four entries selected by the entry addresses are compared to the tag addresses specified in the data field. As a result of the comparison, U bit and V bit specified in the data field are written to the entry for the hit way. Note however, that the tag address and LRU bits are not changed. When no ways are hit, nothing is written to the address array and no operation occurs. This operation is used to invalidate a specific entry of the cache. When the U bit of the hit entry is 1, write back is occurs. However, when 0 is written to the V bit, 0 must also be written to the U bit of that entry. 5.4.2 Data Array The data array is mapped onto H'F1000000 to H'F1FFFFFF. To access a data array, the 32-bit address field (for read/write accesses) and 32-bit data field (for write accesses) must be specified. The address field specifies information for selecting the entry to be accessed; the data field specifies the longword data to be written to the data array. In the address field, specify the entry address for selecting the entry (bits 11 to 4), L indicating the longword position within the (16-byte) line (bits 3 and 2: 00 is longword 0, 01 is longword 1, 10 is longword 2, and 11 is longword 3), W for selecting the way (bits 13 and 12: 00 is way 0, 01 is way 1, 10 is way 2, and 11 is way 3), and H'F1 to indicate data array access (bits 31 to 24). The access size of the data array is fixed at longword, so 00 should be specified to bits 1 and 0 in the address field. The following two operations are enabled for data array. However, information of the address array is not changed by the following operations. Data Array Read: Reads data specified by L (bits 3 and 2) in the address field from the entry specified by the entry address and the way number. Data Array Write: Writes a longword data specified by the data field to the position specified by L (bits 3 and 2) in the address field from the entry specified by the entry address and the way number. Rev. 4.00, 03/04, page 108 of 660 (1) Address array access Address specification Read access 31 24 1111 0000 Write access 31 24 1111 0000 23 14 *............* 13 12 W 11 4 Entry address 3 0 2 * 0 0 0 23 14 *............* 13 12 W 11 4 Entry address 3 A 2 * 0 0 0 Data specification (both read and write accesses) 313029 000 10 9 Address tag (28-10) LRU 4 3 X 2 X 1 U 0 V (2) Data array access (both read and write accesses) Address specification 31 24 1111 0001 Data specification 31 Longword X: 0 for read, don't care for write *: Don't care 0 23 14 *............* 13 12 W 11 4 Entry address 3 L 2 1 0 0 0 Figure 5.4 Specifying Address and Data for Memory-Mapped Cache Access Rev. 4.00, 03/04, page 109 of 660 5.4.3 Usage Examples 1. Invalidating Specific Entries Specific cache entries can be invalidated by writing 0 to the entry's U and V bit. When the A bit is 1, the address tag specified by the write data is compared to the address tag within the cache selected by the entry address, and data is written when a match is found. If no match is found, there is no operation. When the V bit of the entry is 1, a write back occurs. ; R0=H'0110 0010; VPN=B'00 0000 0100 0100 0000 0000, U=0, V=0 ; R1=H'F000 0088; address array access, entry=B'0000 1000, A=1 ; MOV.L R0,@R1 2. Reading the Data of a Specific Entry This example reads the data section of a specific cache entry. The longword indicated in the data field of the data array in figure 5.6 is read to the register. ; R1=H'F100 004C; data array access, entry=B'0000 0100, Way=0, ; longword address=3 ; MOV.L @R0,R1 ; Longword 3 is read. Rev. 4.00, 03/04, page 110 of 660 Section 6 Interrupt Controller (INTC) The interrupt controller (INTC) ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The INTC has registers for setting the priority of each interrupt, and interrupt requests are handled according to the priorities set in these registers. 6.1 Feature INTC has the following features: * 16 levels of interrupt priority can be set: By setting the five interrupt-priority registers, the priorities of on-chip peripheral module, IRQ interrupts can be selected from 16 levels for individual request sources. * NMI noise canceler function: NMI input-level bit indicates NMI pin states. By reading this bit in the interrupt exception service routine, the pin state can be checked, enabling it to be used as a noise canceler. * External devices can be notified that an interrupt has been received (IRQOUT): When the SH7706 has released the bus right, the external bus master can be notified that an external interrupt, an on-chip peripheral module interrupt or a memory refresh request has occurred, enabling this LSI to request the bus right. Rev. 4.00, 03/04, page 111 of 660 Figure 6.1 is a block diagram of the INTC. IRQOUT NMI IRL3 to IRL0 IRQ0 to IRQ5 4 6 Input control DMAC SCIF SCI ADC TMU RTC WDT (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request) (Interrupt request/ refresh request) (Interrupt request) Priority identifier Comparator Interrupt request SR 3 2 1 0 CPU REF H-UDI ICR IPR IPRA to IPRE Bus interface INTC Legend TMU: RTC: SCI: SCIF: WDT: REF: ICR: IPRA-IPRE: SR: DMAC: ADC: H-UDI: Timer unit Realtime clock unit Serial communication interface Serial communication interface (with FIFO) Watchdog timer Refresh requests in the bus state controller Interrupt control register Registers A-E for setting the interrupt proprity levels Status register Direct memory access controller Analog-to-digital converter User debugging interface Figure 6.1 INTC Block Diagram Rev. 4.00, 03/04, page 112 of 660 Internal bus 6.2 Input/Output Pin Table 6.1 lists the INTC pin configuration. Table 6.1 Name Nonmaskable interrupt input pin Interrupt input pins Pin Configuration Abbreviation NMI IRQ5 to IRQ0 IRL3 to IRL0 I/O I I Description Nonmaskable interrupt request signal input Interrupt request signal input (Maskable by interrupt mask bits in SR) Output of signal that notifies external devices that an interrupt source or memory refresh has occurred Interrupt request output pin IRQOUT O 6.3 Interrupt Sources There are 4 types of interrupt sources: NMI, IRQ, IRL, and on-chip peripheral modules. The priority of each interrupt is indicated by a priority level value (16 to 0), with level 16 as the highest and level 1 as the lowest. When level 0 is set, the interrupt is masked and interrupt requests are ignored. 6.3.1 NMI Interrupts The NMI interrupt has the highest priority level of 16. When the BLMSK bit of the interrupt control register (ICR1) is 1 or the BL bit of the status register (SR) is 0, NMI interrupts are accepted when the MAI bit of the ICR1 register is 0. NMI interrupts are edge-detected. In sleep or software standby mode, the interrupt is accepted regardless of the BL. The NMI edge select bit (NMIE) in the interrupt control register 0 (ICR0) is used to select either the rising or falling edge. When the NMIE bit of the ICR0 register is changed, the NMI interrupt is not detected for 20 cycles after changing the ICR0. NMIE to avoid a false detection of the NMI interrupt. NMI interrupt exception processing does not affect the interrupt mask level bits (I3 to I0) in the status register (SR). When the BL bit is 1 and the BLMSK bit of the ICR1 register is set to 1, only NMI interrupts are accepted and the SPC register and SSR register are updated by the NMI interrupt handler, making it impossible to return to the original processing from exception processing initiated prior to the NMI. Use should therefore be restricted to cases where return is not necessary. It is possible to wake the chip up from the software standby state with an NMI interrupt (except when the MAI bit of the ICR1 register is set to 1). Rev. 4.00, 03/04, page 113 of 660 6.3.2 IRQ Interrupt IRQ interrupts are input by priority from pins IRQ0 to IRQ5 with a level or an edge. The priority level can be set by priority setting registers C to D (IPRC to IPRD) in a range from levels 0 to 15. When using edge-sensing for IRQ interrupts, clear the interrupt source by having software read 1 from the corresponding bit in IRR0, then write 0 to the bit. When the ICR1 register is rewritten, IRQ interrupts may be mistakenly detected, depending on the pin states. To prevent this, rewrite the register while interrupts are masked, then release the mask after clearing the illegal interrupt by writing 0 to interrupt request register 0 (IRR0). It is necessary for an edge input interrupt detection to input a pulse width more than two-cycle width by peripheral clock (P) basis. In level detection, keep the level until the CPU accepts an interrupt and starts the interrupt processing. The interrupt mask bits (I3 to I0) of the status register (SR) are not affected by IRQ interrupt processing. Interrupts IRQ4 to IRQ0 can wake the chip up from the software standby state when the relevant interrupt level is higher than I3 to I0 in the SR register (but only when the RTC 32-kHz oscillator is used). Notes: When the IRQ is used in edge sensitive, pay attention to the following: 1. If an IRQ edge is input immediately before the CPU enters standby mode (the period between the SLEEP instruction executed by the CPU to high level of STATUS0), an interrupt may not be detected. In this case, when an IRQ edge is input again after STATUS0 becomes high level, an interrupt is detected. 2. If an IRQ edge is input while the frequency is changed by the FRQCR STC bit (when the WDT is counting), an interrupt may not be detected. In this case, when an IRQ edge is input again after the WDT halts counting, an interrupt is detected. Rev. 4.00, 03/04, page 114 of 660 6.3.3 IRL Interrupts IRL interrupts are input by level at pins IRL3 to IRL0. The priority level is the higher of those indicated by pins IRL3 to IRL0. An IRL3 to IRL0 value of 0 (0000) indicates the highest-level interrupt request (interrupt priority level 15). A value of 15 (1111) indicates no interrupt request (interrupt priority level 0). Figure 6.2 shows an examples of an IRL interrupt connection. Table 6.2 shows IRL pins and interrupt levels. This LSI Interrupt request Priority encoder 4 to to Figure 6.2 Example of IRL Interrupt Connection Table 6.2 IRL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 IRL3 to IRL0 Pins and Interrupt Levels IRL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 IRL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 IRL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Interrupt Priority Level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Interrupt Request Level 15 interrupt request Level 14 interrupt request Level 13 interrupt request Level 12 interrupt request Level 11 interrupt request Level 10 interrupt request Level 9 interrupt request Level 8 interrupt request Level 7 interrupt request Level 6 interrupt request Level 5 interrupt request Level 4 interrupt request Level 3 interrupt request Level 2 interrupt request Level 1 interrupt request No interrupt request Rev. 4.00, 03/04, page 115 of 660 A noise-cancellation feature is built in, and the IRL interrupt is not detected unless the levels sampled at every supporting module cycle remain unchanged for two consecutive cycles, so that no transient level on the IRL pin change is detected. In the software standby mode, as the peripheral clock is stopped, noise cancellation is performed using the 32-kHz clock for the RTC instead. Therefore when the RTC is not used, interruption by means of IRL interrupts cannot be performed in software standby mode. The priority level of the IRL interrupt must not be lowered unless the interrupt is accepted and the interrupt processing starts. If the level is not retained, correct operation is not guaranteed. However, the priority level can be changed to a higher one. The interrupt mask bits (I3 to I0) in the status register (SR) are not affected by IRL interrupt processing. 6.3.4 On-Chip Peripheral Module Interrupts On-chip peripheral module interrupts are generated by the following eight modules: * Timer unit (TMU) * Realtime clock (RTC) * Serial communication interface (SCI, SCIF) * Bus state controller (BSC) * Watchdog timer (WDT) * Direct memory access controller (DMAC) * A/D converter (ADC) * User debugging interface (H-UDI) Not every interrupt source is assigned a different interrupt vector, but sources are reflected in the interrupt event registers (INTEVT and INTEVT2), so it is easy to identify sources by branching with the INTEVT or INTEVT2 register value as an offset. The priority level (from 0 to 15) can be set for each module except for H-UDI by writing to the interrupt priority setting registers A, B and E (IPRA, IPRB and IPRE). The priority level of HUDI interrupt is 15 (fixed). The interrupt mask bits (I3 to I0) of the SR are not affected by the on-chip peripheral module interrupt processing. TMU and RTC interrupts can restore the chip from the software standby state when the relevant interrupt level is higher than I3 to I0 in the SR (but only when the RTC 32-kHz oscillator is used). Rev. 4.00, 03/04, page 116 of 660 6.3.5 Interrupt Exception Processing and Priority Tables 6.3 and 6.4 lists the codes for the interrupt event register (INTEVT and INTEVT2), and the order of interrupt priority. Each interrupt source is assigned unique code. The start address of the interrupt service routine is common to each interrupt source. This is why, for instance, the value of INTEVT or INTEVT2 is used as offset at the start of the interrupt service routine and branched to identify the interrupt source. The order of priority of the on-chip peripheral module, IRQ, and PINT interrupts is set within the priority levels 0 to 15 at will by using the interrupt priority level set to registers A to E (IPRA to IPRE). The order of priority of the on-chip peripheral module, IRQ, and PINT interrupts is set to zero by RESET. When the order of priorities for multiple interrupt sources are set to the same level and such interrupts are generated at the same time, they are processed according to the default order listed in tables 6.3 and 6.4. Table 6.3 Interrupt Exception Handling Sources and Priority (IRQ Mode) INTEVT Code (INTEVT2 Code) H'1C0 (H'1C0) H'5E0 (H'5E0) IRQ0 IRQ1 IRQ2 IRQ3 IRQ4 IRQ5 DMAC DEI0 DEI1 DEI2 DEI3 SCIF (SCI2) ERI2 RXI2 BRI2 TXI2 H'200 to 3C0* (H'600) H'200 to 3C0* (H'620) H'200 to 3C0* (H'640) H'200 to 3C0* (H'660) H'200 to 3C0* (H'680) H'200 to 3C0* (H'6A0) H'200 to 3C0* (H'800) H'200 to 3C0* (H'820) H'200 to 3C0* (H'840) H'200 to 3C0* (H'860) H'200 to 3C0* (H'900) H'200 to 3C0* (H'920) H'200 to 3C0* (H'940) H'200 to 3C0* (H'960) Low Low 0 to 15 (0) IPRE (7 to 4) Low High Interrupt Priority (Initial Value) 16 15 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR (Bit Numbers) -- -- IPRC (3 to 0) IPRC (7 to 4) IPRC (11 to 8) Priority within IPR Setting Unit -- -- -- -- -- Default Priority High Interrupt Source NMI H-UDI IRQ IPRC (15 to 12) -- IPRD (3 to 0) IPRD (7 to 4) -- -- IPRE (15 to 12) High Rev. 4.00, 03/04, page 117 of 660 Interrupt Source ADC TMU0 TMU1 TMU2 ADI TUNI0 TUNI1 TUNI2 TICPI2 RTC ATI PRI CUI SCI (SCI0) ERI RXI TXI TEI WDT BSC (REF) ITI RCMI ROVI INTEVT Code (INTEVT2 Code) H'200 to 3C0* (H'980) H'400 (H'400) H'420 (H'420) H'440 (H'440) H'460 (H'460) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) H'560 (H'560) H'580 (H'580) H'5A0 (H'5A0) Interrupt Priority (Initial Value) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR (Bit Numbers) IPRE (3 to 0) Priority within IPR Default Setting Unit Priority -- High IPRA (15 to 12) -- IPRA (11 to 8) IPRA (7 to 4) -- High Low 0 to 15 (0) IPRA (3 to 0) High Low 0 to 15 (0) IPRB (7 to 4) High Low 0 to 15 (0) 0 to 15 (0) IPRB (15 to 12) -- IPRB (11 to 8) High Low Low Note: * The code corresponding to an interrupt level shown in table 6.5 is set. Rev. 4.00, 03/04, page 118 of 660 Table 6.4 Interrupt Exception Handling Sources and Priority (IRL Mode) INTEVT Code (INTEVT2 Code) H'1C0 (H'1C0) H'5E0 (H'5E0) Interrupt Priority (Initial Value) 16 15 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) IPR (Bit Numbers) -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- IPRD (3 to 0) IPRD (7 to 4) Priority within IPR Setting Default Unit Priority -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- High Interrupt Source NMI H-UDI IRL IRL(3:0) = 0000 IRL(3:0) = 0001 IRL(3:0) = 0010 IRL(3:0) = 0011 IRL(3:0) = 0100 IRL(3:0) = 0101 IRL(3:0) = 0110 IRL(3:0) = 0111 IRL(3:0) = 1000 IRL(3:0) = 1001 IRL(3:0) = 1010 IRL(3:0) = 1011 IRL(3:0) = 1100 IRL(3:0) = 1101 IRL(3:0) = 1110 IRQ IRQ4 IRQ5 DMAC DEI0 DEI1 DEI2 DEI3 SCIF (SCI2) ERI2 RXI2 BRI2 TXI2 ADC ADI H'200 (H'200) H'220 (H'220) H'240 (H'240) H'260 (H'260) H'280 (H'280) H'2A0 (H'2A0) H'2C0 (H'2C0) H'2E0 (H'2E0) H'300 (H'300) H'320 (H'320) H'340 (H'340) H'360 (H'360) H'380 (H'380) H'3A0 (H'3A0) H'3C0 (H'3C0) H'200 to 3C0* (H'680) H'200 to 3C0* (H'6A0) H'200 to 3C0* (H'800) H'200 to 3C0* (H'820) H'200 to 3C0* (H'840) H'200 to 3C0* (H'860) H'200 to 3C0* (H'900) H'200 to 3C0* (H'920) H'200 to 3C0* (H'940) H'200 to 3C0* (H'960) H'200 to 3C0* (H'980) IPRE (15 to 12) High Low 0 to 15 (0) IPRE (7 to 4) High Low 0 to 15 (0) IPRE (3 to 0) -- Low Rev. 4.00, 03/04, page 119 of 660 Interrupt Source TMU0 TMU1 TMU2 TUNI0 TUNI1 TUNI2 TICPI2 RTC ATI PRI CUI SCI (SCI0) ERI RXI TXI TEI WDT BSC (REF) ITI RCMI ROVI INTEVT Code (INTEVT2 Code) H'400 (H'400) H'420 (H'420) H'440 (H'440) H'460 (H'460) H'480 (H'480) H'4A0 (H'4A0) H'4C0 (H'4C0) H'4E0 (H'4E0) H'500 (H'500) H'520 (H'520) H'540 (H'540) H'560 (H'560) H'580 (H'580) H'5A0 (H'5A0) Interrupt Priority (Initial Value) 0 to 15 (0) 0 to 15 (0) 0 to 15 (0) Priority IPR within IPR Default (Bit Numbers) Setting Unit Priority IPRA (15 to 12) -- IPRA (11 to 8) -- IPRA (7 to 4) High Low High 0 to 15 (0) IPRA (3 to 0) High Low 0 to 15 (0) IPRB (7 to 4) High Low 0 to 15 (0) 0 to 15 (0) IPRB (15 to 12) -- IPRB (11 to 8) High Low Low Note: * The code corresponding to an interrupt level shown in table 6.5 is set. Table 6.5 Interrupt Level and INTEVT Code INTEVT Code H'200 H'220 H'240 H'260 H'280 H'2A0 H'2C0 H'2E0 H'300 H'320 H'340 H'360 H'380 H'3A0 H'3C0 Interrupt level 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Rev. 4.00, 03/04, page 120 of 660 6.4 Register Description The INTC has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Interrupt control register 0 (ICR0) * Interrupt control register 1 (ICR1) * Interrupt priority level setting register A (IPRA) * Interrupt priority level setting register B (IPRB) * Interrupt priority level setting register C (IPRC) * Interrupt priority level setting register D (IPRD) * Interrupt priority level setting register E (IPRE) * Interrupt request register 0 (IRR0) * Interrupt request register 1 (IRR1) * Interrupt request register 2 (IRR2) 6.4.1 Interrupt Priority Registers A to E (IPRA to IPRE) The interrupt priority level setting registers A to E (IPRA to IPRE) are 16-bit read/write registers that set priority levels from 0 to 15 for on-chip peripheral module interrupts. These registers are initialized to H'0000 at power-on reset, manual reset, or in hardware standby mode, but is not initialized in standby mode. Table 6.6 lists the relationship between the interrupt sources and the IPRA to IPRE bits. Table 6.6 Register IPRA IPRB IPRC IPRD IPRE Note: * Interrupt Request Sources and IPRA to IPRE Bits 15 to 12 TMU0 WDT IRQ3 Reserved* DMAC Bits 11 to 8 TMU1 REF IRQ2 Reserved* Reserved* Bits 7 to 4 TMU2 SCI0 IRQ1 IRQ5 SCIF Bits 3 to 0 RTC Reserved* IRQ0 IRQ4 ADC These bits are always read as 0. The write value should be 0. As shown in table 6.6, four sets of on-chip peripheral module, IRQ interrupts are assigned to each register. 4-bit groups (bits 15 to 12, bits 11 to 8, bits 7 to 4, and bits 3 to 0) are set with values from H'0 (0000) to H'F (1111). Setting H'0 means priority level 0 (masking is requested); H'F is priority level 15 (the highest level). A reset initializes IPRA to IPRE to H'0000. H'0 should be set into bits corresponding to an unused interrupt. Rev. 4.00, 03/04, page 121 of 660 6.4.2 Interrupt Control Register 0 (ICR0) The interrupt control register 0 (ICR0) is a 16-bit register that sets the input signal detection mode of the external interrupt input pin NMI and indicates the input signal level to the NMI pin. This register is initialized to H'0000 at power-on reset or manual reset, but is not initialized in standby mode. Bit 15 Bit Name NMIL Initial Value 0/1* R/W R Description NMI Input Level Sets the level of the signal input at the NMI pin. This bit can be read to determine the NMI pin level. This bit cannot be modified. 0: NMI input level is low 1: NMI input level is high 14 to 9 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8 NMIE 0 R/W NMI Edge Select Selects whether the interrupt request signal is detected on the falling or rising edge of NMI input. 0: Interrupt request signal is detected on falling edge of NMI input 1: Interrupt request signal is detected on rising edge of NMI input 7 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Note: * When NMI input is high: 1; when NMI input is low: 0. Rev. 4.00, 03/04, page 122 of 660 6.4.3 Interrupt Control Register 1 (ICR1) The interrupt control register 1 (ICR1) is a 16-bit register that specifies the detection mode to external interrupt input pins, IRQ0 to IRQ5 individually: rising edge, falling edge, or low level. Bit 15 Bit Name MAI Initial Value 0 R/W R/W Description Mask All Interrupts When set to 1, masks all interrupt requests when a low level is being input to the NMI pin. Masks NMI interrupts in standby mode. 0: All interrupt requests are not masked when a low level is being input to the NMI pin 1: All interrupt requests are masked when a low level is being input to the NMI pin 14 IRQLVL 1 R/W Interrupt Request Level Detect Selects whether the IRQ3 to IRQ0 pins are used as four independent interrupt pins or as 15-level interrupt pins encoded as IRL3 to IRL0. 0: Used as four independent interrupt request pins IRQ3 to IRQ0 1: Used as encoded 15-level interrupt pins as IRL3 to IRL0 13 BLMSK 0 R/W BL Bit Mask Specifies whether NMI interrupts are masked when the BL bit of the SR register is 1. 0: NMI interrupts are masked when the BL bit is 1 1: NMI interrupts are accepted regardless of the BL bit setting 12 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 11 10 IRQ51S IRQ50S 0 0 R/W R/W IRQ5 Sense Select Select whether the interrupt signal to the IRQ5 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ5 input falling edge 01: An interrupt request is detected at IRQ5 input rising edge 10: An interrupt request is detected at IRQ5 input low level 11: Reserved (Setting prohibited) Rev. 4.00, 03/04, page 123 of 660 Bit 9 8 Bit Name IRQ41S IRQ40S Initial Value 0 0 R/W R/W R/W Description IRQ4 Sense Select Select whether the interrupt signal to the IRQ4 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ4 input falling edge 01: An interrupt request is detected at IRQ4 input rising edge 10: An interrupt request is detected at IRQ4 input low level 11: Reserved (Setting prohibited) 7 6 IRQ31S IRQ30S 0 0 R/W R/W IRQ3 Sense Select Select whether the interrupt signal to the IRQ3 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ3 input falling edge 01: An interrupt request is detected at IRQ3 input rising edge 10: interrupt request is detected at IRQ3 input low level 11: Rserved (Setting prohibited) 5 4 IRQ21S IRQ20S 0 0 R/W R/W IRQ2 Sense Select Select whether the interrupt signal to the IRQ2 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ2 input falling edge 01: An interrupt request is detected at IRQ2 input rising edge 10: An interrupt request is detected at IRQ2 input low level 11: Reserved (Setting prohibited) Rev. 4.00, 03/04, page 124 of 660 Bit 3 2 Bit Name IRQ11S IRQ10S Initial Value 0 0 R/W R/W R/W Description IRQ1 Sense Select Select whether the interrupt signal to the IRQ1 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ1 input falling edge 01: An interrupt request is detected at IRQ1 input rising edge 10: An interrupt request is detected at IRQ1 input low level 11: Reserved (Setting prohibited) 1 0 IRQ01S IRQ00S 0 0 R/W R/W IRQ0 Sense Select Select whether the interrupt signal to the IRQ0 pin is detected at the rising edge, at the falling edge, or at low level. 00: An interrupt request is detected at IRQ0 input falling edge 01: An interrupt request is detected at IRQ0 input rising edge 10: An interrupt request is detected at IRQ0 input low level 11: Reserved (Setting prohibited) 6.4.4 Interrupt Request Register 0 (IRR0) The interrupt request register 0 (IRR0) is an 8-bit register that indicates interrupt requests from external input pins IRQ0 to IRQ5. When clearing IRQ5R to IRQ0R bit to 0, 0 should be written to the bit after the bit is set to 1 and the contents of 1 are read. Only 0 can be written to IRQ5R to IRQ0R. Bit 7, 6 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00, 03/04, page 125 of 660 Bit 5 Bit Name IRQ5R Initial Value R/W 0 R/W Description IRQ5 Interrupt Request Indicates whether an interrupt request is input to the IRQ5 pin. When edge detection mode is set for IRQ5, an interrupt request is cleared by clearing the IRQ5R bit. 0: An interrupt request is not input to IRQ5 pin 1: An interrupt request is input to IRQ5 pin 4 IRQ4R 0 R/W IRQ4 Interrupt Request Indicates whether an interrupt request is input to the IRQ4 pin. When edge detection mode is set for IRQ4, an interrupt request is cleared by clearing the IRQ4R bit. 0: An interrupt request is not input to IRQ4 pin 1: An interrupt request is input to IRQ4 pin 3 IRQ3R 0 R/W IRQ3 Interrupt Request Indicates whether an interrupt request is input to the IRQ3 pin. When edge detection mode is set for IRQ3, an interrupt request is cleared by clearing the IRQ3R bit. 0: An interrupt request is not input to IRQ3 pin 1: An interrupt request is input to IRQ3 pin 2 IRQ2R 0 R/W IRQ2 Interrupt Request Indicates whether an interrupt request is input to the IRQ2 pin. When edge detection mode is set for IRQ2, an interrupt request is cleared by clearing the IRQ2R bit. 0: An interrupt request is not input to IRQ2 pin 1: An interrupt request is input to IRQ2 pin 1 IRQ1R 0 R/W IRQ1 Interrupt Request Indicates whether an interrupt request is input to the IRQ1 pin. When edge detection mode is set for IRQ1, an interrupt request is cleared by clearing the IRQ1R bit. 0: An interrupt request is not input to IRQ1 pin 1: An interrupt request is input to IRQ1 pin 0 IRQ0R 0 R/W IRQ0 Interrupt Request (IRQ0R) Indicates whether an interrupt request is input to the IRQ0 pin. When edge detection mode is set for IRQ0, an interrupt request is cleared by clearing the IRQ0R bit. 0: An interrupt request is not input to IRQ0 pin 1: An interrupt request is input to IRQ0 pin Rev. 4.00, 03/04, page 126 of 660 6.4.5 Interrupt Request Register 1 (IRR1) The interrupt request register 1 (IRR1) is an 8-bit read-only register that indicates whether DMAC or IrDA interrupt requests are generated. Bit 7 to 4 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 3 DEI3R 0 R DEI3 Interrupt Request Indicates whether a DEI3 (DMAC) interrupt request is generated. 0: A DEI3 interrupt request is not generated 1: A DEI3 interrupt request is generated 2 DEI2R 0 R DEI2 Interrupt Request Indicates whether a DEI2 (DMAC) interrupt request is generated. 0: A DEI2 interrupt request is not generated 1: A DEI2 interrupt request is generated 1 DEI1R 0 R DEI1 Interrupt Request Indicates whether a DEI1 (DMAC) interrupt request is generated. 0: A DEI1 interrupt request is not generated 1: A DEI1 interrupt request is generated 0 DEI0R 0 R DEI0 Interrupt Request Indicates whether a DEI0 (DMAC) interrupt request is generated. 0: A DEI0 interrupt request is not generated 1: A DEI0 interrupt request is generated Rev. 4.00, 03/04, page 127 of 660 6.4.6 Interrupt Request Register 2 (IRR2) The interrupt request register 2 (IRR2) is an 8-bit read-only register that indicates whether A/D converter, or SCIF interrupt requests are generated. Bit 7 to 5 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 4 ADIR 0 R ADI Interrupt Request Indicates whether an ADI (ADC) interrupt request is generated. 0: An ADI interrupt request is not generated 1: An ADI interrupt request is generated 3 TXI2R 0 R TXI2 Interrupt Request Indicates whether a TXI2 (SCIF) interrupt request is generated. 0: TXI2 interrupt request is not generated 1: A TXI2 interrupt request is generated 2 BRI2R 0 R BRI2 Interrupt Request Indicates whether a BRI2 (SCIF) interrupt request is generated. 0: A BRI2 interrupt request is not generated 1: A BRI2 interrupt request is generated 1 RXI2R 0 R RXI2 Interrupt Request Indicates whether an RXI2 (SCIF) interrupt request is generated. 0: An RXI2 interrupt request is not generated 1: An RXI2 interrupt request is generated 0 ERI2R 0 R ERI2 Interrupt Request Indicates whether an ERI2 (SCIF) interrupt request is generated. 0: An ERI2 interrupt request is not generated 1: An ERI2 interrupt request is generated Rev. 4.00, 03/04, page 128 of 660 6.5 6.5.1 Operation Interrupt Sequence The sequence of interrupt operations is explained below. Figure 6.3 is a flowchart of the operations. 1. The interrupt request sources send interrupt request signals to the interrupt controller. 2. The interrupt controller selects the highest priority interrupt from the interrupt requests sent, following the priority levels set in interrupt priority registers A to E (IPRA to IPRE). Lower priority interrupts are held pending. If two of these interrupts have the same priority level or if multiple interrupts occur within a single module, the interrupt with the highest default priority or the highest priority within its IPR setting unit (as indicated in table 6.3 and table 6.4) is selected. 3. The priority level of the interrupt selected by the interrupt controller is compared with the interrupt mask bits (I3 to I0) in the status register (SR) of the CPU. If the request priority level is higher than the level in bits I3 to I0, the interrupt controller accepts the interrupt and sends an interrupt request signal to the CPU. When the interrupt controller receives an interrupt, a low level is output from the IRQOUT pin. 4. Detection timing: The INTC operates in synchronization with the peripheral clock (P), and reports the interrupt request to the CPU. The CPU receives an interrupt at a break in instruction. 5. The interrupt source code is set in the interrupt event registers (INTEVT and INTEVT2). 6. The SR and PC are saved to SSR and SPC, respectively. 7. The BL, MD, and RB in SR are set to 1. 8. The CPU jumps to the start address of the interrupt handler (the sum of the value set in the vector base register (VBR) and H'00000600). This jump is not a delayed branch. The interrupt handler may branch with the INTEVT register value as its offset in order to identify the interrupt source. This enables it to branch to the processing routine for the individual interrupt source. Notes: 1. The interrupt mask bits (I3 to I0) in the SR are not changed by acceptance of an interrupt in this LSI. 2. IRQOUT outputs a low level until the interrupt request is cleared. However, if the interrupt source is masked by an interrupt mask bit, the IRQOUT pin returns to the high level. The level is output without regard to the BL bit. 3. The interrupt source flag should be cleared in the interrupt handler. The interrupt source flag should be cleared in the interrupt handler. To ensure that an interrupt request that should have been cleared is not inadvertently accepted again, read the source flag after it has been cleared, then wait for the interval shown in "Time for Rev. 4.00, 03/04, page 129 of 660 priority decision and SR mask bit comparison" in table 6.7 before clearing the BL bit or executing an RTE instruction. Program execution state ICR1.MAI = 1? No No Yes NMI = low? No Yes Interrupt generated? Yes No ICR1.BLMSK = 1? Yes Yes No NMI? Yes Yes NMI? No No SR. BL= 0 or sleepmode? Level 15 interrupt? Yes = 1? Set interrupt cause in INTEVT, INTEVT2 Save SR to SSR; save PC to SPC Set BL/MD/RB bits in SR to 1 Branch to exception handler Yes I3 to I0 level 14 or lower? No Yes No Level 14 interrupt? Yes I3 to I0 level 13 or lower? No Yes No Level 1 interrupt? Yes I3 to I0 level 0? No No I3 to I0: Interrupt mask bits in status register (SR) Figure 6.3 Interrupt Operation Flowchart Rev. 4.00, 03/04, page 130 of 660 6.5.2 Multiple Interrupts When multiple interrupts are used, the structure of the interrupt service routine should be as follows. 1. Branch to a specific interrupt handler corresponding to a code set in INTEVT and INTEVT2. The code in INTEVT and INTEVT2 can be used as a branch-offset for branching to the specific handler. 2. Clear the cause of the interrupt in each specific handler. 3. Save SSR and SPC to the memory. 4. Clear the BL bit in SR, and set the accepted interrupt level in the interrupt mask bits in SR. 5. Handle the interrupt. 6. Execute the RTE instruction. When these procedures are followed in order, an interrupt of higher priority than the one being handled can be accepted after clearing BL in step 4. Rev. 4.00, 03/04, page 131 of 660 6.6 Interrupt Response Time The time from generation of an interrupt request until interrupt exception processing is performed and fetching of the first instruction of the exception handler is started (the interrupt response time) is shown in table 6.7. Figure 6.4 shows an example of pipeline operation when an IRL interrupt is accepted. When SR.BL is 1, interrupt exception processing is masked, and is kept waiting until completion of an instruction that clears BL to 0. The response time is represented by the clock number of I. Depending on the P phase when an interrupt is occurred, one clock period of P may vary from the contents of this table. Table 6.7 Interrupt Response Time Number of States Item NMI IRQ IRL Peripheral Modules Notes 1.5 x Icyc Time for priority 0.5 x Icyc decision and SR + 1.5 x Bcyc + 0.5 x Bcyc + 2 x Pcyc*2 mask bit comparison 0.5 x Icyc 0.5 x Icyc + 0.5 x Bcyc + 1.5 x Pcyc*3 + 3.5 x Pcyc 0.5 x Icyc + 3 x Pcyc*4 Interrupt exception processing is kept waiting until the executing instruction ends. If the number of instruction execution states is S*1, the maximum wait time is: X = S - 1. However, if BL is set to 1 by instruction execution or by an exception, interrupt exception processing is deferred until completion of an instruction that clears BL to 0. If the following instruction masks interrupt exception processing, the processing may be further deferred. X ( 0) x Icyc X ( 0) x Icyc X ( 0) x Icyc X ( 0) x Icyc Wait time until end of sequence being executed by CPU 5 x Icyc Time from interrupt exception processing (save of SR and PC) until fetch of first instruction of exception service routine is started 5 x Icyc 5 x Icyc 5 x Icyc Rev. 4.00, 03/04, page 132 of 660 Number of States Item Response Total time NMI (5.5 + X) x Icyc + 1.5 x Bcyc IRQ (6.5 + X) x Icyc + 0.5 x Bcyc + 2 x Pcyc*4 IRL (5.5 + X) x Icyc + 0.5 x Bcyc + 3.5 x Pcyc Peripheral Modules (5.5 + X) x Icyc + 1.5 x Pcyc*3 (5.5 + X) x Icyc + 3 x Pcyc*4 7*3/8.5*4 10.5 + S*3 16.5 + S* 4 Notes Minimum case 7 9 15.5 + S 9.5 20.5 + S I: B: P = 1:1:1 I: B: P = 4:1:1 Maximum 10.5 + S case Icyc: Duration of one cycle of I. Bcyc: Duration of one cycle of B. Pcyc: Duration of one cycle of P. Notes: 1. S also includes the memory access wait time. The processing requiring the maximum execution time is LDC.L @Rm+, SR. When the memory access is a cache-hit, this requires seven instruction execution cycles. When the external access is performed, the corresponding number of cycles must be added. There are also instructions that perform two external memory accesses; if the external memory access is slow, the number of instruction execution cycles will increase accordingly. 2. Edge detection. 3. Extended modules: TMU, RTC, SCI, WDT, REFC 4. Extended modules: DMAC, ADC, SCIF Rev. 4.00, 03/04, page 133 of 660 Interrupt acceptance Start of interrupt processing 0.5 x Icyc + 0.5 x Bcyc + 3.5 x Pcyc IRL 5 x Icyc Instruction (instruction replaced by interrupt exception processing) IF ID EX EX EX EX Overrun fetch IF First instruction of interrupt handler IF ID EX IF: ID: EX: Instruction fetch: Instruction is fetched from memory in which program is stored. Instruction decode: Fetched instruction is decoded. Instruction execution: Data operation and address calculation are performed in accordance with result of decoding. Figure 6.4 Example of Pipeline Operations when IRL Interrupt is Accepted Rev. 4.00, 03/04, page 134 of 660 Section 7 User Break Controller The UBC provides functions that simplify program debugging. Using this function, a self-monitor debugger can be easily prepared, and a program can be debugged using this LSI alone, without using an in-circuit emulator. Instruction fetches, data read/write, data size, data contents, address values, and the timing to stop execution at instruction fetch can be set to the UBC. The UBC block diagram is shown in figure 7.1. 7.1 Feature The UBC has the following features: * The following break comparison conditions can be set. Number of break channels: (channels A and B) Address: comparison bits are masked in units of 32 bits. One of the two address buses (the virtual address bus (LAB) and the internal address bus (IAB)) can be selected Data: only on channel B, 32-bit maskable One of two data buses (the virtual data bus (LDB) or the internal data bus (IDB)) can be selected. Bus master: CPU cycle or DMAC cycle Bus cycle: instruction fetch or data access Read/write Operand size: byte, word, or longword * A user-designed user-break condition exception processing routine can be run. * In an instruction fetch cycle, it can be selected that a break is set before or after an instruction is executed. * The number of repeat times can be specified as a break condition (It is only for channel B). Maximum repeat times for the break condition: 212 - 1 times. * Eight pairs of branch source/destination buffers. Rev. 4.00, 03/04, page 135 of 660 Access Control IAB LAB Access comparator MDB BBRA BARA Address comparator BAMRA ASID comparator Channel A BASRA Access comparator BBRB BARB Address comparator BAMRB ASID comparator BASRB BDRB BDMRB BETR BRSR Data comparator Channel B PC Trace BRDR CONTROL BRCR LDB/IDB CPU state signals User break request UBC Location CCN Location : Break ASID register B : Break data register B : Break data mask register B : Break execution times register : Branch source register : Branch destination register : Break control register Legend BBRA BARA BAMRA BASRA BBRB BARB BAMRB : Break bus cycle register A : Break address register A : Break address mask register A : Break ASID register A : Break bus cycle register B : Break address register B : Break address mask register B BASRB BDRB BDMRB BETR BRSR BRDR BRCR Figure 7.1 Block Diagram of User Break Controller Rev. 4.00, 03/04, page 136 of 660 7.2 Register Description The UBC has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Break address register A (BARA) * Break address mask register A (BAMRA) * Break bus cycle register A (BBRA) * Break address register B (BARB) * Break address mask register B (BAMRB) * Break bus cycle register B (BBRB) * Break data register B (BDRB) * Break data mask register B (BDMRB) * Break control register (BRCR) * Execution count break register (BETR) * Branch source register (BRSR) * Branch destination register (BRDR) * Break ASID register A (BASRA) * Break ASID register B (BASRB) 7.2.1 Break Address Register A (BARA) BARA is a 32-bit read/write register. BARA specifies the address used as a break condition in channel A. Bit 31 to 0 Bit Name BAA31 to BAA0 Initial Value R/W All 0 R/W Description Break Address Stores the address on the LAB or IAB that specifies break conditions of channel A. Rev. 4.00, 03/04, page 137 of 660 7.2.2 Break Address Mask Register A (BAMRA) BAMRA is a 32-bit read/write register. BAMRA specifies bits masked in the break address specified by BARA. Bit Bit Name Initial Value R/W R/W Description Break Address Mask Bit Specifies bits masked in the channel A break address bits specified by BARA (BAA31 to BAA0). 0: Break address bit BAAn of channel A is included in the break condition 1: Break address bit BAAn of channel A is masked and is not included in the break condition Note: n = 31 to 0. 31 to 0 BAMA31 to All 0 BAMA0 7.2.3 Break Bus Cycle Register A (BBRA) Break bus cycle register A (BBRA) is a 16-bit read/write register, which specifies (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read or write, and (4) operand size in the break conditions of channel A. Bit 15 to 8 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 CDA1 CDA0 0 0 R/W R/W CPU Cycle/DMAC Cycle Select A Selects the CPU cycle or DMAC cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed X1: The break condition is the CPU cycle 10: The break condition is the DMAC cycle Rev. 4.00, 03/04, page 138 of 660 Bit 5 4 Bit Name IDA1 IDA0 Initial Value 0 0 R/W R/W R/W Description Instruction Fetch/Data Access Select A Selects the instruction fetch cycle or data access cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWA1 RWA0 0 0 R/W R/W Read/Write Select A Selects the read cycle or write cycle as the bus cycle of the channel A break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle 1 0 SZA1 SZA0 0 0 R/W R/W Operand Size Select A Selects the operand size of the bus cycle for the channel A break condition. 00: The break condition does not include operand size 11: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: X Don't care 7.2.4 Break Address Register B (BARB) BARB is a 32-bit read/write register. BARB specifies the address used as a break condition in channel B. Bit 31 to 0 Bit Name BAB31 to BAB0 Initial Value R/W All 0 R/W Description Break Address Stores the address of LAB or IAB that specifies the break conditions of channel B. Rev. 4.00, 03/04, page 139 of 660 7.2.5 Break Address Mask Register B (BAMRB) BAMRB is a 32-bit read/write register. BAMRB specifies bits masked in the break address specified by BARB. Bit 31 to 0 Bit Name Initial Value R/W R/W Description Break Address Mask Specifies bits masked in the channel B break address bits specified by BARB (BAB31 to BAB0). 0: Break address BABn of channel B is included in the break condition 1: Break address BABn of channel B is masked and is not included in the break condition Note: n = 31 to 0 BAMB31 to All 0 BAMB0 7.2.6 Break Data Register B (BDRB) BDRB is a 32-bit read/write register. Bit 31 to 0 Bit Name BDB31 to BDB0 Initial Value R/W All 0 R/W Description Break Data Bit 7.2.7 Break Data Mask Register B (BDMRB) BDMRB is a 32-bit read/write register. BDMRB specifies bits masked in the break data specified by BDRB. Bit 31 to 0 Bit Name BDMB31 to BDMB0 Initial Value R/W All 0 R/W Description Break Data Mask 0: Break data BDBn of channel B is included in the break condition 1: Break data BDBn of channel B is masked and is not included in the break condition Notes: n = 31 to 0 Specify an operand size when including the value of the data bus in the break condition. When a byte size is selected as a break condition, the break data must be set in bits 15 to 8 in BDRB for an even break address and bits 7 to 0 for an odd break address. Rev. 4.00, 03/04, page 140 of 660 7.2.8 Break Bus Cycle Register B (BBRB) Break bus cycle register B (BBRB) is a 16-bit read/write register, which specifies, (1) CPU cycle or DMAC cycle, (2) instruction fetch or data access, (3) read/write, and (4) operand size in the break conditions of channel B. Bit 15 to 8 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. These bits are always read as 0. 7 6 CDB1 CDB0 0 0 R/W R/W CPU Cycle/DMAC Cycle Select B Select the CPU cycle or DMAC cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed X1: The break condition is the CPU cycle 10: The break condition is the DMAC cycle 5 4 IDB1 IDB0 0 0 R/W R/W Instruction Fetch/Data Access Select B Select the instruction fetch cycle or data access cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the instruction fetch cycle 10: The break condition is the data access cycle 11: The break condition is the instruction fetch cycle or data access cycle 3 2 RWB1 RWB0 0 0 R/W R/W Read/Write Select B Select the read cycle or write cycle as the bus cycle of the channel B break condition. 00: Condition comparison is not performed 01: The break condition is the read cycle 10: The break condition is the write cycle 11: The break condition is the read cycle or write cycle Rev. 4.00, 03/04, page 141 of 660 Bit 1 0 Bit Name SZB1 SZB0 Initial Value 0 0 R/W R/W R/W Description Operand Size Select B Select the operand size of the bus cycle for the channel B break condition. 00: The break condition does not include operand size 01: The break condition is byte access 10: The break condition is word access 11: The break condition is longword access Note: X: Don't care 7.2.9 Break Control Register (BRCR) BRCR sets the following conditions: 1. Channels A and B are used in two independent channels condition or under the sequential condition. 2. A break is set before or after instruction execution. 3. A break is set by the number of execution times. 4. Determine whether to include data bus on channel B in comparison conditions. 5. Enable PC trace. 6. Enable the ASID check. The break control register (BRCR) is a 32-bit read/write register that has break conditions match flags and bits for setting a variety of break conditions. Bit 31 to 22 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 21 BASMA 0 R/W Break ASID Mask A Specifies whether the bits of the channel A break ASID7 to ASID0 (BASA7 to BASA0) set in BASRA are masked or not. 0: All BASRA bits are included in break condition, ASID is checked 1: No BASRA bits are included in break condition, ASID is not checked Rev. 4.00, 03/04, page 142 of 660 Bit 20 Bit Name BASMB Initial Value R/W 0 R/W Description Break ASID Mask B Specifies whether the bits of channel B break ASID7 to ASID0 (BASB7 to BASB0) set in BASRB are masked or not. 0: All BASRB bits are included in break condition, ASID is checked 1: No BASRB bits are included in break condition, ASID is not checked 19 to 16 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 15 SCMFCA 0 R/W CPU Condition Match Flag A When the CPU bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The CPU cycle condition for channel A does not match 1: The CPU cycle condition for channel A matches 14 SCMFCB 0 R/W CPU Condition Match Flag B When the CPU bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The CPU cycle condition for channel B does not match 1: The CPU cycle condition for channel B matches 13 SCMFDA 0 R/W DMAC Condition Match Flag A When the on-chip DMAC bus cycle condition in the break conditions set for channel A is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The DMAC cycle condition for channel A does not match 1: The DMAC cycle condition for channel A matches Rev. 4.00, 03/04, page 143 of 660 Bit 12 Bit Name SCMFDB Initial Value R/W 0 R/W Description DMAC Condition Match Flag B When the on-chip DMAC bus cycle condition in the break conditions set for channel B is satisfied, this flag is set to 1 (not cleared to 0). In order to clear this flag, write 0 into this bit. 0: The DMAC cycle condition for channel B does not match 1: The DMAC cycle condition for channel B matches 11 PCTE 0 R/W PC Trace Enable Enables PC trace. 0: Disables PC trace 1: Enables PC trace 10 PCBA 0 R/W PC Break Select A (PCBA) Selects the break timing of the instruction fetch cycle for channel A as before or after instruction execution. 0: PC break of channel A is set before instruction execution 1: PC break of channel A is set after instruction execution 9, 8 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 7 DBEB 0 R/W Data Break Enable B Selects whether or not the data bus condition is included in the break condition of channel B. 0: No data bus condition is included in the condition of channel B 1: The data bus condition is included in the condition of channel B 6 PCBB 0 R/W PC Break Select B Selects the break timing of the instruction fetch cycle for channel B as before or after instruction execution. 0: PC break of channel B is set before instruction execution 1: PC break of channel B is set after instruction execution 5, 4 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00, 03/04, page 144 of 660 Bit 3 Bit Name SEQ Initial Value 0 R/W R/W Description Sequence Condition Select Selects two conditions of channels A and B as independent or sequential. 0: Channels A and B are compared under the independent condition 1: Channels A and B are compared under the sequential condition 2, 1 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 ETBE 0 R/W The Number of Execution Times Break Enable Enable the execution-times break condition only on channel B. If this bit is 1 (break enable), a user break is issued when the number of break conditions matches with the number of execution times that is specified by the BETR register. 0: The execution-times break condition is masked on channel B 1: The execution-times break condition is enabled on channel B 7.2.10 Execution Times Break Register (BETR) When the execution-times break condition of channel B is enabled, this register specifies the number of execution times to make the break. The maximum number is 212 - 1 times. Everytime the break condition is satisfied, BETR is decremented by 1. A break is issued when the break condition is satisfied after the BETR becomes H'0001. Bit 15 to 12 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 to 0 -- All 0 R/W Number of execution times Rev. 4.00, 03/04, page 145 of 660 7.2.11 Branch Source Register (BRSR) BRSR is a 32-bit read register. BRSR stores the last fetched address before branch and the pointer (3 bits) which indicates the number of cycles from fetch to execution for the last executed instruction. BRSR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRSR is read and also initialized by power-on resets or manual resets. Other bits are not initialized by reset. Eight BRSR registers have queue structure and a stored register is shifted every branch. Bit 31 Bit Name SVF Initial Value R/W 0 R Description BRSR Valid Flag Indicates whether the address and the pointer by which the branch source address can be calculated. When a branch source address is fetched, this flag is set to 1. This flag is cleared to 0 in reading BRSR. 0: The value of BRSR register is invalid 1: The value of BRSR register is valid 30 to 28 PID2 to PID0 -- R Instruction Decode Pointer PID is a 3-bit binary pointer (0 to 7). These bits indicate the instruction buffer number which stores the last executed instruction before branch. Even: PID indicates the instruction buffer number. Odd: PiD+2 indicates the instruction buffer number 27 to 0 BSA27 to BSA0 -- R Branch Source Address These bits store the last fetched address before branch. Rev. 4.00, 03/04, page 146 of 660 7.2.12 Branch Destination Register (BRDR) BRDR is a 32-bit read register. BRDR stores the branch destination fetch address. BRDR has the flag bit that is set to 1 when branch occurs. This flag bit is cleared to 0, when BRDR is read and also initialized by power-on resets or manual resets. Other bits are not initialized by resets. Eight BRDR registers have queue structure and a stored register is shifted every branch. Bit 31 Bit Name DVF Initial Value 0 R/W R Description BRDR Valid Flag Indicates whether a branch destination address is stored. When a branch destination address is fetched, this flag is set to 1. This flag is set to 0 in reading BRDR. 0: The value of BRDR register is invalid 1: The value of BRDR register is valid 30 to 28 -- -- R Reserved These bits are always read as 0. The write value should always be 0. 27 to 0 BDA27 to BDA0 -- R Branch Destination Address These bits store the first fetched address after branch. 7.2.13 Break ASID Register A (BASRA) Break ASID register A (BASRA) is an 8-bit read/write register that specifies the ASID that serves as the break condition for channel A. It is not initialized by resets. It is located in CCN. Bit 7 to 0 Bit Name BASA7 to BASA0 Initial Value -- R/W R/W Description Break ASID These bits store the ASID (bits 7 to 0) that is the channel A break condition. Rev. 4.00, 03/04, page 147 of 660 7.2.14 Break ASID Register B (BASRB) Break ASID register B (BASRB) is an 8-bit read/write register that specifies the ASID that serves as the break condition for channel B. It is not initialized by resets. It is located in CCN. Bit 7 to 0 Bit Name BASB7 to BASB0 Initial Value R/W -- R/W Description Break ASID These bits store the ASID (bits 7 to 0) that is the channel B break condition. 7.3 7.3.1 Operation Flow of the User Break Operation The flow from setting of break conditions to user break exception processing is described below: 1. The break addresses and the corresponding ASIDs are loaded in the BARA, BARB, BASRA and BASRB. The masked addresses are set in the BAMRA and BAMRB. The break data is set in the BDRB. The masked data is set in the BDMRB. The breaking bus conditions are set in the BBRA and BBRB. Three groups of the BBRA and BBRB (CPU cycle/DMAC cycle select, instruction fetch/data access select, and read/write select) are each set. No user break will be generated if even one of these groups is set with 00. The respective conditions are set in the bits of the BRCR. 2. When the break conditions are satisfied, the UBC sends a user break request to the interrupt controller. The break type will be sent to CPU indicating the instruction fetch, pre/post instruction break, or data access break. When conditions match up, the CPU condition match flags (SCMFCA and SCMFCB) and DMAC condition match flags (SCMFDA and SCMFDB) for the respective channels are set. 3. The appropriate condition match flags (SCMFCA, SCMFDA, SCMFCB, and SCMFDB) can be used to check if the set conditions match or not. The matching of the conditions sets flags, but they are not reset. 0 must first be written to them before they can be used again. 4. There is a chance that the data access break and its following instruction fetch break occur around the same time, there will be only one break request to the CPU, but these two break channel match flags could be both set. Rev. 4.00, 03/04, page 148 of 660 7.3.2 Break on Instruction Fetch Cycle 1. When CPU/instruction fetch/read/word or longword is set in the break bus cycle registers (BBRA/BBRB), the break condition becomes the CPU instruction fetch cycle. Whether it then breaks before or after the execution of the instruction can then be selected with the PCBA/PCBB bits of the break control register (BRCR) for the appropriate channel. 2. An instruction set for a break before execution breaks when it is confirmed that the instruction has been fetched and will be executed. This means this feature cannot be used on instructions fetched by overrun (instructions fetched at a branch or during an interrupt transition, but not to be executed). When this kind of break is set for the delay slot of a delay branch instruction, the break is generated prior to execution of the instruction that then first accepts the break. Meanwhile, the break set for pre-instruction-break on delay slot instruction and postinstruction-break on SLEEP instruction are also prohibited. 3. When the condition is specified to be occurred after execution, the instruction set with the break condition is executed and then the break is generated prior to the execution of the next instruction. As with pre-execution breaks, this cannot be used with overrun fetch instructions. When this kind of break is set for a delay branch instruction, the break is generated at the instruction that then first accepts the break. 4. When an instruction fetch cycle is set for channel B, break data register B (BDRB) is ignored. There is thus no need to set break data for the break of the instruction fetch cycle. 7.3.3 Break by Data Access Cycle 1. The memory cycles in which CPU data access breaks occur are from instructions. 2. The relationship between the data access cycle address and the comparison condition for operand size are listed in table 7.1: Table 7.1 Access Size Longword Word Byte Data Access Cycle Addresses and Operand Size Comparison Conditions Address Compared Compares break address register bits 31 to 2 to address bus bits 31 to 2 Compares break address register bits 31 to 1 to address bus bits 31 to 1 Compares break address register bits 31 to 0 to address bus bits 31 to 0 This means that when address H'00001003 is set without specifying the size condition, for example, the bus cycle in which the break condition is satisfied is as follows (where other conditions are met). Longword access at H'00001000 Word access at H'00001002 Byte access at H'00001003 3. When the data value is included in the break conditions on B channel: Rev. 4.00, 03/04, page 149 of 660 When the data value is included in the break conditions, either longword, word, or byte is specified as the operand size of the break bus cycle registers (BBRA and BBRB). When data values are included in break conditions, a break is generated when the address conditions and data conditions both match. To specify byte data for this case, set the same data in two bytes at bits 15 to 8 and bits 7 to 0 of the break data register B (BDRB) and break data mask register B (BDMRB). When word or byte is set, bits 31 to 16 of BDRB and BDMRB are ignored. 4. When the DMAC data access is included in the break condition: When the address is included in the break condition on DMAC data access, the operand size of the break bus cycle registers (BBRA and BBRB) should be byte, word or no specified operand size. When the data value is included, select either byte or word. 7.3.4 Sequential Break 1. By specifying SEQ in BRCR is set to 1, the sequential break is issued when channel B break condition matches after channel A break condition matches. A user break is ignored even if channel B break condition matches before channel A break condition matches. When channels A and B condition match at the same time, the sequential break is not issued. 2. In sequential break specification, logical or internal bus can be selected and the execution times break condition can be also specified. For example, when the execution times break condition is specified, the break condition is satisfied at channel B condition match with BETR = H'0001 after channel A condition match. 7.3.5 Value of Saved Program Counter The PC when a break occurs is saved to the SPC in user breaks. The PC value saved is as follows depending on the type of break. 1. When instruction fetch (before instruction execution) is specified as a break condition: The value of the program counter (PC) saved is the address of the instruction that matches the break condition. The fetched instruction is not executed, and a break occurs before it. 2. When instruction fetch (after instruction execution) is specified as a break condition: The PC value saved is the address of the instruction to be executed following the instruction in which the break condition matches. The fetched instruction is executed, and a break occurs before the execution of the next instruction. 3. When data access (address only) is specified as a break condition: The PC value is the address of the instruction to be executed following the instruction that matched the break condition. The instruction that matched the condition is executed and the break occurs before the next instruction is executed. 4. When data access (address + data) is specified as a break condition: Rev. 4.00, 03/04, page 150 of 660 The PC value is the start address of the instruction that follows the instruction already executed when break processing started up. When a data value is added to the break conditions, the place where the break will occur cannot be specified exactly. The break will occur before the execution of an instruction fetched around the data access where the break occurred. 7.3.6 PC Trace 1. Setting PCTE in BRCR to 1 enables PC traces. When branch (branch instruction, repeat, and interrupt) is generated, the address from which the branch source address can be calculated and the branch destination address are stored in BRSR and BRDR, respectively. The branch address and the pointer, which corresponds to the branch, are included in BRSR. 2. The branch address before branch occurs can be calculated from the address and the pointer stored in BRSR. The expression from BSA (the address in BRSR), PID (the pointer in BRSR), and IA (the instruction address before branch occurs) is as follows: IA = BSA - 2 * PID. Notes are needed when an interrupt (a branch) is issued before the branch destination instruction is executed. In case of the next figure, the instruction "Exec" executed immediately before branch is calculated by IA = BSA - 2 * PID. However, when branch "branch" has delay slot and the destination address is 4n + 2 address, the address "Dest" which is specified by branch instruction is stored in BRSR (Dest = BSA). Therefore, as IA = BSA - 2 * PID is not applied to this case, this PID is invalid. The case where BSA is 4n + 2 boundary is applied only to this case and then some cases are classified as follows: Exec:branch Dest Dest:instr (not executed) interrupt Int: interrupt routine If the PID value is odd, instruction buffer indicates PID+2 buffer. However, these expressions in this table are accounted for it. Therefore, the true branch source address is calculated with BSA and PID values stored in BRSR. 3. The branch address before branch occurrence, IA, has different values due to some kinds of branch. a. Branch instruction The branch instruction address b. Interrupt The last instruction executed before interrupt The top address of interrupt routine is stored in BRDR. 4. BRSR and BRDR have eight pairs of queue structures. The top of queues is read first when the address stored in the PC trace register is read. BRSR and BRDR share the read pointer. Read BRSR and BRDR in order, the queue only shifts after BRDR is read. When reading BRDR, longword access should be used. Also, the PC trace has a trace pointer, which initially points to the bottom of the queues. The first pair of branch addresses will be stored at the bottom of Rev. 4.00, 03/04, page 151 of 660 the queues, then push up when next pairs come into the queues. The trace pointer will points to the next branch address to be executed, unless it got push out of the queues. When the branch address has been executed, the trace pointer will shift down to next pair of addresses, until it reaches the bottom of the queues. After switching the PCTE bit (in BRCR) off and on, the values in the queues are invalid. The read pointer stay at the position before PCTE is switched, but the trace pointer restart at the bottom of the queues. Rev. 4.00, 03/04, page 152 of 660 7.3.7 Usage Examples Break Condition Specified to a CPU Instruction Fetch Cycle 1. Register specifications BARA = H'00000404, BAMRA = H'00000000, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300400 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00000404, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not included in the condition) No ASID check is included * Channel B Address: Data: H'00008010, Address mask: H'00000006 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) No ASID check is included A user break occurs after an instruction of address H'00000404 is executed or before instructions of adresses H'00008010 to H'00008016 are executed. 2. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'0056, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode * Channel A Address: * Channel B Address: Data: H'0003722E, Address mask: H'00000000, ASID = H'70 H'00000000, Data mask: H'00000000 H'00037226, Address mask: H'00000000, ASID = H'80 Bus cycle: CPU/instruction fetch (before instruction execution)/read/word Bus cycle: CPU/instruction fetch (before instruction execution)/read/word An instruction with ASID = H'80 and address H'00037226 is executed, and a user break occurs before an instruction with ASID = H'70 and address H'0003722E is executed. Rev. 4.00, 03/04, page 153 of 660 3. Register specifications BARA = H'00027128, BAMRA = H'00000000, BBRA = H'005A, BARB = H'00031415, BAMRB = H'00000000, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300000 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00027128, Address mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/write/word No ASID check is included * Channel B Address: Data: H'00031415, Address mask: H'00000000 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) No ASID check is included On channel A, no user break occurs since instruction fetch is not a write cycle. On channel B, no user break occurs since instruction fetch is performed for an even address. 4. Register specifications BARA = H'00037226, BAMRA = H'00000000, BBRA = H'005A, BARB = H'0003722E, BAMRB = H'00000000, BBRB = H'0056, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000008, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B sequence mode * Channel A Address: * Channel B Address: Data: H'0003722E, Address mask: H'00000000, ASID: H'70 H'00000000, Data mask: H'00000000 H'00037226, Address mask: H'00000000, ASID: H'80 Bus cycle: CPU/instruction fetch (before instruction execution)/write/word Bus cycle: CPU/instruction fetch (before instruction execution)/read/word Since instruction fetch is not a write cycle on channel A, a sequence condition does not match. Therefore, no user break occurs. 5. Register specifications BARA = H'00000500, BAMRA = H'00000000, BBRA = H'0057, BARB = H'00001000, BAMRB = H'00000000, BBRB = H'0057, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00300001, BETR = H'0005 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00000500, Address mask: H'00000000 Rev. 4.00, 03/04, page 154 of 660 Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword * Channel B Address: Data: H'00001000, Address mask: H'00000000 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read/longword The number of execution-times break enable (5 times) On channel A, a user break occurs before an instruction of address H'00000500 is executed. On channel B, a user break occurs before the fifth instruction execution after instructions of address H'00001000 are executed four times. 6. Register specifications BARA = H'00008404, BAMRA = H'00000FFF, BBRA = H'0054, BARB = H'00008010, BAMRB = H'00000006, BBRB = H'0054, BDRB = H'00000000, BDMRB = H'00000000, BRCR = H'00000400, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: H'00008404, Address mask: H'00000FFF, ASID: H'80 Bus cycle: CPU/instruction fetch (after instruction execution)/read (operand size is not included in the condition) * Channel B Address: Data: H'00008010, Address mask: H'00000006, ASID: H'70 H'00000000, Data mask: H'00000000 Bus cycle: CPU/instruction fetch (before instruction execution)/read (operand size is not included in the condition) A user break occurs after an instruction with ASID = H'80 and address H'00008000 to H'00008FFE is executed or before instructions with ASID = H'70 and addresses H'00008010 to H'00008016 are executed. Break Condition Specified to a CPU Data Access Cycle 1. Register specifications BARA = H'00123456, BAMRA = H'00000000, BBRA = H'0064, BARB = H'000ABCDE, BAMRB = H'000000FF, BBRB = H'006A, BDRB = H'0000A512, BDMRB = H'00000000, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: H'000ABCDE, Address mask: H'000000FF, ASID: H'70 Rev. 4.00, 03/04, page 155 of 660 H'00123456, Address mask: H'00000000 Bus cycle: CPU/data access/read (operand size is not included in the condition) Data: H'0000A512, Data mask: H'00000000 Bus cycle: CPU/data access/write/word On channel A, a user break occurs with ASID = H'80 during longword read to address H'00123454, word read to address H'00123456, or byte read to address H'00123456. On channel B, a user break occurs with ASID = H'70 when word H'A512 is written in addresses H'000ABC00 to H'000ABCFE. Break Condition Specified to a DMAC Data Access Cycle 1. Register specifications: BARA = H'00314156, BAMRA = H'00000000, BBRA = H'0094, BARB = H'00055555, BAMRB = H'00000000, BBRB = H'00A9, BDRB = H'00000078, BDMRB = H'0000000F, BRCR = H'00000080, BASRA = H'80, BASRB = H'70 Specified conditions: Channel A/channel B independent mode * Channel A Address: * Channel B Address: Data: H'00055555, Address mask: H'00000000, ASID: H'70 H'00000078, Data mask: H'0000000F H'00314156, Address mask: H'00000000, ASID: H'80 Bus cycle: DMAC/instruction fetch/read (operand size is not included in the condition) Bus cycle: DMAC/data access/write/byte On channel A, no user break occurs since instruction fetch is not performed in DMAC cycles. On channel B, a user break occurs with ASID = H'70 when the DMAC writes byte H'7* in address H'00055555. 7.4 Usage Note 1. Only CPU can read/write UBC registers. 2. UBC cannot monitor CPU and DMAC access in the same channel. 3. Notes in specification of sequential break are described below: A. A condition match occurs when a channel B match occurs in a bus cycle after a channel A match occurs in another bus cycle in sequential break setting. Therefore, no condition match occurs even if a bus cycle, in which a channel A match and a channel B match occur simultaneously, is set. B. Since the CPU has a pipeline configuration, the pipeline determines the order of an instruction fetch cycle and a memory cycle. Therefore, when a channel condition matches in the order of bus cycles, a sequential condition is satisfied. C. When the bus cycle condition for channel A is specified as a break before execution (PCBA = 0 in BRCR) and an instruction fetch cycle (in BBRA), the attention is as follows. A break is issued and condition match flags in BRCR are set to 1, when the bus cycle conditions both for channels A and B match simultaneously. Rev. 4.00, 03/04, page 156 of 660 4. The change of a UBC register value is executed in MA (memory access) stage. Therefore, even if the break condition matches in the instruction fetch address following the instruction in which the pre-execution break is specified as the break condition, no break occurs. In order to know the timing UBC register is changed, read the last written register. Instructions after then are valid for the newly written register value. 5. The branch instruction should not be executed as soon as PC trace register BRSR and BRDR are read. 6. When PC breaks and TLB exceptions or errors occur in the same instruction. The priority is as follows: A. Break and instruction fetch exceptions: Instruction fetch exception occurs first. B. Break before execution and operand exception: Break before execution occurs first. C. Break after execution and operand exception: Operand exception occurs first. Rev. 4.00, 03/04, page 157 of 660 Rev. 4.00, 03/04, page 158 of 660 Section 8 Bus State Controller (BSC) The bus state controller (BSC) divides physical address space and output control signals for various types of memory and bus interface specifications. BSC functions enable this LSI to link directly with DRAM, synchronous DRAM, SRAM, ROM, and other memory storage devices without an external circuit. The BSC also allows direct connection to PCMCIA interfaces, simplifying system design and allowing high-speed data transfers in a compact system. Figure 8.1 shows the block diagram of the BSC. 8.1 Feature The BSC has the following features: * Physical address space is divided into six areas A maximum 64 Mbytes for each of the six areas, 0, 2 to 6 Area bus width can be selected by register (area 0 is set by external pin) Wait states can be inserted using the WAIT pin Wait state insertion can be controlled through software. Register settings can be used to specify the insertion of 1 to 10 cycles independently for each area (1 to 38 cycles for areas 5 and 6 and the PCMCIAT interface only) The type of memory connected can be specified for each area, and control signals are output for direct memory connection Wait cycles are automatically inserted to avoid data bus conflict for continuous memory accesses to different areas or writes directly following reads of the same area * Direct interface to synchronous DRAM (except when clock ratio becomes I:B = 1:1) Multiplexes row/column addresses according to synchronous DRAM capacity Supports burst operation Supports bank active mode Has both auto-refresh and self-refresh functions Controls timing of synchronous DRAM direct-connection control signals according to register setting * Burst ROM interface Insertion of wait states controllable through software Register setting control of burst transfers * PCMCIA direct-connection interface Insertion of wait states controllable through software Bus sizing function for I/O bus width (only in the little endian mode) Rev. 4.00, 03/04, page 159 of 660 * Refresh function Refresh cycles will be automatically maintained in the sleep mode even after the external bus frequency is reduced to 1/4 of its normal operating frequency * The refresh counter can be used as an interval timer Outputs an interrupt request signal using the compare-matching function Outputs an interrupt request signal when the refresh counter overflows Bus interface Wait controller WCR1 WCR2 , to , , Area controller BCR1 RD/ to Memory controller BCR2 MCR PCR RFCR RTCNT Refresh controller Comparator RTCOR RTCSR CKE , Interrupt controller Peripheral bus BSC Legend WCR: Wait state control register BCR : Bus control register MCR : Memory control register PCR : PCMCIA control register RFCR : Refresh count register RTCNT Refresh timer count register : RTCOR Refresh time constant register : RTCSR Refresh timer control/status register : Figure 8.1 BSC Functional Block Diagram Rev. 4.00, 03/04, page 160 of 660 Module bus Internal bus 8.2 Input/Output Pin Table 8.1 lists the BSC pin configuration. Table 8.1 Pin Name Address bus Data bus Pin Configuration Signal A25 to A0 D15 to D0 D31 to D16 BS I/O O I/O I/O O O O Description Address output Data I/O When 32-bit bus width, data I/O Shows start of bus cycle. During burst transfers, asserts every data cycle. Chip select signal to indicate area being accessed. Chip select signal to indicate area being accessed. CS5/CE1A and CS6/CE1B can also be used as CE1A and CE1B of PCMCIA. When PCMCIA is used, CE2A and CE2B Data bus direction indicator signal. Synchronous DRAM write indicator signal. When synchronous DRAM is used, RASL for lower 32Mbyte address. When synchronous DRAM is used, RASU for upper 32Mbyte address. When synchronous DRAM is used, CASL signal for lower 32-Mbyte address. When synchronous DRAM is used, CASU signal for upper 32-Mbyte address. When memory other than synchronous DRAM is used, selects D7 to D0 write strobe signal. When synchronous DRAM is used, selects D7 to D0. When memory other than synchronous DRAM is used, selects D15 to D8 write strobe signal. When synchronous DRAM is used, selects D15 to D8. When PCMCIA is used, strobe signal that indicates the write cycle. When memory other than synchronous DRAM is used, selects D23 to D16 write strobe signal. When synchronous DRAM is used, selects D23 to D16. When PCMCIA is used, strobe signal indicating I/O read. Bus cycle start Chip select 0, 2 to 4 CS0, CS2 to CS4 Chip select 5, 6 CS5/CE1A, CS6/CE1B PCMCIA card select CE2A, CE2B Read/write RD/WR O O O O O O O Row address strobe RASL L Row address strobe RASU U Column address strobe Column address strobe Data enable 0 CASL CASU WE0/DQMLL Data enable 1 WE1/DQMLU/ O WE Data enable 2 WE2/DQMUL/ O ICIORD Rev. 4.00, 03/04, page 161 of 660 Pin Name Data enable 3 Signal I/O Description When memory other than synchronous DRAM is used, selects D31 to D24 write strobe signal. When synchronous DRAM is used, selects D31 to D24. When PCMCIA is used, strobe signal indicating I/O write. Strobe signal indicating read cycle Wait state request signal Clock enable control signal of synchronous DRAM Signal indicating PCMCIA 16-bit I/O. Valid only in littleendian mode. Bus release request signal Bus release acknowledge signal WE3/DQMUU/ O ICIOWR Read Wait Clock enable IOIS16 RD WAIT CKE IOIS16 O I O I I O Bus release request BREQ Bus release acknowledgment BACK 8.3 Area Overview Space Allocation: In the architecture of this LSI, both logical spaces and physical spaces have 32bit address spaces. The logical space is divided into five areas by the value of the upper bits of the address. The physical space is divided into eight areas. Logical space can be allocated at physical spaces using a memory management unit (MMU). For details, refer to section 3, Memory Management Unit (MMU), which describes area allocation for physical spaces. As listed in table 8.2, this LSI can be connected directly to six areas of memory/PCMCIA interface, and it outputs chip select signals (CS0, CS2 to CS6, CE2A, CE2B) for each of them. CS0 is asserted during area 0 access; CS6 is asserted during area 6 access. When PCMCIA interface is selected in area 5 or 6, in addition to CS5/CS6, CE2A/CE2B are asserted for the corresponding bytes accessed. Rev. 4.00, 03/04, page 162 of 660 H'00000000 H'20000000 H'40000000 H'60000000 H'80000000 P1 H'A0000000 P2 H'C0000000 P3 H'E0000000 P4 Logical address space Note: P0, U0 Area 0 (CS0) Internal I/O Area 2 (CS2) Area 3 (CS3) Area 4 (CS4) Area 5 (CS5) Area 6 (CS6) Reserved area H'00000000 H'04000000 H'08000000 H'0C000000 H'10000000 H'14000000 H'18000000 Physical address space For logical address spaces P0 and P3, when the memory management unit (MMU) is on, it can optionally generate a physical address for the logical address. It can be applied when the MMU is off and when the MMU is on and each physical address for the logical address is equal except for upper three bits. See table 8.2, for information on converting logical addresses into user-defined physical addresses. Figure 8.2 Corresponding to Logical Address Space and Physical Address Space Table 8.2 Physical Address Space Map Physical Address H'00000000 to H'03FFFFFF H'00000000 + H'20000000 x n to H'03FFFFFF + H'20000000 x n 8 Area Connectable Memory 0 Ordinary memory* , burst ROM 1 Internal I/O registers* 1 Capacity 64 Mbytes Shadow 64 Mbytes Shadow 64 Mbytes Shadow 64 Mbytes Shadow 64 Mbytes Shadow Access Size 8, 16, 32* n: 1 to 6 8, 16, 32* n: 1 to 6 8, 16, 32* * n: 1 to 6 8, 16, 32* * n: 1 to 6 8, 16, 32* n: 1 to 6 3 3 5 3 4 3 2 H'04000000 to H'07FFFFFF H'04000000 + H'20000000 x n to H'07FFFFFF + H'20000000 x n 2 Ordinary memory* , synchronous DRAM 1 H'08000000 to H'0BFFFFFF H'08000000 + H'20000000 x n to H'0BFFFFFF + H'20000000 x n H'0C000000 to H'0FFFFFFF H'0C000000 + H'20000000 x n to H'0FFFFFFF + H'20000000 x n H'10000000 to H'13FFFFFF H'10000000 + H'20000000 x n to H'13FFFFFF + H'20000000 x n 3 Ordinary memory* , synchronous DRAM 1 4 Ordinary memory* 1 Rev. 4.00, 03/04, page 163 of 660 Area Connectable Memory 5 Ordinary memory* , PCMCIA, burst ROM 1 Physical Address H'14000000 to H'15FFFFFF H'16000000 to H'17FFFFFF H'14000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n Capacity 32 Mbytes 32 Mbytes Shadow 32 Mbytes Access Size 8, 16, 32* * 3 6 n: 1 to 6 8, 16, 32* * 3 6 6 Ordinary memory* , PCMCIA, burst ROM 1 H'18000000 to H'19FFFFFF H'1A000000 to H'1BFFFFFF H'18000000 + H'20000000 x n to H'1BFFFFFF + H'20000000 x n Shadow n: 1 to 6 n: 0 to 7 7* 7 Reserved area H'1C000000 + H'20000000 x n to H'1FFFFFFF + H'20000000 x n Notes: 1. 2. 3. 4. 5. 6. 7. Memory with interface such as SRAM or ROM. Use external pin to specify memory bus width. Use register to specify memory bus width. With synchronous DRAM interfaces, bus width must be 16 or 32 bits. With synchronous DRAM interfaces, bus width must be 16 or 32 bits. With PCMCIA interface, bus width must be 8 or 16 bits. Do not access the reserved area. If the reserved area is accessed, the correct operation cannot be guaranteed. 8. When the control register in area 1 is not used for address translation by the MMU, set the top three bits of the logical address to 101 to allocate in the P2 space. Area 0: H'00000000 Ordinary memory/ burst ROM Area 1: H'04000000 Internal I/O Area 2: H'08000000 Ordinary memory/ synchronous DRAM Ordinary memory/ synchronous DRAM Area 3: H'0C000000 Area 4: H'10000000 Ordinary memory Area 5: H'14000000 Ordinary memory/ burst ROM/PCMCIA Ordinary memory/ burst ROM/PCMCIA The PCMCIA interface is shared by the memory and I/O card The PCMCIA interface is shared by the memory and I/O card Area 6: H'18000000 Figure 8.3 Physical Space Allocation Rev. 4.00, 03/04, page 164 of 660 Memory Bus Width: The memory bus width in this LSI can be set for each area. In area 0, an external pin can be used to select byte (8 bits), word (16 bits), or longword (32 bits) on power-on reset. The correspondence between the external pins (MD4 and MD3) and memory size is listed in table below. Table 8.3 MD4 0 0 1 1 Correspondence between External Pins (MD4 and MD3) and Memory Size MD3 0 1 0 1 Memory Size Reserved (Setting prohibited) 8 bits 16 bits 32 bits For areas 2 to 6, byte, word, and longword may be chosen for the bus width using bus control register 2 (BCR2) whenever ordinary memory, ROM, or burst ROM are used. When the synchronous DRAM interface is used, word or longword can be chosen as the bus width. When the PCMCIA interface is used, set the bus width to byte or word. When synchronous DRAM is connected to both area 2 and area 3, set the same bus width for areas 2 and 3. When using port A or B, set a bus width of 8 or 16 bits for all areas. For more information, see section 8.4.2, Bus Control Register 2 (BCR2). Shadow Space: Areas 0, 2 to 6 are decoded by physical addresses A28 to A26, which correspond to areas 000 to 110. Address bits 31 to 29 are ignored. This means that the range of area 0 addresses, for example, is H'00000000 to H'03FFFFFF, and its corresponding shadow space is the address space obtained by adding to it H'20000000 x n (n = 1 to 6). The address range for area 7, which is on-chip I/O space, is H'1C000000 to H'1FFFFFFF. The address space H'1C000000 + H'20000000 x n-H'1FFFFFFF + H'20000000 x n (n = 0 to 7) corresponding to the area 7 shadow space is reserved, so do not use it. 8.3.1 PCMCIA Support This LSI supports PCMCIA standard interface specifications in physical space areas 5 and 6 (except for WP). The interfaces supported are basically the "IC memory card interface" and "I/O card interface" stipulated in JEIDA Specifications Ver. 4.2 (PCMCIA2.1). Rev. 4.00, 03/04, page 165 of 660 Table 8.4 Item Access Data bus Memory type PCMCIA Interface Characteristics Feature Random access 8/16 bits Mask ROM, OTPROM, EPROM, EEPROM, flash memory, SRAM Maximum 32 Mbytes Maximum 32 Mbytes Dynamic bus sizing of I/O bus width* The PCMCIA interface can be accessed from the address translation area or non-address translation area. Memory capacity I/O space capacity Others Note: * Dynamic bus sizing of I/O bus width is supported only in the little endian mode. Area 5: H'14000000 Area 5: H'16000000 Area 6: H'18000000 Area 6: H'1A000000 Commom memory/Attribute memory I/O space Commom memory/Attribute memory I/O space Figure 8.4 PCMCIA Space Allocation Table 8.5 PCMCIA Support Interface IC Memory Card Interface Pin Signal 1 2 3 4 5 6 7 8 9 10 GND D3 D4 D5 D6 D7 CE1 A10 OE A11 I/O Function -- Ground Signal GND D3 D4 D5 D6 D7 CE1 A10 OE A11 I/O Card Interface I/O Function -- Ground SH7706 Pin -- D3 D4 D5 D6 D7 CE1A or CE1B A10 RD A11 I/O Data I/O Data I/O Data I/O Data I/O Data I I I I Card enable Address Output enable Address I/O Data I/O Data I/O Data I/O Data I/O Data I I I I Card enable Address Output enable Address Rev. 4.00, 03/04, page 166 of 660 IC Memory Card Interface Pin Signal 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 A9 A8 A13 A14 WE/PGM RDY/BSY VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 WP* GND GND CD1 D11 D12 D13 D14 O I/O I/O I/O I/O I I I I I I I I I I I I/O Function I I I I I O Address Address Address Address Write enable Ready/Busy Operation power Program power Address Address Address Address Address Address Address Address Address Address Address Signal A9 A8 A13 A14 I/O Card Interface I/O I I I I I O Function Address Address Address Address Write enable Ready/Busy SH7706 Pin A9 A8 A13 A14 WE -- WE/PGM IREQ VCC VPP1 A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16 GND GND CD1 D11 D12 D13 D14 Operation power -- Program/ -- peripheral power I I I I I I I I I I I I/O I/O I/O O Address Address Address Address Address Address Address Address Address Address Address Data Data Data 16-bit I/O port Ground Ground O I/O I/O I/O I/O Card detection Data Data Data Data A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 IOIS16 -- -- -- D11 D12 D13 D14 I/O Data I/O I/O O Data Data Write protect Ground Ground Card detection Data Data Data Data Rev. 4.00, 03/04, page 167 of 660 IC Memory Card Interface Pin Signal 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 Note: D15 CE2 VS1 RFU RFU A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2 RESET WAIT RFU REG BVD2 BVD1 D8 D9 D10 CD2 GND I O O I/O I/O I/O O I I I I I I O I I I I I I/O I/O I I Function Data Card enable Voltage sense 1 Reserved Reserved Address Address Address Address Address Power supply Program power Address Address Address Address Voltage sense 2 Reset Wait request Reserved Attribute memory space select Battery voltage detection Battery voltage detection Data Data Data Card detection Ground Signal D15 CE2 VS1 IORD IOWR A17 A18 A19 A20 A21 VCC VPP2 A22 A23 A24 A25 VS2 RESET WAIT REG SPKR I/O Card Interface I/O I/O I I I I I I I I I Function Data Card enable Voltage sense 1 I/O read I/O write Address Address Address Address Address Power supply Program/ peripheral power I I I I I I O Address Address Address Address Voltage sense 2 Reset Wait request Input acknowledge Attribute memory space select Digital voice signal Card state change Data Data Data Card detection Ground SH7706 Pin D15 CE2A or CE2B -- ICIORD ICIOWR A17 A18 A19 A20 A21 -- -- A22 A23 A24 A25 -- -- -- -- -- -- -- D8 D9 D10 -- -- INPACK O I O STSCHG O D8 D9 D10 CD2 GND I/O I/O I/O O * This LSI does not support WP. Rev. 4.00, 03/04, page 168 of 660 8.4 Register Description The BSC has 11 registers. The synchronous DRAM also has a built-in synchronous DRAM mode register. These registers control direct connection interfaces to memory, wait states and refreshes. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Bus control register 1 (BCR1) * Bus control register 2 (BCR2) * Wait state control register 1 (WCR1) * Wait state control register 2 (WCR2) * Individual memory control register (MCR) * PCMCIA control register (PCR) * Synchronous DRAM mode register (SDMR) * Refresh timer control/status register (RTCSR) * Refresh timer counter (RTCNT) * Refresh time constant register (RTCOR) * Refresh count register (RFCR) 8.4.1 Bus Control Register 1 (BCR1) Bus control register 1 (BCR1) is a 16-bit read/write register that sets the functions and bus cycle state for each area. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or by standby mode. Do not access external memory outside area 0 until BCR1 register initialization is complete. Bit 15 Bit Name PULA Initial Value R/W 0 R/W Description Pin A25 to A0 Pull-Up Specifies whether or not pins A25 to A0 are pulled up for 4 cycles immediately after BACK is asserted. 0: Not pulled up 1: Pulled up 14 PULD 0 R/W Pin D31 to D0 Pull-Up Specifies whether or not pins D31 to D0 are pulled up when not in use. 0: Not pulled up 1: Pulled up Rev. 4.00, 03/04, page 169 of 660 Bit 13 Bit Name HIZMEM Initial Value R/W 0 R/W Description Hi-Z memory control Specifies the state of A25 to 0, BS, CS, RD/WR, WE/DQM, RD, CE2A, CE2B and DRAK0/1 in standby mode. 0: High-impedance state in standby mode. 1: Driven in standby mode. 12 HIZCNT 0 R/W High-Z Control Specifies the state of the RAS and the CAS signals at standby and bus right release. 0: High-impedance state at standby and bus right release. 1: Driven at standby and bus right release. 11 ENDIAN 0/1* 1 R Endian Flag Samples the value of the external pin designating endian upon a power-on reset. Endian for all physical spaces is decided by this bit, which is read-only. 0: (On reset) Endian setting external pin (MD5) is low. Indicates the SH7706 is set as big endian. 1: (On reset) Endian setting external pin (MD5) is high. Indicates the SH7706 is set as little endian. 10 9 A0BST1 A0BST0 0 0 R/W R/W Area 0 Burst ROM Control Specify whether to use burst ROM in physical space area 0. When burst ROM is used, set the number of burst transfers. 00: Access area 0 as ordinary memory 01: Access area 0 as burst ROM (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. 10: Access area 0 as burst ROM (8 consecutive accesses). Can be used when bus width is 8 or 16. 01: Access area 0 as burst ROM (16 consecutive accesses). Can be used only when bus width is 8. Rev. 4.00, 03/04, page 170 of 660 Bit 8 7 Bit Name A5BST1 A5BST0 Initial Value R/W 0 0 R/W R/W Description Area 5 Burst Enable Specify whether to use burst ROM and PCMCIA burst mode in physical space area 5. When burst ROM and PCMCIA burst mode are used, set the number of burst transfers. 00: Access area 5 as ordinary memory 01: Burst access of area 5 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. 10: Burst access of area 5 (8 consecutive accesses). Can be used when bus width is 8 or 16. 11: Burst access of area 5 (16 consecutive accesses). Can be used only when bus width is 8. 6 5 A6BST1 A6BST0 0 0 R/W R/W Area 6 Burst Enable Specify whether to use burst ROM and PCMCIA burst mode in physical space area 6. When burst ROM and PCMCIA burst mode are used, set the number of burst transfers. 00: Access area 6 as ordinary memory 01: Burst access of area 6 (4 consecutive accesses). Can be used when bus width is 8, 16, or 32. 10: Burst access of area 6 (8 consecutive accesses). Can be used when bus width is 8 or 16. 11: Burst access of area 6 (16 consecutive accesses). Can be used only when bus width is 8. 4 3 2 DRAMTP2 0 DRAMTP1 0 DRAMTP0 0 R/W R/W R/W Area 2, Area 3 Memory Type Designate the types of memory connected to physical space areas 2 and 3. Ordinary memory, such as ROM, SRAM, or flash ROM, can be directly connected. Synchronous DRAM can also be directly connected. 000: Areas 2 and 3 are ordinary memory 001: Reserved (Setting prohibited) 010: Area 2: ordinary memory; area 3: synchronous 3 DRAM* 011: Areas 2 and 3 are synchronous DRAM* * 100: Reserved (Setting prohibited) 101: Reserved (Setting prohibited) 110: Reserved (Setting prohibited) 111: Reserved (Setting prohibited) 2 3 Rev. 4.00, 03/04, page 171 of 660 Bit 1 Bit Name A5PCM Initial Value R/W 0 R/W Description Area 5 Bus Type Designates whether to access physical space area 5 as PCMCIA space. 0: Access physical space area 5 as ordinary memory 1: Access physical space area 5 as PCMCIA space 0 A6PCM 0 R/W Area 6 Bus Type Designates whether to access physical space area 6 as PCMCIA space. 0: Access physical space area 6 as ordinary memory 1: Access physical space area 6 as PCMCIA space Notes: 1. Samples the value of the external pin (MD5) designating endian at power-on reset. 2. When selecting this mode, set the same bus width for areas 2 and 3. 3. Do not access to the SRAM when the clock ratio is I : B = 1:1. 8.4.2 Bus Control Register 2 (BCR2) The bus control register 2 (BCR2) is a 16-bit read/write register that selects the bus-size width and 8-bit port of each area. It is initialized to H'3FF0 by a power-on reset, but is not initialized by a manual reset or by standby mode. Do not access external memory outside area 0 until BCR2 register initialization is complete. Bit 15, 14 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 13 12 A6SZ1 A6SZ0 1 1 R/W R/W Area 6 Bus Size Specification Specify the bus sizes of physical space area 6. * When port A/B is unused. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Longword (32-bit) size * When port A/B is used. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Reserved (Setting prohibited) Rev. 4.00, 03/04, page 172 of 660 Bit 11 10 Bit Name A5SZ1 A5SZ0 Initial Value R/W 1 1 R/W R/W Description Area 5 Bus Size Specification Specify the bus sizes of physical space area 5. * When port A/B is unused. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Longword (32-bit) size * When port A/B is used. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Reserved (Setting prohibited) 9 8 A4SZ1 A4SZ0 1 1 R/W R/W Area 4 Bus Size Specification Specify the bus sizes of physical space area 4. * When port A/B is unused. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Longword (32-bit) size * When port A/B is used. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Reserved (Setting prohibited) 7 6 A3SZ1 A3SZ0 1 1 R/W R/W Area 3 Bus Size Specification Specify the bus sizes of physical space area 3. * When port A/B is unused. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Longword (32-bit) size * When port A/B is used. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Reserved (Setting prohibited) Rev. 4.00, 03/04, page 173 of 660 Bit 5 4 Bit Name A2SZ1 A2SZ0 Initial Value 1 1 R/W R/W R/W Description Area 2 Bus Size Specification Specify the bus sizes of physical space area 2. * When port A/B is unused. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Longword (32-bit) size * When port A/B is used. 00: Reserved (Setting prohibited) 01: Byte (8-bit) size 10: Word (16-bit) size 11: Reserved (Setting prohibited) 3 to 0 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 8.4.3 Wait State Control Register 1 (WCR1) Wait state control register 1 (WCR1) is a 16-bit read/write register that specifies the number of idle (wait) state cycles inserted for each area. For some memories, the drive of the data bus may not be turned off quickly even when the read signal from the external device is turned off. This can result in conflicts between data buses when consecutive memory accesses are to different memories or when a write immediately follows a memory read. This LSI automatically inserts idle states equal to the number set in WCR1 in those cases. WCR1 is initialized to H'3FF3 by a power-on reset. It is not initialized by a manual reset or by standby mode. Bit 15 Bit Name WAITSEL Initial Value R/W 0 R/W Description WAIT Sampling Timing Select Specifies the WAIT signal sampling timing. 0: Set 1 to use the WAIT signal. 1: The WAIT signal is sampled at the falling edge of CKIO. 14 -- 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00, 03/04, page 174 of 660 Bit 13 12 Bit Name A6IW1 A6IW0 Initial Value R/W 1 1 R/W R/W Description Area 6 Intercycle Idle Specification Specify the number of idles inserted between bus cycles when switching between physical space area 6 to another space or between a read access to a write access in the same physical space. 00: 1 idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 3 idle cycles inserted 11 10 A5IW1 A5IW0 1 1 R/W R/W Area 5 Intercycle Idle Specification Specify the number of idles inserted between bus cycles when switching between physical space area 5 to another space or between a read access to a write access in the same physical space. 00: 1 idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 3 idle cycles inserted 9 8 A4IW1 A4IW0 1 1 R/W R/W Area 4 Intercycle Idle Specification Specify the number of idles inserted between bus cycles when switching between physical space area 4 to another space or between a read access to a write access in the same physical space. 00: 1 idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 3 idle cycles inserted 7 6 A3IW1 A3IW0 1 1 R/W R/W Area 3 Intercycle Idle Specification Specify the number of idles inserted between bus cycles when switching between physical space area 3 to another space or between a read access to a write access in the same physical space. 00: 1 idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 3 idle cycles inserted Rev. 4.00, 03/04, page 175 of 660 Bit 5 4 Bit Name A2IW1 A2IW0 Initial Value R/W 1 1 R/W R/W Description Area 2 Intercycle Idle Specification Specify the number of idles inserted between bus cycles when switching between physical space area 2 to another space or between a read access to a write access in the same physical space. 00: 1 idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 3 idle cycles inserted 3, 2 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 1 0 A0IW1 A0IW0 1 1 R/W R/W Area 0 Intercycle Idle Specification Specify the number of idles inserted between bus cycles when switching between physical space area 0 to another space or between a read access to a write access in the same physical space. 00: 1 idle cycle inserted 01: 1 idle cycle inserted 10: 2 idle cycles inserted 11: 3 idle cycles inserted Rev. 4.00, 03/04, page 176 of 660 8.4.4 Wait State Control Register 2 (WCR2) Wait state control register 2 (WCR2) is a 16-bit read/write register that specifies the number of wait state cycles inserted for each area. It also specifies the pitch of data access for burst memory accesses. This allows direct connection of even low-speed memories without an external circuit. Bit 15 14 13 Bit Name A6W2 A6W1 A6W0 Initial Value R/W 1 1 1 R/W R/W R/W Description Area 6 Wait Control Specify the number of wait states inserted into physical space area 6. Also specify the burst pitch for burst transfer. Refer to table 8.6 for details. 12 11 10 A5W2 A5W1 A5W0 1 1 1 R/W R/W R/W Area 5 Wait Control Specify the number of wait states inserted into physical space area 5. Also specify the burst pitch for burst transfer. Refer to table 8.7 for details. 9 8 7 6 5 A4W2 A4W1 A4W0 A3W1 A3W0 1 1 1 1 1 R/W R/W R/W R/W R/W Area 4 Wait Control Specify the number of wait states inserted into physical space area 4. Refer to table 8.8 for details. Area 3 Wait Control Specify the number of wait states inserted into physical space area 3. * 00: 01: 10: 11: * 00: 01: 10: 11: For Ordinary memory Inserted Wait States 0 1 2 3 For Synchronus DRAM Synchronus DRAM :CAS Latency 1 1 2 3 WAIT Pin Ignored Enable Enable Enable Rev. 4.00, 03/04, page 177 of 660 Bit 4 3 Bit Name A2W1 A2W0 Initial Value 1 1 R/W R/W R/W Description Area 2 Wait Control Specify the number of wait states inserted into physical space area 2. * 00: 01: 10: 11: * 00: 01: 10: 11: For Ordinary memory Inserted Wait States 0 1 2 3 For Synchronus DRAM Synchronus DRAM :CAS Latency 1 1 2 3 WAIT Pin Ignored Enabled Enabled Enabled 2 1 0 A0W2 A0W1 A0W0 1 1 1 R/W R/W R/W Area 0 Wait Control Specify the number of wait states inserted into physical space area 0. Also specify the burst pitch for burst transfer. Refer to table 8.9 for details. Table 8.6 Area 6 Wait Control Description WCR2's bits Bit 15: A6W2 0 Bit 14: A6W1 0 Bit 13: A6W0 0 1 1 0 1 1 0 0 1 1 0 1 First Cycle Inserted Wait States 0 1 2 3 4 6 8 10 WAIT Pin Ignored Enable Enable Enable Enable Enable Enable Enable Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enable Enable Enable Enable Enable Enable Enable Enable Rev. 4.00, 03/04, page 178 of 660 Table 8.7 Area 5 Wait Control Description WCR2's bits Bit 12: A5W2 0 Bit 11: A5W1 0 Bit 10: A5W0 0 1 1 0 1 1 0 0 1 1 0 1 First Cycle Inserted Wait States 0 1 2 3 4 6 8 10 WAIT Pin Ignored Enable Enable Enable Enable Enable Enable Enable Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enable Enable Enable Enable Enable Enable Enable Enable Table 8.8 Area 4 Wait Control WCR2's bits Description Bit 7: A4W0 0 1 1 0 1 Inserted Wait State 0 1 2 3 4 6 8 10 WAIT Pin Ignored Enable Enable Enable Enable Enable Enable Enable Bit 9: A4W2 0 Bit 8: A4W1 0 1 0 0 1 1 0 1 Rev. 4.00, 03/04, page 179 of 660 Table 8.9 Area 0 Wait Control Description WCR2's bits Bit 2: A0W2 0 Bit 1: A0W1 0 Bit 0: A0W0 0 1 1 0 1 1 0 0 1 1 0 1 First Cycle Inserted Wait States 0 1 2 3 4 6 8 10 WAIT Pin Ignored Enable Enable Enable Enable Enable Enable Enable Burst Cycle (Excluding First Cycle) Number of States Per Data Transfer WAIT Pin 2 2 3 4 4 6 8 10 Enable Enable Enable Enable Enable Enable Enable Enable 8.4.5 Individual Memory Control Register (MCR) The individual memory control register (MCR) is a 16-bit read/write register that specifies RAS and CAS timing and burst control for synchronous DRAM (areas 2 and 3), specifies address multiplexing, and controls refresh. This enables direct connection of synchronous DRAM without external circuits. The MCR is initialized to H'0000 by power-on resets, but is not initialized by manual resets or standby mode. The bits TPC1, TPC0, RCD1, RCD0, TRWL1, TRWL0, TRAS1, TRAS0, RASD and AMX3 to AMX0 are written to at the initialization after a power-on reset and are not then modified again. When RFSH and RMODE are written to, write the same values to the other bits. When using synchronous DRAM, do not access areas 2 and 3 until this register is initialized. Rev. 4.00, 03/04, page 180 of 660 Bit 15 14 Bit Name TPC1 TPC0 Initial Value 0 0 R/W R/W R/W Description RAS Precharge Time When synchronous DRAM interface is selected as connected memory, they set the minimum number of cycles until output of the next bank-active command after precharge. The number of cycles to be inserted immediately after issuing a precharge all banks (PALL) command in auto-refresh or a precharge (PRE) command in bank-active mode is one cycle less than the normal value. In bank-active mode, neither TPC1 nor TPC0 should be cleared to 0. Normal Operation 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles Immediately after* Immediately Precharge after Command Self-Refresh 0 cycle 1 cycle 2 cycles 3 cycles 2 cycles 5 cycles 8 cycles 11 cycles Note: * Immediately after a precharge all banks (PALL) command in auto-refresh and a precharge (PRE) command in bank-active mode. 13 12 RCD1 RCD0 0 0 R/W R/W RAS-CAS Delay When synchronous DRAM interface is selected as connected memory, sets the bank active read/write command delay time. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: 4 cycles Rev. 4.00, 03/04, page 181 of 660 Bit 11 10 Bit Name TRWL1 TRWL0 Initial Value 0 0 R/W R/W R/W Description Write-Precharge Delay The TRWL bits set the synchronous DRAM writeprecharge delay time. This designates the time between the end of a write cycle and the next bank-active command. This is valid only when synchronous DRAM is connected. After the write cycle, the next bank-active command is not issued for the period TPC + TRWL. 00: 1 cycle 01: 2 cycles 10: 3 cycles 11: Reserved (Setting prohibited) 9 8 TRAS1 TRAS0 0 0 R/W R/W CAS-Before-RAS Refresh RAS Assert Time When synchronous DRAM interface is selected as connected memory, no bank-active command is issues during the period TPC + TRAS after an auto-refresh command. 00: 2 cycles 01: 3 cycles 10: 4 cycles 11: 5 cycles 7 RASD 0 R/W Synchronous DRAM Bank Active Specifies whether synchronous DRAM is used in bank active mode or auto-precharge mode. When both areas 2 and 3 are to be connected to synchronous DRAM, select auto-precharge mode. 0: Auto-precharge mode 1: Bank active mode Rev. 4.00, 03/04, page 182 of 660 Bit 6 5 4 3 Bit Name AMX3 AMX2 AMX1 AMX0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Address Multiplex The AMX bits specify address multiplexing for synchronous DRAM. The actual address shift value differs between DRAM interface and synchronous DRAM interface. For Synchronous DRAM interface: 0000: Reserved (Setting prohibited) 0001: Reserved (Setting prohibited) 0010: Reserved (Setting prohibited) 0011: Reserved (Setting prohibited) 0100: The row address begins with A9. (The A9 value is output at A1 when the row address is output. 64 M (1 M x 16 bits x 4 banks)) 0101: The row address begins with A10. (The A10 value is output at A1 when the row address is output. 128 M (2 M x 16 bits x 4 banks), 64 M (2 M x 8 bits x 4 banks)) 0110: Cannot be set. 0111: The row address begins with A9. (The A9 value is output at A1 when the row address is output. 64 M (512 k x 32 bits x 4 2 banks)* ) 1000: Reserved (Setting prohibited) 1001: Reserved (Setting prohibited) 1010: Reserved (Setting prohibited) 1011: Reserved (Setting prohibited) 1100: Reserved (Setting prohibited) 1101: The row address begins with A10. (The A10 value is output at A1 when the row address is output. 256 M (4 M x 16 bits x 4 banks)) 1110: The row address begins with A11. (The A11 value is output at A1 when the row address 1 is output. 512 M (8 M x 16 bits x 4 banks)* ) 1111: Reserved (Setting prohibited) Notes: 1. Cannot be set when using a 32-bit bus width. 2. Cannot be set when using a 16-bit bus width. Rev. 4.00, 03/04, page 183 of 660 Bit 2 Bit Name RFSH Initial Value 0 R/W R/W Description Refresh Control The RFSH bit determines whether or not the refresh operation of the DRAM and synchronous DRAM is performed. The timer for generation of the refresh request frequency can also be used as an interval timer. 0: No refresh 1: Refresh 1 RMODE 0 R/W Refresh Mode The RMODE bit selects whether to perform an ordinary refresh or a self-refresh when the RFSH bit is 1. When the RFSH bit is 1 and this bit is 0, a CAS-before-RAS refresh or an auto-refresh is performed on synchronous DRAM at the period set by the refresh-related registers RTCNT, RTCOR and RTCSR. When a refresh request occurs during an external bus cycle, the bus cycle will be ended and the refresh cycle performed. When the RFSH bit is 1 and this bit is also 1, the synchronous DRAM will wait for the end of any executing external bus cycle before going into a self-refresh. All refresh requests to memory that is in the self-refresh state are ignored. 0: CAS-before-RAS refresh (RFSH must be 1) 1: Self-refresh (RFSH must be 1) 0 -- 0 R/W Reserved This bit is always read as 0. The write value should always be 0. Rev. 4.00, 03/04, page 184 of 660 8.4.6 PCMCIA Control Register (PCR) The PCMCIA control register (PCR) is a 16-bit read/write register that specifies the timing for the assertion or negation of the OE and WE signals for the PCMCIA interface connected to areas 5 and 6. The width for assertion of the OE and WE signals is set by the wait control bit in the WCR2 register. Bit* 15 Bit Name A6W3 Initial Value 0 R/W R/W Description Area 6 Wait Control The A6W3 bit specifies the number of inserted wait states for area 6 combined with bits A6W2 to A6W0 in WCR2. It also specifies the number of transfer states in burst transfer. Set this bit to 0 when area 6 is not set to PCMCIA. Refer to table 8.10 for details. 14 A5W3 0 R/W Area 5 Wait Control The A5W3 bit specifies the number of inserted wait states for area 5 combined with bits A5W2 to A5W0 in WCR2. It also specifies the number of transfer states in burst transfer. Set this bit to 0 when area 5 is not set to PCMCIA. The relationship between the setting value and the number of waits is the same as A6W3. 13, 12 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 7 6 A5TED2 A5TED1 A5TED0 0 0 0 R/W R/W R/W Area 5 Address OE/WE Assert Delay The A5TED bits specify the address to OE/WE assert delay time for the PCMCIA interface connected to area 5. 000: 0.5-cycle delay 001: 1.5-cycle delay 010: 2.5-cycle delay 011: 3.5-cycle delay 100: 4.5-cycle delay 101: 5.5-cycle delay 110: 6.5-cycle delay 111: 7.5-cycle delay Rev. 4.00, 03/04, page 185 of 660 Bit* 10 5 4 Bit Name A6TED2 A6TED1 A6TED0 Initial Value 0 0 0 R/W R/W R/W R/W Description Area 6 Address OE/WE Assert Delay The A6TED bits specify the address to OE/WE assert delay time for the PCMCIA interface connected to area 6. 000: 0.5-cycle delay 001: 1.5-cycle delay 010: 2.5-cycle delay 011: 3.5-cycle delay 100: 4.5-cycle delay 101: 5.5-cycle delay 110: 6.5-cycle delay 111: 7.5-cycle delay 9 3 2 A5TEH2 A5TEH1 A5TEH0 0 0 0 R/W R/W R/W Area 5 OE/WE Negate Address Delay The A5TEH bits specify the OE/WE negate address delay time for the PCMCIA interface connected to area 5. 000: 0.5-cycle delay 001: 1.5-cycle delay 010: 2.5-cycle delay 011: 3.5-cycle delay 100: 4.5-cycle delay 101: 5.5-cycle delay 110: 6.5-cycle delay 111: 7.5-cycle delay 8 1 0 A6TEH2 A6TEH1 A6TEH0 0 0 0 R/W R/W R/W Area 6 OE/WE Negate Address Delay The A6TEH bits specify the OE/WE negate address delay time for the PCMCIA interface connected to area 6. 000: 0.5-cycle delay 001: 1.5-cycle delay 010: 2.5-cycle delay 011: 3.5-cycle delay 100: 4.5-cycle delay 101: 5.5-cycle delay 110: 6.5-cycle delay 111: 7.5-cycle delay Note: * The bit numbers are out of sequence. Rev. 4.00, 03/04, page 186 of 660 Table 8.10 Area 6 Wait Control Description Top Cycle Inserted Wait State 0 1 2 3 4 6 8 10 12 14 18 22 26 30 34 38 Burst Cycle Number of States per One-data Transfer 2 2 3 4 5 7 9 11 13 15 19 23 27 31 35 39 WCR2 A6W3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 A6W2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A6W1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A6W0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 WAIT Pin Ignored Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled WAIT Pin Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Rev. 4.00, 03/04, page 187 of 660 8.4.7 Synchronous DRAM Mode Register (SDMR) The synchronous DRAM mode register (SDMR) is written to via the synchronous DRAM address bus and is an 8-bit write-only register. It sets synchronous DRAM mode for areas 2 and 3. SDMR must be set before synchronous DRAM is accessed. Writes to the synchronous DRAM mode register use the address bus rather than the data bus. If the value to be set is X and the SDMR address is Y, the value X is written in the synchronous DRAM mode register by writing in address X + Y. Since, with a 32-bit bus width, A0 of the synchronous DRAM is connected to A2 of the chip and A1 of the synchronous DRAM is connected to A3 of the chip, the value actually written to the synchronous DRAM is the X value shifted two bits right. With a 16-bit bus width, the value written is the X value shifted one bit right. For example, with a 32-bit bus width, when H'0230 is written to the SDMR register of area 2, random data is written to the address H'FFFFD000 (address Y) + H'08C0 (value X), or H'FFFFD8C0. As a result, H'0230 is written to the SDMR register. The range for value X is H'0000 to H'0FFC. When H'0230 is written to the SDMR register of area 3, random data is written to the address H'FFFFE000 (address Y) + H'08C0 (value X), or H'FFFFE8C0. As a result, H'0230 is written to the SDMR register. The range for value X is H'0000 to H'0FFC. 8.4.8 Refresh Timer Control/Status Register (RTCSR) The refresh timer control/status register (RTCSR) is a 16-bit read/write register that specifies the refresh cycle, whether to generate an interrupt, and that interrupt's cycle. It is initialized to H'0000 by a power-on reset, but is not initialized by a manual reset or standby mode and holds its values unchanged. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR. Note: Writing to the RTCSR differs from that to general registers to ensure the RTCSR is not rewritten incorrectly. Use the word-transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For the byte-transfer instruction, writing is disabled. Read data in 16 bits. 0 is read from undefined bits. Rev. 4.00, 03/04, page 188 of 660 Bit 15 to 8 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 CMF 0 R/W Compare Match Flag The CMF status flag indicates that the values of RTCNT and RTCOR match. 0: The values of RTCNT and RTCOR do not match. Clear condition: When a refresh is performed After 0 has been written in CMF and RFSH = 1 and RMODE = 0 (to perform a CBR refresh). 1: The values of RTCNT and RTCOR match. Set condition: RTCNT = RTCOR * Note: * Contents don't change when 1 is written to CMF. 6 CMIE 0 R/W Compare Match Interrupt Enable Enables or disables an interrupt request caused when the CMF of RTCSR is set to 1. Do not set this bit to 1 when using auto-refresh. 0: Disables an interrupt request caused by CMF 1: Enables an interrupt request caused by CMF 5 4 3 CKS2 CKS1 CKS0 0 0 0 R/W R/W R/W Clock Select Bits Select the clock input to RTCNT. The source clock is the external bus clock (CKIO). The RTCNT count clock is CKIO divided by the specified ratio. RTCOR should be set before setting CKS2 to CKS0. 000: Disables clock input 001: Bus clock (CKIO)/4 010: CKIO/16 011: CKIO/64 100: CKIO/256 101: CKIO/1024 110: CKIO/2048 111: CKIO/4096 Rev. 4.00, 03/04, page 189 of 660 Bit 2 Bit Name OVF Initial Value 0 R/W R/W Description Refresh Count Overflow Flag The OVF status flag indicates when the number of refresh requests indicated in the refresh count register (RFCR) exceeds the limit set in the LMTS bit of RTCSR. 0: RFCR has not exceeded the count limit value set in LMTS Clear Conditions: When 0 is written to OVF 1: RFCR has exceeded the count limit value set in LMTS Set Conditions: When the RFCR value has exceeded the count limit value set in LMTS* Note: * Contents don't change when 1 is written to OVF. 1 OVIE 0 R/W Refresh Count Overflow Interrupt Enable OVIE selects whether to suppress generation of interrupt requests by OVF when the OVF bit of RTCSR is set to 1. 0: Disables interrupt requests from the OVF 1: Enables interrupt requests from the OVF 0 LMTS 0 R/W Refresh Count Overflow Limit Select Indicates the count limit value to be compared to the number of refreshes indicated in the refresh count register (RFCR). When the value RFCR overflows the value specified by LMTS, the OVF flag is set. 0: Count limit value is 1024 1: Count limit value is 512 Rev. 4.00, 03/04, page 190 of 660 8.4.9 Refresh Timer Counter (RTCNT) RTCNT is a 16-bit read/write register. RTCNT is an 8-bit counter that counts up with input clocks. The clock select bits (CKS2 to CKS0) of RTCSR select the input clock. When RTCNT matches RTCOR, the CMF bit of RTCSR is set and RTCNT is cleared. RTCNT is initialized to H'00 by a power-on reset; it continues incrementing after a manual reset; it is not initialized by standby mode and holds its values unchanged. Note: Writing to the RTCNT differs from that to general registers to ensure the RTCNT is not rewritten incorrectly. Use the word-transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For the byte-transfer instruction, writing is disabled. Read data in 16 bits. 0 is read from undefined bits. Bit 15 to 8 7 to 0 Bit Name -- -- Initial Value All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. 8-bit counter 8.4.10 Refresh Time Constant Register (RTCOR) The refresh time constant register (RTCOR) is a 16-bit read/write register. The values of RTCOR and RTCNT (bottom 8 bits) are constantly compared. When the values match, the CMF of RTCSR is set and RTCNT is cleared to 0. When the refresh bit (RFSH) of the individual memory control register (MCR) is set to 1 and the refresh mode is set to auto refresh, a memory refresh cycle occurs when the CMF bit is set. RTCOR is initialized to H'00 by a power-on reset. It is not initialized by a manual reset or standby mode, but holds its contents. Make the RTCOR setting before setting bits CKS2 to CKS0 in RTCSR. Note: Writing to the RTCOR differs from that to general registers to ensure the RTCOR is not rewritten incorrectly. Use the word-transfer instruction to set the upper byte as B'10100101 and the lower byte as the write data. For the byte-transfer instruction, writing is disabled. Read data in 16 bits. 0 is read from undefined bits. Bit 15 to 8 7 to 0 Bit Name -- -- Initial Value All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. Upper limit of the counter (8 bits) Rev. 4.00, 03/04, page 191 of 660 8.4.11 Refresh Count Register (RFCR) The refresh count register (RFCR) is a 16-bit read/write register. It is a 10-bit counter that increments every time RTCOR and RTCNT match. When RFCR exceeds the count limit value set in the LMTS of RTCSR, RTCSR's OVF bit is set and RFCR clears. RFCR is initialized to H'0000 when a power-on reset is performed. It is not initialized by a manual reset or standby mode, but holds its contents. Note: Writing to the RFCR differs from that to general registers to ensure the RFCR is not rewritten incorrectly. Use the word-transfer instruction to set the MSB and followed six bits of upper bytes as B'101001 and remaining bits as the write data. For the byte-transfer instruction, writing is disabled. Read data in 16 bits. 0 is read from undefined bits. Bit 15 to 10 9 to 0 Bit Name -- -- Initial Value All 0 All 0 R/W R R/W Description Reserved These bits are always read as 0. 10-bit counter 8.5 8.5.1 Operation Endian/Access Size and Data Alignment This LSI supports both big endian, in which the 0 address is the most significant byte in the byte data, and little endian, in which the 0 address is the least significant byte. This switchover is designated by an external pin (MD5 pin) at the time of a power-on reset. After a power-on reset, big endian is engaged when MD5 is low; little endian is engaged when MD5 is high. Three data bus widths are available for ordinary memory (byte, word, longword) and two data bus widths (word and longword) for synchronous DRAM. For the PCMCIA interface, choose from byte and word. This means data alignment is done by matching the device's data width and endian. The access unit must also be matched to the device's bus width. This also means that when longword data is read from a byte-width device, the read operation must happen 4 times. In this LSI, data alignment and conversion of data length is performed automatically between the respective interfaces. Tables 8.11 through 8.16 show the relationship between endian, device data width, and access unit. Rev. 4.00, 03/04, page 192 of 660 Table 8.11 32-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D24 Data 7 to 0 -- -- -- Strobe Signals WE1, WE1 DQMLU WE0, WE0 DQMLL D23 to D15 to WE3, WE2, WE3 WE2 D16 D8 D7 to D0 DQMUU DQMUL -- Data 7 to 0 -- -- Data 7 to 0 -- -- -- Data 7 to 0 -- -- -- -- -- Data 7 to 0 -- Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Word access at 0 Data 15 to 8 Word access at 2 -- Data Data 15 to 8 7 to 0 Longword access Data Data Data Data at 0 31 to 24 23 to 16 15 to 8 7 to 0 Table 8.12 16-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 D31 to D23 to D15 to D24 D16 D8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 -- Data 7 to 0 -- Data 15 to 8 Data 15 to 8 WE3, WE3 D7 to D0 DQMUU -- Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU Assert Assert WE0, WE0 DQMLL Longword 1st -- access time at 0 at 0 2nd -- time at 2 Data Data 31 to 24 23 to 16 Data 15 to 8 Data 7 to 0 Rev. 4.00, 03/04, page 193 of 660 Table 8.13 8-Bit External Device/Big Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D23 to D15 to WE3, WE3 D24 D16 D8 D7 to D0 DQMUU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 31 to 24 Data 23 to 16 Data 15 to 8 Data 7 to 0 Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU WE0, WE0 DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Word 1st time -- access at 0 at 0 2nd time -- at 1 Word 1st time -- access at 2 at 2 2nd time -- at 3 Longword 1st time -- access at 0 at 0 2nd time -- at 1 3rd time -- at 2 4th time -- at 3 Rev. 4.00, 03/04, page 194 of 660 Table 8.14 32-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D24 -- -- -- Data 7 to 0 D23 to D16 -- -- Data 7 to 0 -- -- Data 7 to 0 Strobe Signals WE1, WE1 DQMLU WE0, WE0 DQMLL Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert D15 to WE3, WE2, WE3 WE2 D8 D7 to D0 DQMUU DQMUL -- Data 7 to 0 -- -- Data 7 to 0 -- -- -- Word access at 0 -- Word access at 2 Data 15 to 8 Data Data 15 to 8 7 to 0 -- -- Longword access Data Data Data Data at 0 31 to 24 23 to 16 15 to 8 7 to 0 Table 8.15 16-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 Word access at 0 Word access at 2 D31 to D23 to D15 to D24 D16 D8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 -- Data 7 to 0 Data 15 to 8 Data 15 to 8 Data 15 to 8 WE3, WE3 D7 to D0 DQMUU Data 7 to 0 -- Data 7 to 0 -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Assert Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU WE0, WE0 DQMLL Assert Longword 1st -- access time at 0 at 0 2nd -- time at 2 Data Data 31 to 24 23 to 16 Rev. 4.00, 03/04, page 195 of 660 Table 8.16 8-Bit External Device/Little Endian Access and Data Alignment Data Bus Operation Byte access at 0 Byte access at 1 Byte access at 2 Byte access at 3 D31 to D23 to D15 to WE3, WE3 D24 D16 D8 D7 to D0 DQMUU -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 7 to 0 Data 15 to 8 Data 23 to 16 Data 31 to 24 Strobe Signals WE2, WE2 DQMUL WE1, WE1 DQMLU WE0, WE0 DQMLL Assert Assert Assert Assert Assert Assert Word 1st time -- access at 0 at 0 2nd -- time at 1 Word 1st time -- access at 2 at 2 2nd -- time at 3 Longword 1st time -- access at 0 at 0 2nd -- time at 1 3rd time -- at 2 4th time -- at 3 -- -- -- -- Assert Assert -- -- -- -- Assert Assert -- -- -- -- Assert Assert Rev. 4.00, 03/04, page 196 of 660 8.5.2 Description of Areas Area 0: Area 0 physical addresses A28 to A26 are 000. Addresses A31 to A29 are ignored and the address range is H'00000000 + H'20000000 x n - H'03FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories such as SRAM, ROM, and burst ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using external pins MD3 and MD4. When the area 0 space is accessed, a CS0 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A0W2 to A0W0 bits of WCR2. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When the burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 10 according to the number of waits. Area 1: Area 1 physical addresses A28 to A26 are 001. Addresses A31 to A29 are ignored and the address range is H'04000000 + H'20000000 x n to H'07FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Area 1 is the area specifically for the internal peripheral modules. The external memories cannot be connected. Control registers of peripheral modules shown below are mapped to this area 1. Their addresses are physical address, to which logical addresses can be mapped with the MMU enabled: DMAC, PORT, SCIF, ADC, DAC, INTC (except INTEVT, IPRA, IPRB) Those registers must be set not to be cached. Area 2: Area 2 physical addresses A28 to A26 are 010. Addresses A31 to A29 are ignored and the address range is H'08000000 + H'20000000 x n to H'0BFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to this space. Byte, word, or longword can be selected as the bus width using the A2SZ1 to A2SZ0 bits of BCR2 for ordinary memory. When the area 2 space is accessed, a CS2 signal is asserted. When ordinary memories are connected, an RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the A2W1 to A2W0 bits of WCR2. When synchronous DRAM is connected, the RASU, RASL signal, CASU, CASL signal, RD/WR signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of RASU, RASL, CASU, CASL, data timing, and address multiplexing is set with MCR. Rev. 4.00, 03/04, page 197 of 660 Area 3: Area 3 physical addresses A28 to A26 are 011. Addresses A31 to A29 are ignored and the address range is H'0C000000 + H'20000000 x n to H'0FFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM, as well as synchronous DRAM, can be connected to this space. Byte, word or longword can be selected as the bus width using the A3SZ1 to A3SZ0 bits of BCR2 for ordinary memory. When area 3 space is accessed, CS3 is asserted. When ordinary memories are connected, an RD signal that can be used as OE and the WE0 to WE3 signals for write control are asserted and the number of bus cycles is selected between 0 and 3 wait cycles using the A3W1 to A3W0 bits of WCR2. When synchronous DRAM is connected, the RASU, RASL signal, CASU, CASL signal, RD/WR signal, and byte controls DQMHH, DQMHL, DQMLH, and DQMLL are all asserted and addresses multiplexed. Control of RAS, CAS, and data timing and of address multiplexing is set with MCR. Area 4: Area 4 physical addresses A28 to A26 are 100. Addresses A31 to A29 are ignored and the address range is H'10000000 + H'20000000 x n to H'13FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Only ordinary memories like SRAM and ROM can be connected to this space. Byte, word, or longword can be selected as the bus width using the A4SZ1 to A4SZ0 bits of BCR2. When the area 4 space is accessed, a CS4 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A4W2 to A4W0 bits of WCR2. Area 5: Area 5 physical addresses A28 to A26 are 101. Addresses A31 to A29 are ignored and the address range is the 64 Mbytes at H'14000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. When the PCMCIA interface is used, the IC memory card interface address range comprises the 32 Mbytes at H'14000000 + H'20000000 x n to H'15FFFFFF + H'20000000 x n (where n = 0 to 6, and n = 1 to 6 represents shadow space), and the I/O card interface address range comprises the 32 Mbytes at H'16000000 + H'20000000 x n to H'17FFFFFF + H'20000000 x n (where n = 0 to 6, and n = 1 to 6 represents shadow space). For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width using the A5SZ1 to A5SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be selected as the bus width using the A5SZ1 to A5SZ0 bits of BCR2. Rev. 4.00, 03/04, page 198 of 660 When the area 5 space is accessed and ordinary memory is connected, a CS5 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1A signal, CE2A signal, RD signal as OE signal, and WE1, ICIORD, and ICIOWR signals are asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A5W2 to A5W0 bits of WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A5W2 to A5W0 bits of WCR2 and the A5W3 bit of PCR. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). When a burst function is used, the bus cycle pitch of the burst cycle is determined within a range of 2 to 11 (2 to 39 for the PCMCIA interface) according to the number of waits. The setup and hold times of address/CS5 for the read/write strobe signals can be set in the range 0.5 to 7.5 using A5TED2 to A5TED0 and A5TEH2 to A5TEH0 bits of the PCR register. Area 6: Area 6 physical addresses A28 to A26 are 110. Addresses A31 to A29 are ignored and the address range is the 64 Mbytes at H'18000000 + H'20000000 x n - H'1BFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). Ordinary memories like SRAM and ROM as well as burst ROM and PCMCIA interfaces can be connected to this space. When the PCMCIA interface is used, the IC memory card interface address range is 32 Mbytes at H'18000000 + H'20000000 x n - H'19FFFFFF + H'20000000 x n and the I/O card interface address range is 32 Mbytes at H'1A000000 + H'20000000 x n - H'1BFFFFFF + H'20000000 x n (n = 0 to 6 and n = 1 to 6 are the shadow spaces). For ordinary memory and burst ROM, byte, word, or longword can be selected as the bus width using the A6SZ1 to A6SZ0 bits of BCR2. For the PCMCIA interface, byte, and word can be selected as the bus width using the A6SZ1 to A6SZ0 bits of BCR2. When the area 6 space is accessed and ordinary memory is connected, a CS6 signal is asserted. An RD signal that can be used as OE and the WE0 to WE3 signals for write control are also asserted. When the PCMCIA interface is used, the CE1B signal, CE2B signal, RD signal as OE signal, and WE, ICIORD, and ICIOWR signals are asserted. The number of bus cycles is selected between 0 and 10 wait cycles using the A6W2 to A6W0 bits of WCR2. With the PCMCIA interface, from 0 to 38 wait cycles can be selected using the A6W2 to A6W0 bits of WCR2 and the A6W3 bit of PCR. In addition, any number of waits can be inserted in each bus cycle by means of the external wait pin (WAIT). The bus cycle pitch of the burst cycle is determined within a range of 2 to 11 (2 to 39 for the PCMCIA interface) according to the number of waits. The setup and hold times of address/CS6 for the read/write strobe signals can be set in the range 0.5 to 7.5 using A6TED2 to A6TED0 and A6TEH2 to A6TEH0 bits of the PCR register. Rev. 4.00, 03/04, page 199 of 660 8.5.3 Basic Interface Basic Timing: The basic interface of this LSI uses strobe signal output in consideration of the fact that mainly static RAM will be directly connected. Figure 8.5 shows the basic timing of normal space accesses. A no-wait normal access is completed in two cycles. The BS signal is asserted for one cycle to indicate the start of a bus cycle. The CSn signal is negated on the T2 clock falling edge to secure the negation period. Therefore, in case of access at minimum pitch, there is a halfcycle negation period. There is no access size specification when reading. The correct access start address is output in the least significant bit of the address, but since there is no access size specification, 32 bits are always read in case of a 32-bit device, and 16 bits in case of a 16-bit device. When writing, only the WE signal for the byte to be written is asserted. For details, see section 8.5.1, Endian/Access Size and Data Alignment. Read/write for cache fill or write-back follows the set bus width and transfers a total of 16 bytes continuously. The bus is not released during this transfer. For cache misses that occur during byte or word operand accesses or branching to odd word boundaries, the fill is always performed by longword accesses on the chip-external interface. Write-through-area write access and noncacheable read/write access are based on the actual address size. T1 T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS Figure 8.5 Basic Timing of Basic Interface Rev. 4.00, 03/04, page 200 of 660 Figures 8.6, 8.7, and 8.8 show examples of connection to 32, 16, and 8-bit data-width static RAM, respectively. 128k x 8-bit SRAM **** **** **** **** **** **** **** **** **** **** **** This LSI A18 A2 CSn RD D31 **** A16 A0 CS OE I/O7 D24 WE3 D23 **** **** I/O0 WE **** D16 WE2 D15 **** **** A16 A0 CS OE I/O7 I/O0 WE **** D0 WE0 **** **** D8 WE1 D7 **** **** A16 A0 CS OE I/O7 I/O0 WE **** A16 A0 CS OE I/O7 I/O0 WE Figure 8.6 Example of 32-Bit Data-Width Static RAM Connection Rev. 4.00, 03/04, page 201 of 660 **** This LSI **** **** **** **** **** **** **** 128k x 8-bit SRAM **** **** **** **** A17 A1 CSn RD D15 **** A16 A0 CS OE I/O7 D8 WE1 D7 **** **** I/O0 WE **** D0 WE0 A16 A0 CS OE I/O7 I/O0 WE Figure 8.7 Example of 16-Bit Data-Width Static RAM Connection 128k x 8-bit SRAM **** **** **** **** This LSI A16 A0 CSn RD D7 **** A16 A0 CS OE I/O7 I/O0 WE D0 WE0 Figure 8.8 Example of 8-Bit Data-Width Static RAM Connection Rev. 4.00, 03/04, page 202 of 660 **** Wait State Control: Wait state insertion on the basic interface can be controlled by the WCR2 settings. If the WCR2 wait specification bits corresponding to a particular area are not zero, a software wait is inserted in accordance with that specification. For details, see section 8.4.4, Wait State Control Register 2 (WCR2) The specified number of Tw cycles are inserted as wait cycles using the basic interface wait timing shown in figure 8.9. T1 Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 BS Figure 8.9 Basic Interface Wait Timing (Software Wait Only) When software wait insertion is specified by WCR2, the external wait input WAIT signal is also sampled. WAIT pin sampling is shown in figure 8.10. A 2-cycle wait is specified as a software wait. Sampling is performed at the transition from the Tw state to the T2 state; therefore, if the WAIT signal has no effect if asserted in the T1 cycle or the first Tw cycle. When the WAITSEL bit in the WCR1 register is set to 1, the WAIT signal is sampled at the falling edge of the clock. If the setup time and hold times with respect to the falling edge of the clock are not satisfied, the value sampled at the next falling edge is used. Rev. 4.00, 03/04, page 203 of 660 However, the WAIT signal is ignored in the following cases: * In 16-byte DMA transfer or dual addressing mode, or when writing data to the external address area * In 16-byte DMA transfer or single addressing mode, or when transferring data from an external device with DACK to the external address area * When accessing cache for write back Wait states inserted by WAIT signal T1 Tw Tw Tw T2 CKIO A25 to A0 CSn RD/WR RD Read D31 to D0 WEn Write D31 to D0 WAIT BS Figure 8.10 Basic Interface Wait State Timing (Wait State Insertion by WAIT Signal WAITSEL = 1) Rev. 4.00, 03/04, page 204 of 660 8.5.4 Synchronous DRAM Interface * Synchronous DRAM Direct Connection Since synchronous DRAM can be selected by the CS signal, physical space areas 2 and 3 can be connected using RAS and other control signals in common. If the memory type bits (DRAMTP2 to 0) in BCR1 are set to 010, area 2 is ordinary memory space and area 3 is synchronous DRAM space; if set to 011, areas 2 and 3 are both synchronous DRAM space. However, do not access to the synchronous DRAM when clock ratio is Io:Bo = 1:1. With this LSI, burst length 1 burst read/single write mode is supported as the synchronous DRAM operating mode. A data bus width of 16 or 32 bits can be selected. A 16-byte burst transfer is performed in a cache fill/write-back cycle, and only one access is performed in a write-through area write or a non-cacheable area read/write. The control signals for direct connection of synchronous DRAM are RASL, RASU, CASL, CASU, RD/WR, CS2 or CS3, DQMUU, DQMUL, DQMLU, DQMLL, and CKE. All the signals other than CS2 and CS3 are common to all areas, and signals other than CKE are valid and fetched to the synchronous DRAM only when CS2 or CS3 is asserted. Synchronous DRAM can therefore be connected in parallel to a number of areas. CKE is negated (low) only when self-refreshing is performed, and is always asserted (high) at other times. In the refresh cycle and mode-register write cycle, RASU and RASL or CASU and CASL are output. Commands for synchronous DRAM are specified by RASL, RASU, CASL, CASU, RD/WR, and special address signals. The commands are NOP, auto-refresh (REF), self-refresh (SELF), precharge all banks (PALL), row address strobe bank active (ACTV), read (READ), read with precharge (READA), write (WRIT), write with precharge (WRITA), and mode register write (MRS). Byte specification is performed by DQMUU, DQMUL, DQMLU, and DQMLL. A read/write is performed for the byte for which the corresponding DQM is low. In big-endian mode, DQMUU specifies an access to address 4n, and DQMLL specifies an access to address 4n + 3. In littleendian mode, DQMUU specifies an access to address 4n + 3, and DQMLL specifies an access to address 4n. Figures 8.11 shows examples of the connection of two 1M x 16-bit x 4-bank synchronous DRAMs and figure 8.12 shows one 1M x 16-bit x 4-bank synchronous DRAM, respectively. Rev. 4.00, 03/04, page 205 of 660 This LSI A15 A14 A13 **** **** 64M synchronous DRAM (1M x 16-bit x 4-bank) A13 A12 A11 **** **** A2 CKIO CKE A0 CLK CKE RD/ D31 **** DQ15 DQ0 **** D16 D15 **** **** D0 **** A13 A12 A11 A0 CLK CKE **** DQ15 **** DQ0 Note : "x" is U or L Figure 8.11 Example of 64-Mbit Synchronous DRAM Connection (32-Bit Bus Width) Rev. 4.00, 03/04, page 206 of 660 **** This LSI A14 A13 A12 *** *** *** 64M synchronous DRAM 1M x 16-bit x 4-bank A13 A12 A11 A0 CLK CKE *** A1 CKIO CKE RD/ D15 *** *** *** DQ15 DQ0 *** D0 Figure 8.12 Example of 64-Mbit Synchronous DRAM (16-Bit Bus Width) * Address Multiplexing Synchronous DRAM can be connected without external multiplexing circuitry in accordance with the address multiplex specification bits AMX3-AMX0 in MCR. Table 8.17 shows the relationship between the address multiplex specification bits and the bits output at the address pins. A25 to A17 and A0 are not multiplexed; the original values are always output at these pins. When A0, the LSB of the synchronous DRAM address, is connected to this LSI, it performs longword address specification. Connection should therefore be made in the following order: connect pin A0 of the synchronous DRAM to pin A2 of this LSI, then connect pin A1 to pin A3. Table 8.18 shows an example of the connection of address pins when AMX[3:0] = 0100 with 32bit bus width. Rev. 4.00, 03/04, page 207 of 660 Table 8.17 Relationship between Bus Width, AMX, and Address Multiplex Output Bus Memory Setting Output A1 to A8 A1 to A8 A9 A9 A10 A10 A19 A10 A19 A10 A18 A10 A19 A10 A18 A10 A20 A10 A19 A10 A19 A10 A18 A10 A19 External Address Pins A11 A11 A20 A11 A20 A11 A19 A11 A20 A11 A19 L/H*3 A21 L/H* A20 L/H* A20 L/H*3 A19 L/H*3 A20 3 3 Width Type 32 bits 4M x 16 bits x 1 4 banks* AMX3 AMX2 AMX1 AMX0 Timing 1 1 0 1 Column address Row address 0 1 0 1 Column address Row address 0 1 0 0 Column address Row address 0 1 0 1 Column address Row address 0 1 1 1 Column address Row address 1 1 1 0 Column address Row address 1 2 A12 L/H* A21 L/H* A21 L/H*3 A20 L/H* A21 L/H*3 A20 A12 A22 A12 A21 A12 A21 A12 A20 A12 A21 3 3 3 A13 A13 A22 A13 A22 A13 A21 A13 A22 A21*4 A21* A23 A23 A22 A22 A22* A22* 4 4 A14 A23 A23 A23* A23* 4 A15 A24* A24 A24* 4 4 A16 A25* 4 A10 to A17 A18 A1 to A8 A9 A25*4 2M x 16 bits x 2 4 banks* A10 to A17 A18 A1 to A8 A9 to A16 A1 to A8 A9 A17 A9 4 A24*4 A23*4 A23*4 A24* 4 1M x 16 bits x 2 4 banks* A22*4 A22*4 A23* A23* 4 2M x 8 bits x 2 4 banks* A10 to A17 A18 A1 to A8 A9 to A16 A1 to A8 A9 A17 A9 4 A24*4 A15 A23 A25*4 A25* A24* 4 512k x 32 bits x 2 4 banks* A22*4 A22* 4 16 bits 8M x 16 bits x 1 4 banks* A24*4 A24* A23* A23* 4 A11 to A18 A19 A1 to A8 A9 4M x 16 bits x 4 banks* 1 0 1 Column address Row address 4 4 A10 to A17 A18 A1 to A8 A9 4 A24*4 A24 A24 A15 A23 A24 A24 2M x 16 bits x 2 4 banks* 0 1 0 1 Column address Row address A23* 4 A10 to A17 A18 A1 to A8 A9 to A16 A1 to A8 A9 A17 A9 4 A23*4 A22*4 A22*4 A23*4 A23* 4 1M x 16 bits x 2 4 banks* 0 1 0 0 Column address Row address A21*4 A21*4 A22*4 A22* 4 2M x 8 bits x 4 banks*2 0 1 0 1 Column address Row address A10 to A17 A18 Notes: 1. Only RASL/CASL are output. 2. RASU and CASU are output for upper 32-Mbyte addresses, and RASL and CASL for lower 32-Mbyte addresses. 3. L/H is a bit used in the command specification; it is fixed at L or H according to the access mode. 4. Bank address specification Rev. 4.00, 03/04, page 208 of 660 Table 8.18 Example of Correspondence between this LSI and Synchronous DRAM Address Pins (AMX (3 to 0) = 0100 (32-Bit Bus Width)) Address Pin of this LSI RAS Cycle A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A23 A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 CAS Cycle A23 A22 A13 L/H A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 A13(BA1) A12(BA0) A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Not used Not used Address Address/precharge setting Address Synchronous DRAM Address Pin Function BANK select address * Burst Read Figure 8.13 shows the timing chart for a burst read. In the example below, it is assumed that four 2M x 8-bit synchronous DRAMs are connected and a 32-bit data width is used, and the burst length is 1. Following the Tr cycle in which ACTV command output is performed, a READ command is issued in the Tc1, Tc2, and Tc3 cycles, and a READA command in the Tc4 cycle, and the read data is accepted on the rising edge of the external command clock (CKIO) from cycle Td1 to cycle Td4. The Tpc cycle is used to wait for completion of auto-precharge based on the READA command inside the synchronous DRAM; no new access command can be issued to the same bank during this cycle, but access to synchronous DRAM for another area is possible. In the this LSI, the number of Tpc cycles is determined by the TPC bit specification in MCR, and commands cannot be issued for the same synchronous DRAM during this interval. Rev. 4.00, 03/04, page 209 of 660 The example in figure 8.13 shows the basic timing. To connect low-speed synchronous DRAM, the cycle can be extended by setting WCR2 and MCR bits. The number of cycles from the ACTV command output cycle, Tr, to the READ command output cycle, Tc1, can be specified by the RCD bit in MCR, with a values of 0 to 3 specifying 1 to 4 cycles, respectively. In case of 2 or more cycles, a Trw cycle, in which an NOP command is issued for the synchronous DRAM, is inserted between the Tr cycle and the Tc cycle. The number of cycles from READ and READA command output cycles Tc1-Tc4 to the first read data latch cycle, Td1, can be specified as 1 to 3 cycles independently for areas 2 and 3 by means of A2W1 and A2W0 or A3W1 and A3W0 in WCR2. This number of cycles corresponds to the number of synchronous DRAM CAS latency cycles. Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 Tpc CKIO Address upper bits A12 or A11 *1 Address lower bits *2 or RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.13 Basic Timing for Synchronous DRAM Burst Read Rev. 4.00, 03/04, page 210 of 660 Figure 8.14 shows the burst read timing when RCD is set to 1, A3W1 and A3W0 are set to 10, and TPC is set to 1. The BS cycle, which is asserted for one cycle at the start of a bus cycle for normal space access, is asserted in each of cycles Td1 to Td4 in a synchronous DRAM cycle. When a burst read is performed, the address is updated each time CAS is asserted. As the unit of burst transfer is 16 bytes, address updating is performed for A3 and A2 only (A3, A2, and A1 for a 16-bit bus width). The order of access is as follows: in a fill operation in the event of a cache miss, the missed data is read first, then 16-byte boundary data including the missed data is read in wraparound mode. Tr CKIO Address upper bits A12 or A11 *1 Address lower bits *2 or Trw Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 Tpc RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.14 Synchronous DRAM Burst Read Wait Specification Timing Rev. 4.00, 03/04, page 211 of 660 * Single Read Figure 8.15 shows the timing when a single address read is performed. As the burst length is set to 1 in synchronous DRAM burst read/single write mode, only the required data is output. Consequently, no unnecessary bus cycles are generated even when a cache-through area is accessed. Tr CKIO Tc1 Td1 Tpc Address upper bits A12 or A11 *1 Address lower bits *2 or RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.15 Basic Timing for Synchronous DRAM Single Read Rev. 4.00, 03/04, page 212 of 660 * Burst Write The timing chart for a burst write is shown in figure 8.16. In this LSI, a burst write occurs only in the event of cache write-back or 16-byte transfer by DMAC. In a burst write operation, following the Tr cycle in which ACTV command output is performed, a WRIT command is issued in the Tc1, Tc2, and Tc3 cycles, and a WRITA command that performs auto-precharge is issued in the Tc4 cycle. In the write cycle, the write data is output at the same time as the write command. In case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR. Tr CKIO Tc1 Tc2 Tc3 Tc4 (Trw1) (Tpc) Address upper bits A12 or A11 *1 Address lower bits *2 RD/ D31 to D0 (read) Notes: 1. Command bit 2. Column address Figure 8.16 Basic Timing for Synchronous DRAM Burst Write Rev. 4.00, 03/04, page 213 of 660 * Single Write The basic timing chart for write access is shown in figure 8.17. In a single write operation, following the Tr cycle in which ACTV command output is performed, a WRITA command that performs auto-precharge is issued in the Tc1 cycle. In the write cycle, the write data is output at the same time as the write command. In case of the write with auto-precharge command, precharging of the relevant bank is performed in the synchronous DRAM after completion of the write command, and therefore no command can be issued for the same bank until precharging is completed. Consequently, in addition to the precharge wait cycle, Tpc, used in a read access, cycle Trwl is also added as a wait interval until precharging is started following the write command. Issuance of a new command for the same bank is postponed during this interval. The number of Trwl cycles can be specified by the TRWL bit in MCR. Tr CKIO Tc1 (Trwl) (Tpc) Address upper bits A12 or A11 *1 Address lower bits *2 RD/ D31 to D0 CKE Notes: 1. Command bit 2. Column address Figure 8.17 Basic Timing for Synchronous DRAM Single Write Rev. 4.00, 03/04, page 214 of 660 * Bank Active The synchronous DRAM bank function is used to support high-speed accesses to the same row address. When the RASD bit in MCR is 1, read/write command accesses are performed using commands without auto-precharge (READ, WRIT). In this case, precharging is not performed when the access ends. When accessing the same row address in the same bank, it is possible to issue the READ or WRIT command immediately, without issuing an ACTV command. As synchronous DRAM is internally divided into two or four banks, it is possible to activate one row address in each bank. If the next access is to a different row address, a PRE command is first issued to precharge the relevant bank, then when precharging is completed, the access is performed by issuing an ACTV command followed by a READ or WRIT command. If this is followed by an access to a different row address, the access time will be longer because of the precharging performed after the access request is issued. In a write, when auto-precharge is performed, a command cannot be issued for a period of Trwl + Tpc cycles after issuance of the WRITA command. When bank active mode is used, READ or WRIT commands can be issued successively if the row address is the same. The number of cycles can thus be reduced by Trwl + Tpc cycles for each write. The number of cycles between issuance of the precharge command and the row address strobe command is determined by the TPC bit in MCR. Whether faster execution speed is achieved by use of bank active mode or by use of basic access is determined by the probability of accessing the same row address (P1), and the average number of cycles from completion of one access to the next access (Ta). If Ta is greater than Tpc, the delay due to the precharge wait when reading is imperceptible. If Ta is greater than Trw1 + Tpc, the delay due to the precharge wait when writing is imperceptible. In this case, the access speed for bank active mode and basic access is determined by the number of cycles from the start of access to issuance of the read/write command: (Tpc + Trcd) x (1 - P1) and Trcd, respectively. There is a limit on Tras, the time for placing each bank in the active state. If there is no guarantee that there will not be a cache hit and another row address will be accessed within the period in which this value is maintained by program execution, it is necessary to set auto-refresh and set the refresh cycle to no more than the maximum value of Tras. In this way, it is possible to observe the restrictions on the maximum active state time for each bank. If auto-refresh is not used, measures must be taken in the program to ensure that the banks do not remain active for longer than the prescribed time. A burst read cycle without auto-precharge is shown in figure 8.18, a burst read cycle for the same row address in figure 8.19, and a burst read cycle for different row addresses in figure 8.20. Similarly, a burst write cycle without auto-precharge is shown in figure 8.21, a burst write cycle for the same row address in figure 8.22, and a burst write cycle for different row addresses in figure 8.23. Rev. 4.00, 03/04, page 215 of 660 A Tnop cycle, in which no operation is performed, is inserted before the Tc1 cycle in which the READ command is issued in figure 8.19, but when synchronous DRAM is read, there is a twocycle latency for the DQMxx signal that performs the byte specification. If the Tc1 cycle were performed immediately, without inserting a Tnop cycle, it would not be possible to perform the DQMxx signal specification for Td1 cycle data output. This is the reason for inserting the Tnop cycle. If the CAS latency is two cycles or longer, Tnop cycle insertion is not performed, since the timing requirements will be met even if the DQMxx signal is set after the Tc1 cycle. When bank active mode is set, if only accesses to the respective banks in the area 3 space are considered, as long as accesses to the same row address continue, the operation starts with the cycle in figure 8.18 or 8.21, followed by repetition of the cycle in figure 8.19 or 8.22. An access to a different area 3 space during this time has no effect. If there is an access to a different row address in the bank active state, after this is detected the bus cycle in figure 8.19 or 8.22 is executed instead of that in figure 8.19 or 8.22. In bank active mode, too, all banks become inactive after a refresh cycle or after the bus is released as the result of bus arbitration. Tr CKIO Address upper bits A12 or A11 *1 Address lower bits *2 or Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.18 Burst Read Timing (No Precharge) Rev. 4.00, 03/04, page 216 of 660 Tnop CKIO Address upper bits A12 or A11 *1 Address lower bits *2 or Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.19 Burst Read Timing (Same Row Address) Rev. 4.00, 03/04, page 217 of 660 Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO Address upper bits A12 or A11 *1 Address lower bits *2 or RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.20 Burst Read Timing (Different Row Addresses) Rev. 4.00, 03/04, page 218 of 660 Tr CKIO Tc1 Tc2 Tc3 Tc4 Address upper bits A12 or A11 *1 Address lower bits *2 or RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.21 Burst Write Timing (No Precharge) Rev. 4.00, 03/04, page 219 of 660 Tc1 CKIO Tc2 Tc3 Tc4 Address upper bits A12 or A11 *1 Address lower bits *2 or RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.22 Burst Write Timing (Same Row Address) Rev. 4.00, 03/04, page 220 of 660 Tp Tr Tc1 Tc2 Tc3 Td4 CKIO Address upper bits A12 or A11 *1 Address lower bits *2 or RD/ D31 to D0 Notes: 1. Command bit 2. Column address Figure 8.23 Burst Write Timing (Different Row Addresses) * Refreshing The bus state controller is provided with a function for controlling synchronous DRAM refreshing. Auto-refreshing can be performed by clearing the RMODE bit to 0 and setting the RFSH bit to 1 in MCR. If synchronous DRAM is not accessed for a long period, self-refresh mode, in which the power consumption for data retention is low, can be activated by setting both the RMODE bit and the RFSH bit to 1. Rev. 4.00, 03/04, page 221 of 660 1. Auto-Refreshing Figure 8.24 shows the auto-refreshing operation. Refreshing is performed at intervals determined by the input clock selected by bits CKS2 to 0 in RTCSR, and the value set in RTCOR. The value of bits CKS2 to 0 in RTCOR should be set so as to satisfy the refresh interval stipulation for the synchronous DRAM used. First make the settings for RTCOR, RTCNT, and the RMODE and RFSH bits in MCR, then make the CKS2 to CKS0 setting. When the clock is selected by CKS2 to CKS0, RTCNT starts counting up from the value at that time. The RTCNT value is constantly compared with the RTCOR value, and if the two values are the same, a refresh request is generated and an auto-refresh is performed. At the same time, RTCNT is cleared to zero and the count-up is restarted. Figure 8.25 shows the auto-refresh cycle timing. All-bank precharging is performed in the Tp cycle, then an REF command is issued in the TRr cycle following the interval specified by the TPC bits in MCR. After the TRr cycle, new command output cannot be performed for the duration of the number of cycles specified by the TRAS bits in MCR plus the number of cycles specified by the TPC bits in MCR. The TRAS and TPC bits must be set so as to satisfy the synchronous DRAM refresh cycle time stipulation (active/active command delay time). Auto-refreshing is performed in normal operation, in sleep mode, and in case of a manual reset. RTCOR value RTCNT RTCNT cleared to 0 when RTCNT = RTCOR H'00000000 Time RTCSR.CKS(2 to 0) = 000 000 CMF CMF flag cleared by start of refresh cycle External bus Auto-refresh cycle Figure 8.24 Auto-Refresh Operation Rev. 4.00, 03/04, page 222 of 660 Tp TRr TRrw TRrw (Tpc) CKIO CKE , , RD/ Figure 8.25 Synchronous DRAM Auto-Refresh Timing 2. Self-Refreshing Self-refresh mode is a kind of standby mode in which the refresh timing and refresh addresses are generated within the synchronous DRAM. Self-refreshing is activated by setting both the RMODE bit and the RFSH bit to 1. The self-refresh state is maintained while the CKE signal is low. Synchronous DRAM cannot be accessed while in the self-refresh state. Self-refresh mode is cleared by clearing the RMODE bit to 0. After self-refresh mode has been cleared, command issuance is disabled for the number of cycles specified by the TPC bits in MCR. Self-refresh timing is shown in figure 8.26. Settings must be made so that self-refresh clearing and data retention are performed correctly, and auto-refreshing is performed at the correct intervals. When self-refreshing is activated from the state in which auto-refreshing is set, or when exiting standby mode other than through a power-on reset, auto-refreshing is restarted if RFSH is set to 1 and RMODE is cleared to 0 when self-refresh mode is cleared. If the transition from clearing of self-refresh mode to the start of auto-refreshing takes time, this time should be taken into consideration when setting the initial value of RTCNT. Making the RTCNT value 1 less than the RTCOR value will enable refreshing to be started immediately. After self-refreshing has been set, the self-refresh state continues even if the chip standby state is entered using the this LSI standby function, and is maintained even after recovery from standby mode other than through a power-on reset. In case of a power-on reset, the bus state controller's registers are initialized, and therefore the self-refresh state is cleared. Self-refreshing is performed in normal operation, in sleep mode, in standby mode, and in case of a manual reset. Rev. 4.00, 03/04, page 223 of 660 When using synchronous DRAM, use the following procedure to initiate self-refreshing. 1. 2. 3. Clear the refresh control bit to 0. Write H'00 to the RTCNT register. Set the refresh control bit and refresh mode bit to 1. Tp CKIO TRs1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) CKE , , RD/ Figure 8.26 Synchronous DRAM Self-Refresh Timing 3. Relationship between Refresh Requests and Bus Cycle Requests If a refresh request is generated during execution of a bus cycle, execution of the refresh is deferred until the bus cycle is completed. If a refresh request occurs when the bus has been released by the bus arbiter, refresh execution is deferred until the bus is acquired. If a match between RTCNT and RTCOR occurs while a refresh is waiting to be executed, so that a new refresh request is generated, the previous refresh request is eliminated. In order for refreshing to be performed normally, care must be taken to ensure that no bus cycle or bus mastership occurs that is longer than the refresh interval. When a refresh request is generated, the IRQOUT pin is asserted (driven low). Therefore, normal refreshing can be performed by having the IRQOUT pin monitored by a bus master other than this LSI requesting the bus, or the bus arbiter, and returning the bus to this LSI. When refreshing is started, and if no other interrupt request has been generated, the IRQOUT pin is negated (driven high). Rev. 4.00, 03/04, page 224 of 660 * Power-On Sequence In order to use synchronous DRAM, mode setting must first be performed after powering on. To perform synchronous DRAM initialization correctly, the bus state controller registers must first be set, followed by a write to the synchronous DRAM mode register. In synchronous DRAM mode register setting, the address signal value at that time is latched by a combination of the RAS, CAS, and RD/WR signals. If the value to be set is X, the bus state controller provides for value X to be written to the synchronous DRAM mode register by performing a write to address H'FFFFD000 + X for area 2 synchronous DRAM, and to address H'FFFFE000 + X for area 3 synchronous DRAM. In this operation the data is ignored, but the mode write is performed as a byte-size access. To set burst read/single write, CAS latency 1 to 3, wrap type = sequential, and burst length 1 supported by this LSI, arbitrary data is written in a byte-size access to the following addresses. Area 2 FFFFD840 FFFFD880 FFFFD8C0 Area 2 FFFFD420 FFFFD440 FFFFD460 Area 3 FFFFE840 FFFFE880 FFFFE8C0 Area 3 FFFFE420 FFFFE440 FFFFE460 32-bit Bus width CAS latency 1 CAS latency 2 CAS latency 3 16-bit Bus width CAS latency 1 CAS latency 2 CAS latency 3 Mode register setting timing is shown in figure 8.27. As a result of the write to address H'FFFFD000 + X or H'FFFFE000 + X, a precharge all banks (PALL) command is first issued in the TRp1 cycle, then a mode register write command is issued in the TMw1 cycle. Address signals, when the mode-register write command is issued, are as follows: 32-bit Bus width A15 to A9 A8 to A6 A5 A4 to A2 A14 to A8 A7 to A5 A4 A3 to A1 0000100 (burst read and single write) CAS latency 0 (burst type = sequential) 000 (burst length 1) 0000100 (burst read and single write) CAS latency 0 (burst type = sequential) 000 (burst length 1) 16-bit Bus width Rev. 4.00, 03/04, page 225 of 660 Before mode register setting, a 100 s idle time (depending on the memory manufacturer) must be guaranteed after powering on requested by the synchronous DRAM. If the reset signal pulse width is greater than this idle time, there is no problem in performing mode register setting immediately. The number of dummy auto-refresh cycles specified by the manufacturer (usually 8) or more must be executed. This is usually achieved automatically while various kinds of initialization are being performed after auto-refresh setting, but a way of carrying this out more dependably is to set a short refresh request generation interval just while these dummy cycles are being executed. With simple read or write access, the address counter in the synchronous DRAM used for autorefreshing is not initialized, and so the cycle must always be an auto-refresh cycle. TRp1 TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 CKIO A15 to A12 or (A14 to A11) A11 (A10) A12 (A11) A10 to A2 (A9 to A2) RD/ or or D31 to D0 CKE (High) Figure 8.27 Synchronous DRAM Mode Write Timing Rev. 4.00, 03/04, page 226 of 660 8.5.5 Burst ROM Interface Setting bits A0BST (1 to 0), A5BST (1 to 0), and A6BST (1 to 0) in BCR1 to a non-zero value allows burst ROM to be connected to areas 0, 5, and 6. The burst ROM interface provides highspeed access to ROM that has a nibble access function. The timing for nibble access to burst ROM is shown in figure 8.28. Two wait cycles are set. Basically, access is performed in the same way as for normal space, but when the first cycle ends the CS0 signal is not negated, and only the address is changed before the next access is executed. When 8-bit ROM is connected, the number of consecutive accesses can be set as 4, 8, or 16 by bits A0BST (1 to 0), A5BST (1 to 0), or A6BST (1 to 0). When 16-bit ROM is connected, 4 or 8 can be set in the same way. When 32-bit ROM is connected, only 4 can be set. WAIT pin sampling is performed in the first access if one or more wait states are set, and is always performed in the second and subsequent accesses. The second and subsequent access cycles also comprise two cycles when a burst ROM setting is made and the wait specification is 0. The timing in this case is shown in figure 8.29. However, the WAIT signal is ignored in the following cases: * In 16-byte DMA transfer or dual addressing mode, or when writing data to the external address area * In 16-byte DMA transfer or single addressing mode, or when transferring data from an external device with DACK to the external bus area * When accessing cache for write back Rev. 4.00, 03/04, page 227 of 660 T1 TW TW TB2 TB1 TW TB2 TB1 T2 CKIO A25 to A4 A3 to A0 CSn RD/WR RD D31 to D0 BS WAIT Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 8.28 Burst ROM Wait Access Timing Rev. 4.00, 03/04, page 228 of 660 T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO A25 to A4 A3 to A0 RD/ D31 to D0 Note: For a write cycle, a basic bus cycle (write cycle) is performed. Figure 8.29 Burst ROM Basic Access Timing 8.5.6 PCMCIA Interface In this LSI, setting the A5PCM bit in BCR1 to 1 makes the bus interface for physical space area 5 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2 (PCMCIA2.1). Setting the A6PCM bit to 1 makes the bus interface for physical space area 6 an IC memory card and I/O card interface as stipulated in JEIDA version 4.2. Figure 8.30 shows the PCMCIA space allocation. When the PCMCIA interface is used, a bus size of 8 or 16 bits can be set by bits A5SZ1 and A5SZ0, or A6SZ1 and A6SZ0, in BCR2. Rev. 4.00, 03/04, page 229 of 660 Figure 8.31 shows an example of PCMCIA card connection to this LSI. To enable active insertion of the PCMCIA cards (i.e. insertion or removal while system power is being supplied), a 3-state buffer must be connected between this LSI bus interface and the PCMCIA cards. As operation in big-endian mode is not explicitly stipulated in the JEIDA/PCMCIA specifications, the PCMCIA interface for this LSI in big-endian mode is stipulated independently. However, the WAIT signal is ignored in the following cases: * In 16-byte DMA transfer or dual addressing mode, or when writing data to the external address area * In 16-byte DMA transfer or single addressing mode, or when transferring data from an external device with DACK to the external bus area * When accessing cache for write back 32-Mbyte capacity (REG = I/O port) Area 5: H'14000000 Common memory/ attribute memory Area 5: H'16000000 I/O space Area 6: H'18000000 Common memory/ attribute memory Area 6: H'1A000000 I/O space Up to 16-Mbyte capacity (REG = A24) Area 5: H'14000000 Area 5: H'15000000 Area 5: H'16000000 H'17000000 Area 6: H'18000000 Area 6: H'19000000 Area 6: H'1A000000 H'1B000000 Attribute memory Common memory I/O space Attribute memory Common memory I/O space Figure 8.30 PCMCIA Space Allocation Rev. 4.00, 03/04, page 230 of 660 A24 to A0 D15 to D0 RD/WR CE1B/(CS6) CE1A/(CS5) CE2B CE2A A25 to A0 G D7 to D0 G DIR D15 to D8 G DIR CE1 CE2 D15 to D0 PC card (memory/IO) This LSI RD WE ICIORD ICIOWR OE WE/PGM (IORD) G (IOWR) WAIT WAIT IOIS16 (IOIS16) Card detection circuit CD1, CD2 Output port D7 to D0 A25 to A0 G D15 to D0 G DIR D15 to D8 G DIR CE1 CE2 OE WE/PGM PC card (memory/IO) G WAIT Card detection circuit CD1, CD2 Figure 8.31 Example of PCMCIA Interface Rev. 4.00, 03/04, page 231 of 660 Memory Card Interface Basic Timing: Figure 8.32 shows the basic timing for the PCMCIA IC memory card interface. When physical space areas 5 and 6 are designated as PCMCIA interface areas, bus accesses are automatically performed as IC memory card interface accesses. With a high external bus frequency (CKIO), the setup and hold times for the address (A24 to A0), card enable (CS5, CE2A, CS6, CE2B), and write data (D15 to D0) in a write cycle, become insufficient with respect to RD and WR (the WE pin in this LSI). This LSI provides for this by enabling setup and hold times to be set for physical space areas 5 and 6 in the PCR register. Also, software waits by means of a WCR2 register setting and hardware waits by means of the WAIT pin can be inserted in the same way as for the basic interface. Figure 8.33 shows the PCMCIA memory bus wait timing. Tpcm1 CKIO Tpcm2 A25 to A0 RD/ (read) D15 to D0 (read) (write) D15 to D0 (write) Figure 8.32 Basic Timing for PCMCIA Memory Card Interface Rev. 4.00, 03/04, page 232 of 660 Tpcm0 CKIO Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w A25 to A0 RD/ (read) D15 to D0 (read) (write) D15 to D0 (write) Figure 8.33 Wait Timing for PCMCIA Memory Card Interface Rev. 4.00, 03/04, page 233 of 660 Memory Card Interface Burst Timing: In this LSI, when the IC memory card interface is selected, page mode burst access mode can be used, for read access only, by setting bits A5BST1 and A5BST0 in BCR1 for physical space area 5, or bits A6BST1 and A6BST0 in BCR1 for area 6. This burst access mode is not stipulated in JEIDA version 4.2 (PCMCIA2.1), but allows highspeed data access using ROM provided with a burst mode, etc. Burst access mode timing is shown in figures 8.34 and 8.35. Tpcm1 CKIO Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 A25 to A4 A3 to A0 RD/ (read) D15 to D0 (read) Figure 8.34 Basic Timing for PCMCIA Memory Card Interface Burst Access Rev. 4.00, 03/04, page 234 of 660 Tpcm0 Tpcm1 Tpcm1wTpcm1wTpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO A25 to A4 A3 to A0 RD/ (read) D15 to D0 (read) Figure 8.35 Wait Timing for PCMCIA Memory Card Interface Burst Access When the entire 32-Mbyte memory space is used as IC memory card interface space, the common memory/attribute memory switching signal REG is generated using a port, etc. If 16-Mbytes or less of memory space is sufficient, using 16 Mbytes of memory space as common memory space and 16 Mbytes as attribute memory space enables the A24 pin to be used for the REG signal. I/O Card Interface Timing: Figures 8.36 and 8.37 show the timing for the PCMCIA I/O card interface. Switching between the I/O card interface and the IC memory card interface is performed according to the accessed address. When PCMCIA is designed for physical space area 5, the bus access is automatically performed as an I/O card interface access when a physical address from H'16000000 to H'17FFFFFF is accessed. When PCMCIA is designated for physical space area 6, the bus access is automatically performed as an I/O card interface access when a physical address from H'1A000000 to H'1BFFFFFF is accessed. When accessing a PCMCIA I/O card, the access should be performed using a non-cacheable area in virtual space (P2 or P3 space) or an area specified as non-cacheable by the MMU. Rev. 4.00, 03/04, page 235 of 660 When an I/O card interface access is made to a PCMCIA card in little-endian mode, dynamic sizing of the I/O bus width is possible using the IOIS16 pin. When a 16-bit bus width is set for area 5 or 6, if the IOIS16 signal is high during a word-size I/O bus cycle, the I/O port is recognized as being 8 bits in width. In this case, a data access for only 8 bits is performed in the I/O bus cycle being executed, followed automatically by a data access for the remaining 8 bits. Figure 8.38 shows the basic timing for dynamic bus sizing. In big-endian mode, the IOIS16 signal is not supported. In big-endian mode, the IOIS16 signal should be fixed low. Tpci1 Tpci2 CKIO A25 to A0 RD/ (read) D15 to D0 (read) I (write) D15 to D0 (write) Figure 8.36 Basic Timing for PCMCIA I/O Card Interface Rev. 4.00, 03/04, page 236 of 660 Tpci0 CKIO Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w A25 to A0 RD/ (read) D15 to D0 (read) (write) D15 to D0 (write) Figure 8.37 Wait Timing for PCMCIA I/O Card Interface Rev. 4.00, 03/04, page 237 of 660 Tpci0 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w CKIO A25 to A1 A0 RD/ (read) D15 to D0 (read) I (write) D15 to D0 (write) Figure 8.38 Dynamic Bus Sizing Timing for PCMCIA I/O Card Interface Rev. 4.00, 03/04, page 238 of 660 8.5.7 Waits between Access Cycles A problem associated with higher external memory bus operating frequencies is that data buffer turn-off on completion of a read from a low-speed device may be too slow, causing a collision with data in the next access. This results in lower reliability or incorrect operation. To avoid this problem, a data collision prevention feature has been provided. This memorizes the preceding access area and the kind of read/write. If there is a possibility of a bus collision when the next access is started, a wait cycle is inserted before the access cycle thus preventing a data collision. There are two cases in which a wait cycle is inserted: when an access is followed by an access to a different area, and when a read access is followed by a write access from this LSI. When this LSI performs consecutive write cycles, the data transfer direction is fixed (from this LSI to other memory) and there is no problem. With read accesses to the same area, in principle, data is output from the same data buffer, and wait cycle insertion is not performed. Bits AnIW1 and AnIW0 (n = 0, 2 to 6) in WCR1 specify the number of idle cycles to be inserted between access cycles when a physical space area access is followed by an access to another area, or when this LSI performs a write access after a read access to physical space area n. If there is originally space between accesses, the number of idle cycles inserted is the specified number of idle cycles minus the number of empty cycles. Waits are not inserted between accesses when bus arbitration is performed, since empty cycles are inserted for arbitration purposes. T1 CKIO A25 to A0 T2 Twait T1 T2 Twait T1 T2 RD/ D31 to D0 Area m read Area n space read Area n space write Area m inter-access wait specification Area n inter-access wait specification Figure 8.39 Waits between Access Cycles Rev. 4.00, 03/04, page 239 of 660 8.5.8 Bus Arbitration When a bus release request (BREQ) is received from an external device, buses are released after the bus cycle being executed is completed and a bus grant signal (BACK) is output. The bus is not released during burst transfers for cache fills or a write back and TAS instruction execution between the read cycle and write cycle. Bus arbitration is not executed in multiple bus cycles that are generated when the data bus width is shorter than the access size; i.e. in the bus cycles when longword access is executed for the 8-bit memory. At the negation of BREQ, BACK is negated and bus use is restarted. See Appendix B, Pin Functions, for the pin state when the bus is released. This LSI sometimes needs to retrieve a bus it has released. For example, when memory generates a refresh request or an interrupt request internally, this LSI must perform the appropriate processing. This LSI has a bus request signal (IRQOUT) for this purpose. When it must retrieve the bus, it asserts the IRQOUT signal. Devices asserting an external bus release request receive the assertion of the IRQOUT signal and negate the BREQ signal to release the bus. This LSI retrieves the bus and carries out the processing. IRQOUT Pin Assertion Conditions: * When a memory refresh request has been generated but the refresh cycle has not yet begun * When an interrupt is generated with an interrupt request level higher than the setting of the interrupt mask bits (I3 to I0) in the status register (SR). (This does not depend on the SR.BL bit.) 8.5.9 Bus Pull-Up With this LSI, address pin pull-up can be performed when the bus is released by setting the PULA bit in BCR1 to 1. The address pins are pulled up for a 4-clock period after BACK is asserted. Figure 8.40 shows the address pin pull-up timing. Similarly, data pin pull-up can be performed by setting the PULD bit in BCR1 to 1. The data pins should be pulled up when the data bus is not in use. The data pin pull-up timing for a read cycle is shown in figure 8.41, and the timing for a write cycle in figure 8.42. CKIO A25 to A0 Pull-up Hi-Z Figure 8.40 Pins A25 to A0 Pull-Up Timing Rev. 4.00, 03/04, page 240 of 660 CKIO D31 to D0 Pull-up Pull-up Figure 8.41 Pins D31 to D0 Pull-Up Timing (Read Cycle) CKIO D31 to D0 Pull-up Pull-up Figure 8.42 Pins D31 to D0 Pull-Up Timing (Write Cycle) Rev. 4.00, 03/04, page 241 of 660 Rev. 4.00, 03/04, page 242 of 660 Section 9 Direct Memory Access Controller (DMAC) This chip includes a four-channel direct memory access controller (DMAC). The DMAC can be used in place of the CPU to perform high-speed transfers between external devices that have DACK (transfer request acknowledge signal), external memory, memory-mapped external devices, and on-chip peripheral modules (SCIF, A/D converter, and D/A converter). Using the DMAC reduces the burden on the CPU and increases overall operating efficiency. Figure 9.1 shows a block diagram of the DMAC. 9.1 Feature The DMAC has the following features. * Four channels * Address space: Architecturally 4-Gbytes * 8-bit, 16-bit, 32-bit, or 16-byte transfer (In 16-byte transfer, four 32-bit reads are executed, followed by four 32-bit writes.) * Maximum transfer counter: 16 Mbytes (16777216 transfers) * Supports dual address mode Direct address transfer mode: The values specified in the DMAC registers indicates the transfer source and transfer destination. Two bus cycles are required for one data transfer. Indirect address transfer mode: Data is transferred with the address stored prior to the address specified in the transfer source address in the DMAC. Other operations are the same as those of direct address transfer mode. This function is only valid in channel 3. Four bus cycles are required for one data transfer. * Supports single address mode Either the transfer source or transfer destination peripheral device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. One bus cycle is required for one data transfer. * Channel functions: Transfer mode that can be specified is different in each channel. Channel 0: External request can be accepted. Channel 1: External request can be accepted. Channel 2: This channel has a source address reload function, which reloads a source address for each 4 transfers. Channel 3: In this channel, direct address transfer mode or indirect address transfer mode can be specified. * Reload function: The value that was specified in the source address register can be automatically reloaded every 4 DMA transfers. This function is only valid in channel 2. Rev. 4.00, 03/04, page 243 of 660 * Three types of Transfer requests External request: From two DREQ pins (channels 0 and 1 only). DREQ can be detected either by the falling edge or by the low level. On-chip module request: Requests from on-chip peripheral modules such as serial communications interface (SCIF), A/D converter (A/D), and a timer (CMT). This request can be accepted in all the channels. Auto request: The transfer request is generated automatically within the DMAC. * Selectable bus modes: Cycle-steal mode or burst mode * Selectable channel priority levels Fixed mode: The channel priority is fixed. Round-robin mode: The priority of the channel in which the execution request was accepted is made the lowest. * Interrupt request: An interrupt request can be generated to the CPU after transfers end by the specified counts. DMAC module Interation control Register control Internal bus SAR_n DAR_n On-chip peripheral module Peripheral bus DMATCR_n Start-up control CHCR_n , SCIF A/D converter CMT DEI_n DACK0, DACK1 DRAK0, DRAK1 External ROM External RAM External I/O (memory mapped) External I/O (with acknowledge) Bus state controller Request priority control DMAOR Bus interface Legend DMAOR: DMAC operation register SAR_n: DMAC source address register DAR_n: DMAC destination address register DMATCR_n:DMAC transfer count register CHCR_n: DMAC channel control register DEI_n: DMA transfer-end interrupt request to CPU n: 0 to 3 Figure 9.1 DMAC Block Diagram Rev. 4.00, 03/04, page 244 of 660 9.2 Input/Output Pin Table 9.1 shows the DMAC pins. Table 9.1 Pin Configuration Symbol DREQ0 DACK0 I/O I O Function DMA transfer request input from external device to channel 0 Strobe output to an external I/O at DMA transfer request from external device to channel 0 Output showing that DREQ0 has been accepted DMA transfer request input from external device to channel 1 Strobe output to an external I/O at DMA transfer request from external device to channel 1 Output showing that DREQ1 has been accepted Channel Name 0 DMA transfer request DREQ acknowledge DMA request acknowledge 1 DMA transfer request DREQ acknowledge DRAK0 DREQ1 DACK1 O I O DMA request acknowledge DRAK1 O 9.3 Register Description DMAC has a total of 17 registers. Each channel has four control registers. One other control register is shared by all channels. Refer to section 23, List of Registers, for more details of the addresses and access sizes. Channel 0 * DMA source address register 0 (SAR0) * DMA destination address register 0 (DAR0) * DMA transfer count register 0 (DMATCR0) * DMA channel control register 0 (CHCR0) Channel 1 * DMA source address register 1 (SAR1) * DMA destination address register 1 (DAR1) * DMA transfer count register 1 (DMATCR1) * DMA channel control register 1 (CHCR1) Rev. 4.00, 03/04, page 245 of 660 Channel 2 * DMA source address register 2 (SAR2) * DMA destination address register 2 (DAR2) * DMA transfer count register 2 (DMATCR2) * DMA channel control register 2 (CHCR2) Channel 3 * DMA source address register 3 (SAR3) * DMA destination address register 3 (DAR3) * DMA transfer count register 3 (DMATCR3) * DMA channel control register 3 (CHCR3) Any Channel * DMA operation register (DMAOR) 9.3.1 DMA Source Address Registers 0 to 3 (SAR_0 to SAR_3) DMA source address registers 0 to 3 (SAR_0 to SAR_3) are 32-bit read/write registers that specify the source address of a DMA transfer. These registers include count functions, and during a DMA transfer, these registers indicate the next source address. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. When transferring data in 16-byte units, a 16-byte boundary (address 16n) must be set for the source address value. Specifying other addresses does not guarantee operation. The initial value is undefined by resets. The previous value is held in standby mode. When accessed in 16 bits, the other 16-bit data which has not been accessed is held. 9.3.2 DMA Destination Address Registers 0 to 3 (DAR_0 to DAR_3) DMA destination address registers 0 to 3 (DAR_0 to DAR_3) are 32-bit read/write registers that specify the destination address of a DMA transfer. These registers include count functions, and during a DMA transfer, these registers indicate the next destination address. To transfer data in 16 bits or in 32 bits, specify the address with 16-bit or 32-bit address boundary. Specifying other addresses does not guarantee operation. The initial value is undefined by resets. The previous value is held in standby mode. When accessed in 16 bits, the other 16-bit data which has not been accessed is held. Rev. 4.00, 03/04, page 246 of 660 9.3.3 DMA Transfer Count Registers 0 to 3 (DMATCR_0 to DMATCR_3) DMA transfer count registers 0 to 3 (DMATCR_0 to DMATCR_3) are 24-bit read/write registers that specify the DMA transfer count (bytes, words, or longwords) in each channel. The number of transfers is 1 when the setting is H'000001, and 16777216 (the maximum) when H'000000 is set. During a DMA transfer, these registers indicate the remaining transfer count. To transfer data in 16 bytes, one 16-byte transfer (128 bits) counts one. Upper eight bits in DMATCR are reserved. These bits are always read as 0. The write value should always be 0. When using 16-byte transfer, an integral multiple of 4 (4n) must be set for the number of transfers to ensure normal operation. The initial value is undefined by resets. The previous value is held in standby mode. Bit 31 to 24 Bit Name Initial Value R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 23 to 0 R/W 24-bit register 9.3.4 DMA Channel Control Registers 0 to 3 (CHCR_0 to CHCR_3) DMA channel control registers 0 to 3 (CHCR_0 to CHCR_3) are 32-bit read/write registers that specifies operation mode, transfer method, or others in each channel. These register values are initialized to 0s by resets. The previous value is held in standby mode. When accessed in 16 bits, the other 16-bit data which has not been accessed is held. Bit 31 to 21 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00, 03/04, page 247 of 660 Bit 20 Bit Name DI Initial Value R/W 0 (R/W)* 2 Description Direct/Indirect Selection DI selects direct address mode or indirect address mode in channel 3. This bit is only valid in CHCR_3 and is not used in CHCR_0 to CHCR_2. Writing to this bit is invalid in CHCR_0 to CHCR_2; 0 is read if this bit is read. When using 16-byte transfer, direct address mode must be specified. Operation is not guaranteed if indirect address mode is specified. 0: Direct address mode 1: Indirect address mode 19 RO 0 (R/W)* 2 Source Address Reload RO selects whether the source address initial value is reloaded in channel 2. This bit is only valid in CHCR_2 and is not used in CHCR_0 to CHCR_1, or CHCR_3. Writing to this bit is invalid in CHCR_0, CHCR_1, and CHCR_3; 0 is read if this bit is read. When using 16-byte transfer, this bit must be cleared to 0, specifying nonreloading. Operation is not guaranteed if reloading is specified. 0: A source address is not reloaded 1: A source address is reloaded 18 RL 0 (R/W)* 2 Request Check Level RL specifies the DRAK (acknowledge of DREQ) signal output is high active or low active. This bit is only valid in CHCR_0 and CHCR_1. Writing to this bit is invalid in CHCR_2 and CHCR_3; 0 is read if this bit is read. 0: Low-active output of DRAK 1: High-active output of DRAK 17 AM 0 (R/W)* 2 Acknowledge Mode AM specifies whether DACK is output in data read cycle or in data write cycle in dual address mode. This bit is only valid in CHCR_0 and CHCR_1. Writing to this bit is invalid in CHCR_2 and CHCR_3; 0 is read if this bit is read. 0: DACK output in read cycle 1: DACK output in write cycle Rev. 4.00, 03/04, page 248 of 660 Bit 16 Bit Name AL Initial Value R/W 0 (R/W)* 2 Description Acknowledge Level AL specifies the DACK (acknowledge) signal output is high active or low active. This bit is only valid in CHCR_0 and CHCR_1. Writing to this bit is invalid in CHCR_2 and CHCR_3; 0 is read if this bit is read. 0: Low-active output of DACK 1: High-active output of DACK 15 14 DM1 DM0 0 0 R/W R/W Destination Address Mode DM1 and DM0 select whether the DMA destination address is incremented, decremented, or left fixed. 00: Fixed destination address (Initial value) 01: Destination address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Destination address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) 11: Reserved (Setting prohibited) 13 12 SM1 SM0 0 0 R/W R/W Source Address Mode SM1 and SM0 select whether the DMA source address is incremented, decremented, or left fixed. 00: Fixed source address 01: Source address is incremented (+1 in 8-bit transfer, +2 in 16-bit transfer, +4 in 32-bit transfer, +16 in 16-byte transfer) 10: Source address is decremented (-1 in 8-bit transfer, -2 in 16-bit transfer, -4 in 32-bit transfer; illegal setting in 16-byte transfer) 11: Reserved (Setting prohibited) Notes: If the transfer source is specified in indirect address, specify the address, in which the data to be transferred is stored and which is stored as data (indirect address), SAR_3. Specification of SAR_3 increment or decrement in indirect address mode depends on SM1 and SM0 settings. In this case, however, the SAR_3 increment or decrement value is +4, -4, or fixed to 0 regardless of the transfer data size specified in TS1 and TS0. Rev. 4.00, 03/04, page 249 of 660 Bit 11 10 9 8 Bit Name RS3 RS2 RS1 RS0 Initial Value 0 0 0 0 R/W R/W R/W R/W R/W Description Resource Select RS3 to RS0 specify which transfer requests will be sent to the DMAC. 0000: External request, dual address mode 0001: Reserved (Setting prohibited) 0010: External request / Single address mode External address space external device with DACK 0011: External request / Single address mode External device with DACK external address space 0100: Auto request 0101: Reserved (Setting prohibited) 0110: Reserved (Setting prohibited) 0111: Reserved (Setting prohibited) 1000: Reserved (Setting prohibited) 1001: Reserved (Setting prohibited) 1010: Reserved (Setting prohibited) 1011: Reserved (Setting prohibited) 1100: SCIF transmission 1101: SCIF reception 1110: Internal A/D 1111: CMT Notes: 1. External request specification is valid only in channels 0 and 1. None of the request sources can be selected in channels 2 and 3. 2. When using 16-byte transfer, the following settings must not be made: 1100 SCIF transmission 1101 SCIF reception 1110 A/D converter 1111 CMT Operation is not guaranteed if these settings are made. Rev. 4.00, 03/04, page 250 of 660 Bit 7 Bit Name -- Initial Value R/W 0 R Description Reserved This bit is always read 0. The write value should always be 0. 6 DS 0 (R/W)* DREQ Select Bit 2 DS selects the sampling method of the DREQ pin that is used in external request mode is detection in low level or at the falling edge. This bit is only valid in CHCR_0 and CHCR_1. Writing to this bit is invalid in CHCR_2 and CHCR_3; 0 is read if this bit is read. In channel 0 and 1, if an on-chip peripheral module is specified as a transfer request source or an auto request is specified, specification of this bit is ignored and detection at the falling edge is fixed except in an auto-request. 0: DREQ detected in low level 1: DREQ detected at falling edge 5 TM 0 R/W Transmit Mode TM specifies the bus mode when transferring data. 0: Cycle steal mode 1: Burst mode 4 3 TS1 TS0 0 0 R/W R/W Transmit Size Bits 1 and 0 TS1 and TS0 specify the size of data to be transferred. 00: Byte size (8 bits) 01: Word size (16 bits) 10: Longword size (32 bits) 11: 16-byte unit (4 longword transfers) 2 IE 0 R/W Interrupt Enable Bit Setting this bit to 1 generates an interrupt request when data transfer end (TE = 1) by the count specified in DMATCR. 0: Interrupt request is not generated even if data transfer ends by the specified count 1: Interrupt request is generated if data transfer ends by the specified count Rev. 4.00, 03/04, page 251 of 660 Bit 1 Bit Name TE Initial Value 0 R/W R/(W)* 1 Description Transfer End TE is set to 1 when data transfer ends by the count specified in DMATCR. At this time, if the IE bit is set to 1, an interrupt request is generated. Before this bit is set to 1, if data transfer ends due to an NMI interrupt, a DMAC address error, or clearing the DE bit or the DME bit in DMAOR, this bit is not set to 1. Even if the DE bit is set to 1 while this bit is set to 1, transfer is not enabled. 0: Data transfer does not end by the count specified in DMATCR Clear condition: Writing 0 after TE = 1 read at power-on reset or manual reset 1: Data transfer ends by the specified count 0 DE 0 R/W DMAC Enable DE enables channel operation. 0: Disables channel operation 1: Enables channel operation Note: If an auto request is specifies (specified in RS3 to RS0), transfer starts when this bit is set to 1. In an external request or an internal module request, transfer starts if transfer request is generated after this bit is set to 1. Clearing this bit during transfer can terminate transfer. Even if the DE bit is set, transfer is not enabled if the TE bit is 1, the DME bit in DMAOR is 0, or the NMIF bit in DMAOR is 1. Notes: 1. Only 0 can be written to the TE bit after 1 is read. 2. DI, RO, RL, AM, AL, and DS bits are not included in some channels. Rev. 4.00, 03/04, page 252 of 660 9.3.5 DMA Operation Register (DMAOR) The DMA operation register (DMAOR) is a 16-bit read/write register that controls the DMAC transfer mode. This register's values are initialized to 0s by resets. The previous value is held in standby mode. Bit 15 to 10 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 9 8 PR1 PR0 0 0 R/W R/W Priority Mode PR1 and PR0 select the priority level between channels when there are transfer requests for multiple channels simultaneously. 00: CH0 > CH1 > CH2 > CH3 01: CH0 > CH2 > CH3 > CH1 10: CH2 > CH0 > CH1 > CH3 11: Round-robin 7 to 3 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 AE 0 R/(W)* Address Error Flag AE indicates that an address error occurred during DMA transfer. If this bit is set during data transfer, transfers on all channels are suspended. The CPU cannot write 1 to this bit. 0: No DMAC address error. DMA transfer is enabled. Clearing conditions: Writing AE = 0 after AE = 1 read, power-on reset, manual reset 1: DMAC address error. DMA transfer is disabled. Setting condition: This bit is set by occurrence of a DMAC address error. Rev. 4.00, 03/04, page 253 of 660 Bit 1 Bit Name NMIF Initial Value 0 R/W Description R/(W)* NMI Flag NMIF indicates that an NMI interrupt occurred. This bit is set regardless of whether DMAC is in operating or halt state. If this bit is set during data transfer, the transfer on all channels are suspended. The CPU cannot write 1 to this bit. Only 0 can be written to clear this bit after 1 is read. 0: No NMI input. DMA transfer is enabled. (Initial value) Clearing condition: Writing NMIF = 0 after NMIF = 1 read, power-on reset, manual reset 1: NMI input. DMA transfer is disabled. Setting condition: This bit is set by occurrence of an NMI interrupt. 0 DME 0 R/W DMA Master Enable DME enables or disables DMA transfers on all channels. If the DME bit and the DE bit corresponding to each channel in CHCR are set to 1s, transfer is enabled in the corresponding channel. If this bit is cleared during transfer, transfers on all the channels can be suspended. Even if the DME bit is set, transfer is not enabled if the TE bit is 1 or the DE bit is 0 in CHCR, or the AE bit is 1 or the NMIF bit is 1 in DMAOR. 0: Disable DMA transfers on all channels 1: Enable DMA transfers on all channels Note: * Only 0 can be written to the AE and NMIF bits after 1 is read. Rev. 4.00, 03/04, page 254 of 660 9.4 Operation When there is a DMA transfer request, the DMAC starts the transfer according to the predetermined channel priority order; when the transfer end conditions are satisfied, it ends the transfer. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The dual address mode has direct address transfer mode and indirect address transfer mode. In the bus mode, the burst mode or the cycle steal mode can be selected. 9.4.1 DMA Transfer Flow After the DMA source address registers (SAR_0 to SAR_3), DMA destination address registers (DAR_0 to DAR_3), DMA transfer count registers (DMATCR_0 to DMATCR_3), DMA channel control registers (CHCR_0 to CHCR_3), and DMA operation register (DMAOR) are set, the DMAC transfers data according to the following procedure: 1. Checks to see if transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0) 2. When a transfer request comes and transfer is enabled, the DMAC transfers 1 transfer unit of data (depending on the TS0 and TS1 settings). For an auto request, the transfer begins automatically when the DE bit and DME bit are set to 1. The DMATCR value will be decremented for each transfer. The actual transfer flows vary by address mode and bus mode. 3. When the specified number of transfer have been completed (when DMATCR reaches 0), the transfer ends normally. If the IE bit of the CHCR is set to 1 at this time, a DEI interrupt is sent to the CPU. 4. When an NMI interrupt is generated or an address error occurs during DMA transfer, the transfers are suspended. Transfers are also suspended when the DE bit of the CHCR or the DME bit of the DMAOR are changed to 0. Figure 9.2 is a flowchart of this procedure. Rev. 4.00, 03/04, page 255 of 660 Start Initial settings (SAR, DAR, DMATCR, CHCR, DMAOR) DE, DME = 1 and NMIF, TE = 0? Yes No Transfer request occurs?*1 Yes No *2 Bus mode, transfer request mode, ,4-3 detection selection system *3 Transfer (1 transfer unit); DMATCR - 1 DMATCR, SAR and DAR updated DMATCR = 0? No NMIF = 1 or DE = 0 or DME = 0? Yes Transfer aborted No Yes DEI interrupt request (when IE = 1) NMIF = 1 or DE = 0 or DME = 0? Yes Transfer end No Normal end Notes: 1. 2. 3. In auto-request mode, transfer begins when NMIF and TE are all 0 and the DE and DME bits are set to 1. ,4-3 = level detection in burst mode (external request) or cycle-steal mode. ,4-3 = edge detection in burst mode (external request), or auto-request mode in burst mode. Figure 9.2 DMAC Transfer Flowchart Rev. 4.00, 03/04, page 256 of 660 9.4.2 DMA Transfer Requests DMA transfer requests are basically generated in either the data transfer source or destination, but they can also be generated by external devices and on-chip peripheral modules that are neither the source nor the destination. Transfers can be requested in three modes: auto request, external request, and on-chip peripheral module request. The request mode is selected in the RS3 to RS0 bits of CHCR_0 to CHCR_3. Auto-Request Mode: When there is no transfer request signal from an external source, as in a memory-to-memory transfer or a transfer between memory and an on-chip peripheral module unable to request a transfer, the auto-request mode allows the DMAC to automatically generate a transfer request signal internally. When the DE bits of CHCR_0 to CHCR_3 and the DME bit of the DMAOR are set to 1, the transfer begins so long as the TE bits of CHCR_0 to CHCR_3 and the AE but and NMIF bit of DMAOR are all 0. External Request Mode: In this mode a transfer is performed at the request signal (DREQ) of an external device. Choose one of the modes shown in table 9.2 according to the application system. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon a request at the DREQ input. Choose to detect DREQ by either the falling edge or low level of the signal input with the DS bit of CHCR_0 to CHCR_1 (DS = 0 is level detection, DS = 1 is edge detection). The source of the transfer request does not have to be the data transfer source or destination. Table 9.2 RS3 0 RS2 0 Selecting External Request Modes with the RS Bits RS1 0 1 RS0 0 0 Address Mode Dual address mode Single address mode Source Any* External memory, memory-mapped external device External device with DACK Destination Any* External device with DACK External memory, memory-mapped external device 1 Note: * External memory, memory-mapped external device, on-chip memory, on-chip peripheral module (excluding DMAC, UBC, and BSC) Rev. 4.00, 03/04, page 257 of 660 On-Chip Peripheral Module Request: In this mode a transfer is performed at the transfer request signal (interrupt request signal) of an on-chip peripheral module. This mode cannot be set in case of 16-byte transfer. The transfer request signals include 4 signals: the receive data full interrupts (RXI) and the transmit data empty interrupts (TXI) from serial communication interfaces (SCIF), the A/D conversion end interrupt (ADI) of the A/D converter, and the compare match timer interrupt (CMI) of the CMT. When this mode is selected, if the DMA transfer is enabled (DE = 1, DME = 1, TE = 0, AE = 0, NMIF = 0), a transfer is performed upon the input of a transfer request signal. The source of the transfer request does not have to be the data transfer source or destination. When RXI is set as the transfer request, however, the transfer source must be the SCI's receive data register (RDR). Likewise, when TXI is set as the transfer request, the transfer source must be the SCI's transmit data register (TDR). And if the transfer requester is the A/D converter, the data transfer source must be the A/D data register (ADDR). Table 9.3 Selecting On-Chip Peripheral Module Request Modes with the RS Bit DMA Transfer Request Source RS3 RS2 1 1 1 1 1 1 0 0 1 1 1 1 RS1 1 1 0 0 1 1 RS0 0 1 0 1 0 1 DestiDMA Transfer Request Signal Source nation Bus Mode SCIF TXI2 (SCIF transmit data empty Any* transmitter interrupt transfer request) SCIF receiver A/D converter CMT RXI2 (SCIF receive data full interrupt transfer request) ADI (A/D conversion end interrupt) CMI (Compare match timer interrupt) RDR1 ADDR Any* TDR2 Any* Any* Any* Burst/ cycle steal Burst/ cycle steal Burst/ cycle steal Burst/ cycle steal ADDR: A/D data register of A/D converter Note: * External memory, memory-mapped external device, on-chip peripheral module (excluding DMAC, UBC , and BSC) When outputting transfer requests from on-chip peripheral modules, the appropriate interrupt enable bits must be set to output the interrupt signals. If the interrupt request signal of the on-chip peripheral module is used as a DMA transfer request signal, an interrupt is not generated to the CPU. The DMA transfer request signals of table 9.3 are automatically withdrawn when the corresponding DMA transfer is performed. If the cycle-steal mode is being used, they are withdrawn at the first transfer; if the burst mode is being used, they are withdrawn at the last transfer. Rev. 4.00, 03/04, page 258 of 660 9.4.3 Channel Priority When the DMAC receives simultaneous transfer requests on two or more channels, it selects a channel according to a predetermined priority order. Two modes (fixed mode and round-robin mode) are selected by the priority bits PR1 and PR0 in the DMA operation register (DMAOR). Fixed Mode: In this mode, the priority levels among the channels remain fixed. There are three kinds of fixed modes as follows: * CH0 > CH1 > CH2 > CH3 * CH0 > CH2 > CH3 > CH1 * CH2 > CH0 > CH1 > CH3 These are selected by the PR1 and the PR0 bits in the DMA operation register (DMAOR). Round-Robin Mode: Each time one word, byte, or longword, or 16-byte data is transferred on one channel, the priority order is rotated. The channel on which the transfer was just finished rotates to the bottom of the priority order. The round-robin mode operation is shown in figure 9.3. The priority of the round-robin mode is CH0 > CH1 > CH2 > CH3 immediately after a reset. Rev. 4.00, 03/04, page 259 of 660 (1) When channel 0 transfers Initial priority order CH0 > CH1 > CH2 > CH3 CH1 > CH2 > CH3 > CH0 Channel 0 becomes bottom priority Priority order afrer transfer (2) When channel 1 transfers Channel 0 becomes bottom priority. The priority of channel 0, which was higher than channel 3, is also shifted. Initial priority order CH0 > CH1 > CH2 > CH3 Priority order afrer transfer CH2 > CH3 > CH0 > CH1 (3) When channel 2 transfers Channel 2 becomes bottom priority. The priority of channels 0 and 1, which were higher than channel 2, are also shifted. If immediately Priority order CH3 > CH0 > CH1 > CH2 after there is a request to transfer afrer transfer channel 1 only, channel 1 becomes bottom priority and the priority of channels 0 and 3, which were Post-transfer priority order higher than channel 1, are also when there is an CH2 > CH3 > CH0 > CH1 shifted. immediate transfer request to channel 1 only CH0 > CH1 > CH2 > CH3 Initial priority order (4) When channel 3 transfers Priority order afrer transfer Priority order afrer transfer CH0 > CH1 > CH2 > CH3 CH0 > CH1 > CH2 > CH3 Priority order does not change Figure 9.3 Round-Robin Mode Rev. 4.00, 03/04, page 260 of 660 Figure 9.4 shows how the priority order changes when channel 0 and channel 3 transfers are requested simultaneously and a channel 1 transfer is requested during the channel 0 transfer. The DMAC operates as follows: 1. Transfer requests are generated simultaneously to channels 0 and 3. 2. Channel 0 has a higher priority, so the channel 0 transfer begins first (channel 3 waits for transfer). 3. A channel 1 transfer request occurs during the channel 0 transfer (channels 1 and 3 are both waiting) 4. When the channel 0 transfer ends, channel 0 becomes lowest priority. 5. At this point, channel 1 has a higher priority than channel 3, so the channel 1 transfer begins (channel 3 waits for transfer). 6. When the channel 1 transfer ends, channel 1 becomes lowest priority. 7. The channel 3 transfer begins. 8. When the channel 3 transfer ends, channels 3 and 2 shift downward in priority so that channel 3 becomes the lowest priority. Transfer request Waiting channel(s) DMAC operation Channel priority (1) Channels 0 and 3 3 (2) Channel 0 transfer start Priority order changes 1,3 (4) Channel 0 transfer ends 1>2>3>0 0>1>2>3 (3) Channel 1 (5) Channel 1 transfer starts Priority order changes 3 (6) Channel 1 transfer ends 2>3>0>1 (7) Channel 3 transfer starts None (8) Channel 3 transfer ends Priority order changes 0>1>2>3 Figure 9.4 Changes in Channel Priority in Round-Robin Mode Rev. 4.00, 03/04, page 261 of 660 9.4.4 DMA Transfer Types The DMAC supports the transfers shown in table 9.4. The dual address mode has the direct address mode and the indirect address mode. In the direct address mode, an output address value is the data transfer target address; in the indirect address mode, the value stored in the output address, not the output address value itself, is the data transfer target address. A data transfer timing depends on the bus mode, which has cycle steal mode and burst mode. Table 9.4 Supported DMA Transfers Destination External Device External with DACK Memory Not available Dual, single Dual, single Not available Dual, single Dual Dual Dual MemoryOn-Chip Mapped External Peripheral Device Module Dual, single Dual Dual Dual Not available Dual Dual Dual Source External device with DACK External memory Memory-mapped external device On-chip peripheral module Notes: 1. Dual: Dual address mode 2. Single: Single address mode 3. The dual address mode includes the direct address mode and the indirect address mode. 4. 16-byte transfer is not available for on-chip peripheral modules. Rev. 4.00, 03/04, page 262 of 660 Address Modes: * Dual Address Mode In the dual address mode, both the transfer source and destination are accessed (selectable) by an address. The source and destination can be located externally or internally. The dual address mode has (1) direct address transfer mode and (2) indirect address transfer mode. (1) In the direct address transfer mode, DMA transfer requires two bus cycles because data is read from the transfer source in a data read cycle and written to the transfer destination in a data write cycle. At this time, transfer data is temporarily stored in the DMAC. In the transfer between external memories as shown in figure 9.5, data is read to the DMAC from one external memory in a data read cycle, and then that data is written to the other external memory in a write cycle. Figures 9.6 to 9.8 show examples of the timing at this time. DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The SAR value is an address, data is read from the transfer source module, and the data is tempolarily stored in the DMAC. First bus cycle DMAC SAR Address bus Memory Data bus DAR Transfer source module Transfer destination module Data buffer The DAR value is an address and the value stored in the data buffer in the DMAC is written to the transfer destination module. Second bus cycle Figure 9.5 Operation in the Direct Address Mode in the Dual Address Mode Rev. 4.00, 03/04, page 263 of 660 CKIO A25 to A0 Transfer source address Transfer destination address D31 to D0 DACKn Data read cycle Data write cycle (1st cycle) Note: (2nd cycle) Transfer between external memories, DACK output in a read cycle DACK output timing . is the same as that of Figure 9.6 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) Rev. 4.00, 03/04, page 264 of 660 CKIO A25 to A0 Transfer source address +4 +8 +12 +4 Transfer destination address +8 +12 D31 to D0 DACKn Data read cycle (1st cycle) Note: (2nd cycle) Transfer between external memories, DACK output in a read cycle DACK output timing . is the same as that of Figure 9.7 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (16-byte Transfer, Transfer Source: Ordinary Memory, Transfer Destination: Ordinary Memory) CKIO A25 to A0 Transfer source address Transfer destination address +4 +8 +12 D31 to D0 RD/ DACKn Data read cycle (1st cycle) Note: (2nd cycle) Data write cycle Transfer between external memories, DACK output in a read cycle DACK output timing is the same as that of . Figure 9.8 Example of DMA Transfer Timing in the Direct Address Mode in the Dual Address Mode (16-byte Transfer, Transfer Source: Synchronous DRAM, Transfer Destination: Ordinary Memory) Rev. 4.00, 03/04, page 265 of 660 (2) In the indirect address transfer mode, the address of memory in which data to be transferred is stored is specified in the transfer source address register (SAR_3) in the DMAC. In this mode, the address value specified in the transfer source address register in the DMAC is read first. This value is temporarily stored in the DMAC. Next, the read value is output as an address, and the value stored in that address is stored in the DMAC again. Then, the value read afterwards is written to the address specified in the transfer destination address; this completes one DMA transfer. 16-byte transfer is not possible. Figure 9.9 shows one example. In this example, the transfer destination, the transfer source, and the storage destination of the indirect address are external memories with a 16bit width in the indirect address mode, and transfer data is 16 or 8 bits. Figure 9.10 shows an example of the transfer timing. Rev. 4.00, 03/04, page 266 of 660 Address bus SAR_3 D M A C DAR_3 Temporary buffer Data buffer Memory Data bus Transfer source module Transfer destination module When the value in SAR_3 is an address, the memory data is read and the value is stored in the temporary buffer. The value to be read must be 32 bits since it is used for the address. First and second bus cycles SAR_3 Address bus Memory Data bus D M A C DAR_3 Temporary buffer Data buffer Transfer source module Transfer destination module When the value in the temporary buffer is an address, the data is read from the transfer source module to the data buffer. Third bus cycle SAR_3 Address bus Memory Data bus D M A C DAR_3 Temporary buffer Data buffer Transfer source module Transfer destination module When the value in SAR_3 is an address, the value in the data buffer is written to the transfer source module. Fourth bus cycle Note: The above description uses the memory, transfer source module, or transfer destination module; in practice, any module can be connected in the addressing space. Figure 9.9 Operation in the Indirect Address mode in the Dual Address Mode (When the External Memory Space has a 16-bit Width) Rev. 4.00, 03/04, page 267 of 660 CK A25 to A0 Transfer source address (H) Transfer source address (L) NOP Indirect address NOP Transfer destination address D31 to D0 Indirect address(H) Indirect address(L) Transfer data Transfer data Internal addresu bus Transfer source address *1 NOP Indirect address Internal data bus Transfer source address * 2 Transfer data Transfer data DMAC indirect address buffer Indirect address DMAC data buffer Transfer data Address read cycle NOP cycle (2nd) Data read cycle (3rd) NOP cycle Data write cycle (4th) (1st) Notes: 1. The internal address bus value does not change, and controlled by the port. 2. The DMAC does not fetch the value until 32-bit data is output to the internal data bus. Figure 9.10 Example of Transfer Timing in the Indirect Address Mode in the Dual Address Mode Rev. 4.00, 03/04, page 268 of 660 * Single Address Mode In the single address mode, either the transfer source or transfer destination external device is accessed (selected) by means of the DACK signal, and the other device is accessed by address. In this mode, the DMAC performs one DMA transfer in one bus cycle, accessing one of the external devices by outputting the DACK transfer request acknowledge signal to it, and at the same time outputting an address to the other device involved in the transfer. For example, in the case of transfer between external memory and an external device with DACK, as shown in figure 9.11, when the external device outputs data to the data bus, that data is written to the external memory in the same bus cycle. External address bus SH7706 External memory External data bus DMAC External device with DACK DACK DREQ Data flow Figure 9.11 Data Flow in the Single Address Mode Two kinds of transfer are possible in the single address mode: (1) transfer between an external device with DACK and a memory-mapped external device, and (2) transfer between an external device with DACK and external memory. In both cases, only the external request signal (DREQ) is used for transfer requests. Rev. 4.00, 03/04, page 269 of 660 Figures 9.12 to 9.14 show examples of DMA transfer timing in the single address mode. CKI0 A25 to A0 Address output to external memory space Write strobe signal to external memory space D31 to D0 DACKn Data output from external device with DACK DACK signal (active-low) to external device with DACK (a) External device with DACK external memory space (ordinary memory) CKI0 A25 to A0 Address output to external memory space Read strobe signal to external memory space D31 to D0 DACKn Data output from external memory space DACK signal (active-low) to external device with DACK (b) External memory space external device with DACK (active low) Figure 9.12 Example of DMA Transfer Timing in the Single Address Mode Rev. 4.00, 03/04, page 270 of 660 CKIO A25 to A0 Transfer source address +4 +8 +12 D31 to D0 DACKn Figure 9.13 Example of DMA Transfer Timing in the Single Address Mode (16- Byte Transfer, External Memory Space (Ordinary Memory) -> External Device with DACK) Bus Modes: There are two bus modes: cycle-steal and burst. Select the mode in the TM bits of CHCR_0 to CHCR_3 (one byte, word, or longword, or 16-byte data). * Cycle-Steal Mode In the cycle-steal mode, the bus right is given to another bus master after a one-transfer-unit (8-, 16-, or 32-bit unit) DMA transfer. When another transfer request occurs, the bus rights are obtained from the other bus master and a transfer is performed for one transfer unit. When that transfer ends, the bus right is passed to the other bus master. This is repeated until the transfer end conditions are satisfied. In the cycle-steal mode, transfer areas are not affected regardless of settings of the transfer request source, transfer source, and transfer destination. Figure 9.14 shows an example of DMA transfer timing in the cycle steal mode. Transfer conditions shown in the figure are: Dual address mode DREQ level detection Bus right returned to CPU Bus cycle CPU CPU CPU DMAC Read DMAC Write CPU DMAC Read DMAC Write CPU CPU Figure 9.14 DMA Transfer Example in the Cycle-Steal Mode Rev. 4.00, 03/04, page 271 of 660 * Burst Mode In the burst mode, once the bus right is obtained, the transfer is performed continuously without passing it until the transfer end conditions are satisfied. In the external request mode with low level detection of the DREQ pin, however, when the DREQ pin is driven high, the bus is passed to the other bus master after the DMAC transfer request that has already been accepted ends, even if the transfer end conditions have not been satisfied. The burst mode cannot be used when the serial communications interface (SCIF) and A/D converter are the transfer request sources. Figure 9.15 shows a timing at this point. Bus cycle CPU CPU CPU DMAC Read DMAC Write DMAC Read DMAC Write DMAC Read DMAC Write CPU Figure 9.15 DMA Transfer Example in the Burst Mode Relationship between Request Modes and Bus Modes by DMA Transfer Category: Table 9.5 shows the relationship between request modes and bus modes by DMA transfer category. Table 9.5 Relationship of Request Modes and Bus Modes by DMA Transfer Category Request Mode External External All* All* All* 1 Addres s Mode Transfer Category Dual External device with DACK and external memory External device with DACK and memory-mapped external device External memory and external memory External memory and memorymapped external device Memory-mapped external device and memory-mapped external device External memory and on-chip peripheral module Memory-mapped external device and on-chip peripheral module Bus Mode B/C B/C B/C B/C B/C Transfer Size (bits) Usable Channels 8/16/32/128 0,1 8/16/32/128 0, 1 8/16/32/128 0 to 3* 8/16/32/128 0 to 3* 8/16/32/128 0 to 3* 5 1 5 1 5 All* All* 2 B/C* B/C* B/C* 3 8/16/32* 8/16/32* 8/16/32* 4 0 to 3* 0 to 3* 0 to 3* 5 2 3 4 5 On-chip peripheral module and on- All* chip peripheral module 2 3 4 5 Rev. 4.00, 03/04, page 272 of 660 Address Mode Transfer Category Single External device with DACK and external memory External device with DACK and memory-mapped external device Request Mode External External Bus Mode B/C B/C Transfer Size (bits) Usable Channels 8/16/32/128 0, 1 8/16/32/128 0, 1 B: Burst, C: Cycle steal Notes: 1. External requests, auto requests and on-chip peripheral module requests are all available. For on-chip peripheral module requests, however, SCIF, and A/D converter cannot be specified as the transfer request source. 2. External requests, auto requests and on-chip peripheral module requests are all available. When the SCIF, or A/D converter is also the transfer request source, however, the transfer destination or transfer source must be the SCIF, or A/D converter, respectively. 3. If the transfer request source is the SCIF, the cycle-steal mode is only available. 4. The access size permitted when the transfer destination or source is an on-chip peripheral module register. 5. If the transfer request is an external request, channels 0 and 1 are only available. 6. If the transfer request source is the SDRAM, the transfer size should be set smaller than the bus width. Bus Mode and Channel Priority Order: When a given channel 1 is transferring in the burst mode and there is a transfer request to a channel 0 with a higher priority, the transfer of channel 0 will begin immediately. At this time, if the priority is set in the fixed mode (CH0 > CH1), the channel 1 transfer will continue when the channel 0 transfer has completely finished, even if channel 0 is operating in the cycle-steal mode or in the burst mode. If the priority is set in the round-robin mode, channel 1 will begin operating again after channel 0 completes the transfer of one transfer unit, even if channel 0 is in the cycle-steal mode or in the burst mode. The bus will then switch between the two in the order channel 1, channel 0, channel 1, channel 0. Rev. 4.00, 03/04, page 273 of 660 Even if the priority is set in the fixed mode or in the round-robin mode, it will not give the bus to the CPU since channel 1 is in the burst mode. This example is illustrated in figure 9.16. CPU DMAC CH1 DMAC CH1 DMAC CH0 *1 DMAC CH1 *2 DMAC CH0 *1 DMAC CH1 DMAC CH1 CPU CPU Notes: DMAC CH1 Burst mode 1. Cycle-steal mode 2. Burst mode Round-robin mode in DMAC CH0 and CH1 DMAC CH1 Burst mode CPU Figure 9.16 Bus State when Multiple Channels are Operating (Priority Level is Roundrobin Mode) 9.4.5 Number of Bus Cycle States and DREQ Pin Sampling Timing Number of Bus Cycle States: When the DMAC is the bus master, the number of bus cycles is controlled by the bus state controller (BSC) in the same way as when the CPU is the bus master. For details, see section 8, Bus State Controller (BSC). DREQ Pin Sampling Timing: In the external request mode, the DREQ pin is sampled by clock pulse (CKIO) falling edge or low level detection. When DREQ input is detected, a DMAC bus cycle is generated and DMA transfer is performed, at the earliest, three states later. The second and subsequent DREQ sampling operations are started two cycles after the first sample. Rev. 4.00, 03/04, page 274 of 660 Operation * Cycle-Steal Mode In the cycle-steal mode, the DREQ sampling timing is the same regardless of whether level or edge detection is used. For example, in figure 9.17 (cycle-steal mode, level detection), DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. If DREQ is not detected at this time, sampling is performed in each subsequent cycle. Thus, DREQ sampling is performed one step in advance. The third sampling operation is not performed until the idle cycle following the end of the first DMA transfer. The above conditions are the same whatever the number of CPU transfer cycles, as shown in figure 9.18, and whatever the number of DMA transfer cycles, as shown in figure 9.19. DACK is output in a read in the example in figure 9.17, and in a write in the example in figure 9.18. In both cases, DACK is output for the same duration as CSn. Figure 9.20 illustrates the case where DREQ is not detected and sampling is subsequently executed every cycle. Figure 9.21 shows an example of edge detection in the cycle-steal mode. * Burst Mode, Level Detection In the case of burst mode with level detection, the DREQ sampling timing is the same as in the cycle-steal mode. For example, in figure 9.22, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. The second sampling is started two cycles after the first. Subsequent sampling operations are performed in the idle cycle following the end of the DMA transfer cycle. In the burst mode, also, the DACK output period is the same as in the cycle-steal mode. * Burst Mode, Edge Detection In the case of burst mode with edge detection, DREQ sampling is only performed once. For example, in figure 9.23, DMAC transfer begins, at the earliest, three cycles after the first sampling is performed. After this, DMAC transfer is executed continuously until the number of data transfers set in the DMATCR register have been completed. DREQ is not sampled during this time. To restart DMA transfer after it has been suspended by an NMI, first clear NMIF, then input an edge request again. In the burst mode, also, the DACK output period is the same as in the cycle-steal mode. Rev. 4.00, 03/04, page 275 of 660 1st sampling CKIO 2nd sampling 3rd sampling DRAK (High active) Bus cycle DACK CPU DMAC(Read) DMAC(Write) CPU DMAC(Read) DMAC(Write) Figure 9.17 Cycle-Steal Mode, Level Input (CPU Access: 2 Cycles) 1st sampling CKIO 2nd sampling 3rd sampling DRAK (High active) Bus cycle DACK CPU DMAC(Read) DMAC(Write) CPU DMAC(Read) Figure 9.18 Cycle-Steal Mode, Level Input (CPU Access: 3 Cycles) 1st sampling 2nd sampling 3rd sampling CKIO DRAK (High active) Bus cycle CPU DMAC(Read) DMAC(Write) CPU DMAC(Read) DACK (RD output) Figure 9.19 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DMA RD Access: 4 Cycles) Rev. 4.00, 03/04, page 276 of 660 1st sampling CKIO 2nd sampling is performed, but since is high, per-cycle sampling starts 2nd sampling 3rd sampling is performed, is high, but since per-cycle sampling starts 3rd sampling DRAK (High active) Bus cycle DACK (RD output) CPU DMAC(Read) DMAC(Write) CPU DMAC(Read) DMAC(Write) CPU Figure 9.20 Cycle-Steal Mode, Level input (CPU Access: 2 Cycles, DREQ Input Delayed) 2nd sampling is performed, but since there is no ,4-3 falling edge, per-cycle sampling starts 2nd sampling 3rd sampling is performed, but since there is no ,4-3 falling edge, per-cycle sampling starts 1st sampling CKIO 3rd sampling ,4-3 DRAK (High active) Bus cycle DACK (RD output) CPU High High High High DMAC(Read) DMAC(Write) CPU DMAC(Read) DMAC(Write) CPU Note: When a ,4-3 falling edge is detected, ,4-3 must be high for at least one cycle before the sampling point. Figure 9.21 Cycle-Steal Mode, Edge input (CPU Access: 2 Cycles) 1st sampling CKIO 2nd sampling 3rd sampling DRAK (High active) Bus cycle DACK CPU DMAC(Read) DMAC(Write) DMAC(Read) DMAC(Write) DMAC(Read) Figure 9.22 Burst Mode, Level Input Rev. 4.00, 03/04, page 277 of 660 1st sampling CKIO DRAK (High active) Bus cycle DACK CPU DMAC(Read) DMAC(Write) DMAC(Read) DMAC(Write) DMAC(Read) Figure 9.23 Burst Mode, Edge Input 9.4.6 Source Address Reload Function Channel 2 includes a reload function, in which the value returns to the value set in the SAR_2 for each four transfers by setting the RO bit in CHCR_2 to 1. 16-byte transfer cannot be used. Figure 9.24 shows this operation. Figure 9.25 shows the timing chart of the source address reload function, which is under the following conditions: burst mode, auto request, 16-bit transfer data size, SAR_2 count-up, DAR_2 fixed, reload function on, and usage of only channel 2. DMAC DMAC control RO bit = 1 CHCR_2 Transfer request Count signal DMATCR_2 Reload signal Reload control Reload signal 4 time count SAR_2 Address bus SAR_2 (initial value) Figure 9.24 Source Address Reload Function Diagram Rev. 4.00, 03/04, page 278 of 660 CK Internal address bus Internal data bus SAR_2 DAR_2 SAR_2+2 DAR_2 SAR_2+4 DAR_2 SAR_2+6 DAR_2 SAR_2 SAR_2 data First transfer of channel 2 SAR_2 output DAR_2 output SAR_2+2 data SAR_2+4 data SAR_2+6 data Second transfer SAR_2+2 output DAR_2 output Third transfer SAR_2+4 output DAR_2 output Fourth transfer SAR_2+6 output DAR_2 output Fifth transfer SAR_2 reload SAR_2 output DAR_2 output Figure 9.25 Timing Chart of Source Address Reload Function Even if the transfer data size is 8, 16, or 32 bits, a reload function can be executed. DMATCR_2, which specifies a transfer count, decrements 1 each time a transfer ends regardless of whether a reload function is on or off. Consequently, be sure to specify the value multiple of four in DMATCR_2 when the reload function is on. Specifying other values does not guarantee the operation. Though the counters that count transfers of four times for the reload function are reset by clearing the DME bit in DMAOR or the DE bit in CHCR_2, by setting the transfer end flag (TE bit in CHCR_2) by a DMAC address error, or by inputting NMI, besides by resets, the SAR_2, DAR_2, DMATCR_2 registers are not reset. Therefore, if these sources are generated, the counters that are initialized and are not initialized exist in the DMAC; malfunction will be caused by restarting the DMAC in that state. Consequently, if these sources occur except for setting the TE bit during the usage of the reload function, set SAR_2, DAR_2, and DMATCR_2 again. Rev. 4.00, 03/04, page 279 of 660 9.4.7 DMA Transfer Ending Conditions The DMA transfer ending conditions vary for individual channels ending and all channels ending together. At transfer end, the following conditions are applied except the case where the value set in the DMATCR reaches 0. (a) Cycle-steal mode (external request, internal request, and auto request) When the transfer ending conditions are satisfied, DMAC transfer request acceptance is suspended. The DMAC stops operating after completing the number of transfers that it has accepted until the ending conditions are satisfied. In the cycle-steal mode, the operation is the same regardless of whether the transfer request is detected by the level or at the edge. (b) Burst mode, edge detection (external request, internal request, and auto request) The timing from the point where the ending conditions are satisfied to the point where the DMAC stops operating differs from that in cycle steal mode. In the edge detection in the burst mode, though only one transfer request is generated to start up the DMAC, stop request sampling is performed in the same timing as transfer request sampling in the cycle-steal mode. As a result, the period when stop request is not sampled is regarded as the period when transfer request is generated, and after performing the DMA transfer for this period, the DMAC stops operating. (c) Burst mode, level detection (external request) Same as described in (a). (d) Bus timing when transfers are suspended The transfer is suspended when one transfer ends. Even if transfer ending conditions are satisfied during read in the direct address transfer in the dual address mode, the subsequent write process is executed, and after the transfer in (a) to (c) above has been executed, DMAC operation suspends. Rev. 4.00, 03/04, page 280 of 660 Individual Channel Ending Conditions: There are two ending conditions. A transfer ends when the value of the channel's DMATCR is 0, or when the DE bit of the channel's CHCR is cleared to 0. * When DMATCR is 0: When the DMATCR value becomes 0 and the corresponding channel's DMA transfer ends, the transfer end flag bit (TE) is set in the CHCR. If the IE (interrupt enable) bit has been set, a DMAC interrupt (DEI) is requested to the CPU. This transfer ending does not apply to conditions in (a) to (d) described above. * When DE of CHCR is 0: Software can halt a DMA transfer by clearing the DE bit in the channel's CHCR. The TE bit is not set when this happens. This transfer ending does not apply to conditions in (a) to (d) described above. Conditions for Ending All Channels Simultaneously: Transfers on all channels end when the NMIF or AE bit in the DMAOR is set to 1, or when the DME bit in the DMAOR is cleared to 0. * Transfers ending when the AE bit or NMIF bit is set to 1 in DMAOR: When an NMI interrupt occurs, the AE bit or NMIF bit is set to 1 in the DMAOR and all channels stop their transfers according to the conditions in (a) to (d) described above, and pass the bus right to other bus masters. Consequently, even if the AE bit or NMI bit is set to 1 during transfer, the SAR, DAR, DMATCR are updated. The TE bit is not set. To resume the transfers after DMAC address error exception handling or NMI interrupt exception handling, clear the AE or NMIF bit to 0. At this time, if there are channels that should not be restarted, clear the corresponding DE bit in the CHCR. * Transfers ending when DME is cleared to 0 in DMAOR: Clearing the DME bit to 0 in the DMAOR forcibly stops the transfers on all channels. The TE bit is not set. All channels stop their transfers according to the conditions in (a) to (d) in 9.4.7, DMA Transfer Ending Conditions, as in DMAC address error occurrence or NMI interrupt generation. In this case, the values in SAR, DAR, and DMATCR are also updated. Rev. 4.00, 03/04, page 281 of 660 9.5 Compare Match Timer (CMT) DMAC has an on-chip compare match timer (CMT) to generate DMA transfer request. The CMT has 16-bit counter. Figure 9.26 shows a CMT block diagram. 9.5.1 Feature The CMT has the following features: * Four types of counter input clock can be selected One of four internal clocks (P/4, P/8, P/16, P/64) can be selected. * Generate DMA transfer request when compare match occurs. P/4 P/8 P/16 P/64 CMT Control circuit Clock selection Comparator CMCOR CMCSR CMCNT CMSTR Module bus Bus interface Legend CMSTR: CMCSR: CMCOR: CMCNT: Internal bus Compare match timer start register Compare match timer control/status register Compare match timer constant register Compare match timer counter Figure 9.26 CMT Block Diagram Rev. 4.00, 03/04, page 282 of 660 9.5.2 Register Description The CMT has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Compare match timer start register (CMSTR) * Compare match timer control/status register (CMCSR) * Compare match counter (CMCNT) * Compare match constant register (CMCOR) * Compare Match Timer Start Register (CMSTR) The compare match timer start register (CMSTR) is a 16-bit register that selects whether to operate or halt the channel 0 and channel 1 counter (CMCNT). Bit 15 to 2 Bit Name -- Initial Value All 0 R/W Description R Reserved These bits are always read as 0. The write value should always be 0. 1 0 -- STR0 0 0 R/W Reserved This bit can be read or written. Write 0 when writing. R/W Count start 0 Selects whether to operate or halt compare match timer counter 0. 0: CMCNT0 count operation halted 1: CMCNT0 count operation * Compare Match Timer Control/Status Register (CMCSR) The compare match timer control/status register (CMCSR) is a 16-bit register that indicates the occurrence of compare matches, sets the enable/disable of interrupts, and establishes the clock used for incrementation. Bit 15 to 8 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits always read as 0. The write value should always be 0. Rev. 4.00, 03/04, page 283 of 660 Bit 7 Bit Name CMF Initial Value 0 R/W Description R/(W)* Compare match flag This flag indicates whether CMCNT and CMCOR values have matched or not. 0: CMCNT and CMCOR values have not matched Clearing condition: Write 0 to CMF after reading CMF = 1 1: CMCNT and CMCOR values have matched 6 -- 0 R/W Reserved Both read and write are available. The write value should always be 0. 5 to 2 -- 0 R Reserved These bits always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Clock select 1 and 0 These bits select the clock input to the CMCNT from among the four internal clocks obtained by dividing the system clock (P). When the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the clock selected by CKS1 and CKS0. 00: P /4 01: P /8 10: P /16 11: P /64 Note: * The only value that can be written is 0 to clear the flag. * Compare Match Counter (CMCNT) The compare match counter (CMCNT) is a 16-bit register used as an up-counter. When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the CMCNT value matches that of the CMCOR, the CMCNT is cleared to H'0000 and the CMF flag of the CMCSR is set to 1. The CMCNT0 is initialized to H'0000 by resets. It retains its previous value in standby mode. * Compare Match Constant Register (CMCOR) The compare match constant register (CMCOR) is a 16-bit register that sets the compare match period with the CMCNT. The CMCOR is initialized to H'FFFF by resets. It retains its previous value in standby mode. Rev. 4.00, 03/04, page 284 of 660 9.5.3 Operation * Period Count Operation When an internal clock is selected with the CKS1 and CKS0 bits of the CMCSR register and the STR bit of the CMSTR is set to 1, the CMCNT begins incrementing with the selected clock. When the CMCNT counter value matches that of the CMCOR, the CMCNT counter is cleared to H'0000 and the CMF flag of the CMCSR register is set to 1. The CMCNT counter begins counting up again from H'0000. Figure 9.27 shows the compare match counter operation. CMCNT value Counter cleared by CMCOR compare match CMCOR H'0000 Time Figure 9.27 Counter Operation * CMCNT Count Timing One of four clocks (P/4, P/8, P/16, P/64) obtained by dividing the the system clock (P) can be selected by the CKS1 and CKS0 bits of the CMCSR. Figure 9.28 shows the timing. CK Internal clock CMCNT0 input clock CMCNT0 N-1 N N+1 Figure 9.28 Count Timing Rev. 4.00, 03/04, page 285 of 660 * Compare Match Flag Set Timing The CMF bit of the CMCSR register is set to 1 by the compare match signal generated when the CMCOR register and the CMCNT counter match. The compare match signal is generated upon the final state of the match (timing at which the CMCNT counter matching count value is updated). Consequently, after the CMCOR register and the CMCNT counter match, a compare match signal will not be generated until a CMCNT counter input clock occurs. Figure 9.29 shows the CMF bit set timing. CK CMCNT input clock CMCNT N 0 CMCOR N Compare match signal CMF CMI Figure 9.29 CMF Set Timing * Compare Match Flag Clear Timing The CMF bit of the CMCSR register is cleared by writing 0 to it after reading 1. Figure 9.30 shows the timing when the CMF bit is cleared by the CPU. CMCSR0 write cycle T1 T2 CK CMF Figure 9.30 Timing of CMF Clear by the CPU Rev. 4.00, 03/04, page 286 of 660 9.6 9.6.1 Examples of Use Example of DMA Transfer between A/D Converter and External Memory (Address Reload on) In this example, DMA transfer is performed between the on-chip A/D converter (transfer source) and the external memory (transfer destination) with address reload function on. Table 9.6 shows the transfer conditions and register settings. Table 9.6 Transfer Conditions and Register Settings for Transfer between On-Chip A/D converter and External Memory Register SAR_2 DAR_2 DMATCR_2 CHCR_2 Setting H'04000080 H'00400000 H'00000080 H'00089E35 Transfer Conditions Transfer source: on-chip A/D converter Transfer destination: external memory Number of transfers: 128 (reloading 32 times) Transfer source address: incremented Transfer destination address: decremented Transfer request source: A/D converter Bus mode: burst Transfer unit: long word Interrupt request generated at end of transfer Channel priority order: 0 > 2 > 3 > 1 DMAOR H'0101 When the address reload function is on, the values set in SAR_0 to SAR_3 returns to the initially set value at each four transfers. In this example, when an interrupt request is generated from A/D converter, longword data is read from the register in address H'04000080 in A/D converter, and it is written to external memory address H'00400000. Since longword data has been transferred, the values in SAR_2 and DAR_2 are H'04000084 and H'003FFFFC, respectively. The bus right is maintained and data transfers are successively performed because this transfer is in the burst mode. After four transfers end, fifth and sixth transfers are performed if the address reload function is off, and the value in SAR_2 is incremented from H'0400008C, H'04000090, H'04000094,.... If the address reload function is on, the DMA transfer stops after the fourth transfer ends, the bus request signal to the CPU is cleared. At this time, the value stored in SAR_2 is not incremented from H'0400008C to H'04000090, but returns to the initially set value H'04000080. The value in DAR_2 continues being decremented regardless of whether the address reload function is on or off. As a result, the values in the DMAC are as shown in table 9.7 when the fourth transfer ends, depending on whether the address reload function is on or off. Rev. 4.00, 03/04, page 287 of 660 Table 9.7 Items SAR_2 DAR_2 DMATCR_2 Bus right Values in the DMAC after the Fourth Transfer Ends Address reload on H'04000080 H'003FFFFC H'0000007C Released Stops Not generated Executed Address reload off H'04000090 H'003FFFFC H'0000007C Held Keeps operating Not generated Not executed DMAC operation Interrupt Transfer request source flag clear Notes: 1. An interrupt is generated regardless of whether the address reload function is on or off, if transfers are executed until the value in DMATCR_2 reaches 0 and the IE bit in CHCR_2 has been set to 1. 2. The transfer request source flag is cleared regardless of whether the address reload function is on or off, if transfers are executed until the value in DMATCR_2 reaches 0. 3. Specify the burst mode to use the address reload function. This function may not be correctly executed in the cycle steal mode. 4. Set the value multiple of four in DMATCR_2 to use the address reload function. This function may not be correctly executed if other values are specified. 9.6.2 Example of DMA Transfer between External Memory and SCIF Transmitter (Indirect Address on) In this example, DMA transfer is performed between the external memory specified with the indirect address (transfer source) and the SCIF transmitter (transfer destination) using DMAC channel 3. Table 9.8 shows the transfer conditions and register settings. In addition, the trigger of the number of transmit FIFO data is set to 1 (TTRG1 = TTRG0 = 1 in SCFCR). Rev. 4.00, 03/04, page 288 of 660 Table 9.8 Transfer Conditions and Register Settings for Transfer between External Memory and SCIF Transmitter Register SAR_3 -- -- DAR_3 Setting H'00400000 H'00450000 H'55 H'04000156 Transfer Conditions Transfer source: external memory Value stored in address H'00400000 Value stored in address H'04500000 Transfer destination: On-chip SCIF TDR2 Number of transfers: 10 Transfer source address: incremented Transfer destination address: fixed Transfer request source: SCIF (TXI2) Bus mode: cycle steal Transfer unit: byte No interrupt request generated at end of transfer Channel priority order: 0 > 1 > 2 > 3 DMATCR_3 H'0000000A CHCR_3 H'00011C01 DMAOR H'0001 If the indirect address is on, data stored in the address set in SAR_0 to SAR_3 is not used as transfer source data. In the indirect address, after the value stored in the address set in SAR_0 to SAR_3 is read, that read value is used as an address again, and the value stored in that address is read and stored in the corresponding address set in DAR_0 to DAR_3. In the example shown in table 9.3, when an SCIF transfer request is generated, the DMAC reads the value in address H'00400000 set in SAR_3. Since the value H'00450000 is stored in that address, the DMAC reads the value H'00450000. Next, the DMAC uses that read value as an address again, and reads the value H'55 stored in that address. Then, the DMAC writes the value H'55 to address H'04000156 set in DAR_3; this completes one indirect address transfer. In the indirect address, when data is read first from the address set in SAR_3, the data transfer size is always longword regardless of the settings of the TS0 and the TS1 bits that specify the transfer data size. However, whether the transfer source address is fixed, incremented, or decremented is specified according to the SM0 and the SM1 bits. Therefore, in this example, though the transfer data size is specified as byte, the value in SAR_3 is H'00400004 when one transfer ends. Write operation is the same as that in the normal dual address transfer. Rev. 4.00, 03/04, page 289 of 660 9.7 Cautions 1. CHCR_0 to CHCR_3 can be accessed in any data size. The DMA operation register (DMAOR) must be accessed in byte (eight bits) or word (16 bits); other registers must be accessed in word (16 bits) or longword (32 bits). 2. Before rewriting the RS0 to RS3 bits of CHCR_0 to CHCR_3, first clear the DE bit to 0 (when rewriting CHCR, be sure to clear the DE bit to 0 in advance). 3. Even when the NMI interrupt is input when the DMAC is not operating, the NMIF bit of the DMAOR will be set. 4. When entering the standby mode, the DME bit in DMAOR must be cleared to 0 and the transfers accepted by the DMAC must end. 5. The on-chip peripherals which DMAC can access are SCIF, A/D converter, D/A converter, and I/O ports. Do not access the other peripherals by DMAC. 6. When starting up the DMAC, set CHCR_0 to CHCR_3 or DMAOR last. Specifying other registers last does not guarantee normal operation. 7. Even if the maximum number of transfers is performed in the same channel after the DMATCR_0 to DMATCR_3 count reaches 0 and the DMA transfer ends normally, write 0 to DMATCR_0 to DMATCR_3. Otherwise, normal DMA transfer may not be performed. 8. When using the address reload function, specify the burst mode as a transfer mode. In the cycle-steal mode, normal DMA transfer may not be performed. 9. When using the address reload function, set the value multiple of four in DMATCR_0 to DMATCR_3. Specifying other values does not guarantee normal operation. 10. When detecting an external request at the falling edge, keep the external request pin high when setting the DMAC. 11. Do not access the space ranging from H'4000062 to H'400006F, which is not used in the DMAC. Accessing that space may cause malfunctions. 12. The WAIT signal is ignored in the following cases: A. In 16-byte DMA transfer or dual addressing mode, or when writing data to the external address area B. In 16-byte DMA transfer or single addressing mode, or when transferring data from an external device with DACK to the external address area Rev. 4.00, 03/04, page 290 of 660 Section 10 Clock Pulse Generator (CPG) The clock pulse generator (CPG) supplies all clocks to the processor and controls the power-down modes. A block diagram of the clock pulse generator is shown in figure 10.1. 10.1 Feature The CPG has the following features: * Four clock modes: Selection of 4 clock modes for different frequency ranges, power consumption, direct crystal input, and external clock input are available. * Three clocks generated independently: An internal clock for the CPU, cache, and TLB (I); a peripheral clock (P) for the on-chip supporting modules; and a bus clock (CKIO) for the external bus interface. * Frequency change function: Internal and peripheral clock frequencies can be changed independently using the PLL circuit and divider circuit within the CPG. Frequencies are changed by software using frequency control register (FRQCR) settings. * Power-down mode control: The clock can be stopped for sleep mode and software standby mode and specific modules can be stopped using the module standby function. Rev. 4.00, 03/04, page 291 of 660 Clock pulse generator CAP1 PLL circuit 1 (x 1, 2, 3, 4) CKIO Cycle = Bcyc CAP2 XTAL EXTAL Crystal oscillator PLL circuit 2 (x 1, 4) Divider 2 x1 x 1/2 x 1/3 x 1/4 x 1/6 Divider 1 x1 x 1/2 x 1/3 x 1/4 Internal clock (I) Cycle = Icyc Peripheral clock (P) Cycle = Pcyc Bus clock (B) Cycle = Bcyc CPG control unit Clock frequency control circuit Standby control circuit Standby control MD2 MD1 MD0 FRQCR STBCR Bus interface Legend FRQCR: Frequency control register STBCR: Standby control register Internal bus Figure 10.1 Block Diagram of Clock Pulse Generator Rev. 4.00, 03/04, page 292 of 660 The clock pulse generator blocks function as follows: 1. PLL Circuit 1: PLL circuit 1 doubles, triples, quadruples, or leaves unchanged the input clock frequency from the CKIO terminal. The multiplication rate is set by the frequency control register. When this is done, the phase of the leading edge of the internal clock (I, B, P) is controlled so that it will agree with the phase of the leading edge of the CKIO pin. 2. PLL Circuit 2: PLL circuit 2 leaves unchanged or quadruples the frequency of the crystal oscillator or the input clock frequency coming from the EXTAL pin. The multiplication ratio is fixed by the clock operation mode. The clock operation mode is set by pins MD0, MD1, and MD2. See table 10.3 for more information on clock operation modes. 3. Crystal Oscillator: This oscillator is used when a crystal oscillator element is connected to the XTAL and EXTAL pins. It operates according to the clock operating mode setting. 4. Divider 1: Divider 1 generates a clock at the operating frequency used by the internal clock. The operating frequency can be 1, 1/2, 1/3, or 1/4 times the output frequency of PLL circuit 1, as long as it stays at or above the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. 5. Divider 2: Divider 2 generates a clock at the operating frequency used by the bus clock (B) and peripheral clock (P). The operating frequency of the peripheral clock can be 1, 1/2, 1/3, 1/4, or 1/6 times the output frequency of PLL Circuit 1, as long as it stays at or below the clock frequency of the CKIO pin. The division ratio is set in the frequency control register. 6. Clock Frequency Control Circuit: The clock frequency control circuit controls the clock frequency using the MD2 to MD0 pins and the frequency control register. 7. Standby Control Circuit: The standby control circuit controls the state of the clock pulse generator and other modules during clock switching and sleep/standby modes. 8. Frequency Control Register: The frequency control register has control bits assigned for the following functions: clock output/non-output from the CKIO pin, on/off control of PLL circuit 1, PLL standby, the frequency multiplication ratio of PLL 1, and the frequency division ratio of the internal clock and the peripheral clock. 9. Standby Control Register: The standby control register has bits for controlling the power-down modes. See section 22, Power-Down Modes, for more information. Rev. 4.00, 03/04, page 293 of 660 10.2 Input/Output Pin Table 10.1 lists the CPG pins and their functions. Table 10.1 Clock Pulse Generator Pins and Functions Pin Name Mode control pins Symbol MD0 MD1 MD2 Crystal I/O pins (clock input pins) XTAL EXTAL CKIO I/O I I I O I I/O I I Connects a crystal oscillator. Connects a crystal oscillator. Also used to input an external clock. Inputs or outputs an external clock. Connects capacitor for PLL circuit 1 operation (recommended value 470 pF). Connects capacitor for PLL circuit 2 operation (recommended value 470 pF). Description Set the clock operating mode. Clock I/O pin Capacitor connection pins CAP1 for PLL CAP2 10.3 Clock Operating Modes Table 10.2 shows the relationship between the mode control pin (MD2 to MD0) combinations and the clock operating modes. Table 10.3 shows the usable frequency ranges in the clock operating modes and frequency ranges of the input clock (crystal oscillation). Operation cannot be guaranteed if settings other than those listed in table 10.3 are used. Table 10.2 Clock Operating Modes Pin Values Mode MD2 MD1 MD0 0 0 0 0 Clock I/O Source EXTAL Output CKIO PLL2 On/Off On, multiplication ratio: 1 1 0 0 1 EXTAL CKIO On, multiplication ratio: 4 2 0 1 0 Crystal oscillator 7 -- 1 1 1 CKIO - CKIO On, multiplication ratio: 4 Off On PLL1 output PLL1 On PLL1 output PLL1 On PLL1 output PLL1 (EXTAL) x 4 (Crystal) x 4 (CKIO) PLL1 On/Off On Divider 1 Input Divider 2 Input CKIO Frequency (EXTAL) PLL1 output PLL1 Other than the above Reserved (setting disabled) Rev. 4.00, 03/04, page 294 of 660 Mode 0: An external clock is input from the EXTAL pin and undergoes waveform shaping by PLL circuit 2 before being supplied inside this LSI. The frequency ratio between EXTAL input clock and CKIO output clock is 1:1. An input clock frequency of 25 MHz to 66.67 MHz can be used, and the CKIO frequency range is 25 MHz to 66.67 MHz. Mode 1: An external clock is input from the EXTAL pin and its frequency is multiplied by 4 by PLL circuit 2 before being supplied inside this LSI, allowing a low-frequency external clock to be used. The frequency ratio between EXTAL input clock and CKIO output clock is 1:4. An input clock frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency range is 25 MHz to 66.67 MHz. Mode 2: The on-chip crystal oscillator operates, with the oscillation frequency being multiplied by 4 by PLL circuit 2 before being supplied inside this LSI, allowing a low crystal frequency to be used. The frequency ratio between crystal oscillation and CKIO output clock is 1:4. A crystal oscillation frequency of 6.25 MHz to 16.67 MHz can be used, and the CKIO frequency range is 25 MHz to 66.67 MHz. Mode 7: In this mode, the CKIO pin is an input, an external clock is input to this pin, and undergoes waveform shaping, and also frequency multiplication according to the setting, by PLL circuit 1 before being supplied to this LSI. In modes 0 to 2, the system clock is generated from the output of this LSI's CKIO pin. Consequently, if a large number of Ics are operating synchronized with the clock, the CKIO pin load will be large. This mode, however, assumes a comparatively large-scale system. If a large number of ICs are operating on the clock cycle, a clock generator with a number of low-skew clock outputs can be provided, so that the ICs can operate synchronously by distributing the clocks to each one. As PLL circuit 1 compensates for fluctuations in the CKIO pin load, this mode is suitable for connection of synchronous DRAM. Rev. 4.00, 03/04, page 295 of 660 Table 10.3 Available Combination of Clock Mode and FRQCR Values Clock Mode FRQCR 0 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 1, 2 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 PLL1 ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3) ON (x 3) ON (x 3) ON (x 3) ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3) ON (x 3) ON (x 3) ON (x 3) PLL2 ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 1) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) ON (x 4) Clock Rate* (I:B:P) Input Frequency Range 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 3:1:1 3:1:1/2 1:1:1 1:1:1/2 4:4:4 4:4:2 4:4:1 8:4:4 8:4:2 4:4:4 4:4:2 16:4:4 8:4:4 4:4:4 12:4:4 12:4:2 4:4:4 4:4:2 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 16.67 MHz 6.25 MHz to 16.67 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 16.67 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 16.67 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 11.11 MHz 6.25 MHz to 8.34 MHz 6.25 MHz to 11.11 MHz CKIO Frequency Range 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz Rev. 4.00, 03/04, page 296 of 660 Clock Mode FRQCR 7 H'0100 H'0101 H'0102 H'0111 H'0112 H'0115 H'0116 H'0122 H'0126 H'012A H'A100 H'A101 H'E100 H'E101 PLL1 ON (x 1) ON (x 1) ON (x 1) ON (x 2) ON (x 2) ON (x 2) ON (x 2) ON (x 4) ON (x 4) ON (x 4) ON (x 3) ON (x 3) ON (x 3) ON (x 3) PLL2 OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF Clock Rate* (I:B:P) Input Frequency Range 1:1:1 1:1:1/2 1:1:1/4 2:1:1 2:1:1/2 1:1:1 1:1:1/2 4:1:1 2:1:1 1:1:1 3:1:1 3:1:1/2 1:1:1 1:1:1/2 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz CKIO Frequency Range 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 66.67 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz 25 MHz to 33.34 MHz 25 MHz to 44.44 MHz Note: * Taking input clock as 1 Max. frequency: I = 133.34 MHz, B (CKIO) = 66.67 MHz, P = 33.34 MHz Cautions: 1. The input to divider 1 is the output of the PLL circuit 1: * When PLL circuit 1 is on. 2. The input of divider 2 is the output of the PLL circuit 1. 3. The frequency of the internal clock (I): * The frequency of the internal clock (I) is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 1 when PLL circuit 1 is on. * Do not set the internal clock frequency lower than the CKIO pin frequency. 4. The frequency of the peripheral clock (P): * The frequency of the peripheral clock (P) is the product of the frequency of the CKIO pin, the frequency multiplication ratio of PLL circuit 1, and the division ratio of divider 2. * The peripheral clock frequency should not be set higher than the frequency of the CKIO pin, higher than 33 MHz, or lower than 1/8 the internal clock (I). 5. The output frequency of PLL circuit 1 is the product of the CKIO frequency and the multiplication ratio of PLL circuit 1. 6. x 1, x 2, x 3, or x 4 can be used as the multiplication ratio of PLL circuit 1. x 1, x 1/2, x 1/3, and x 1/4 can be selected as the division ratios of dividers 1 and 2. Set the rate in the frequency control register. The on/off state of PLL circuit 2 and the multiplication ratio are determined by the mode. Rev. 4.00, 03/04, page 297 of 660 10.4 Register Description The CPG includes the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Frequency control register (FRQCR) 10.4.1 Frequency Control Register (FRQCR) The frequency control register (FRQCR) is a 16-bit read/write register used to specify, the frequency multiplication ratio of PLL circuit 1, and the frequency division ratio of the internal clock and the peripheral clock. Only word access can be used on the FRQCR register. The FRQCR register is initialized to H'0102 at a power-on reset by the RESETP pin and retains its previous value at a manual reset or in standby mode. Bit 15 5 4 Bit Name STC2 STC1 STC0 Initial Value R/W 0 0 0 R/W R/W R/W Description Frequency Multiplication Ratio These bits specify the frequency multiplication ratio of PLL circuit 1. 000: x 1 001: x 2 100: x 3 010: x 4 Other than the above: Reserved (Setting prohibited) Note: Do not set the output frequency of PLL circuit 1 higher than 133 MHz. 14 3 2 IFC2 IFC1 IFC0 0 0 0 R/W R/W R/W Internal Clock Frequency Division Ratio These bits specify the frequency division ratio (Divider 1)of the internal clock with respect to the output frequency of PLL circuit 1. 000: x 1 001: x 1/2 100: x 1/3 010: x 1/4 Other than the above: Reserved (Setting prohibited) Note: Do not set the internal clock frequency lower than the CKIO frequency. Rev. 4.00, 03/04, page 298 of 660 Bit 13 1 0 Bit Name PFC2 PFC1 PFC0 Initial Value R/W 0 0 0 R/W R/W R/W Description Peripheral Clock Frequency Division Ratio These bits specify the division ratio (Divider 2)of the peripheral clock frequency with respect to the frequency of the output frequency of PLL circuit 1 or the frequency of the CKIO pin. 000: x 1 001: x 1/2 100: x 1/3 010: x 1/4 101: x 1/6 Other than the above: Reserved (Setting prohibited) Note: Do not set the peripheral clock frequency higher than the frequency of the CKIO pin. 12 to 9, -- 7, 6 8 -- 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 R Reserved This bit is always read as 1. The write value should always be 1. Note: Take enough care because the positions of the bits are not continuous. Rev. 4.00, 03/04, page 299 of 660 10.5 Operation The frequency of the internal clock and peripheral clock can be changed either by changing the multiplication rate of PLL circuit 1 or by changing the division rates of dividers 1 and 2. All of these are controlled by software through the frequency control register. The methods are described below. 10.5.1 Changing the Multiplication Rate A PLL settling time is required when the multiplication rate of PLL circuit 1 is changed. The onchip WDT counts the settling time. Refer to section 11, Watchdog Timer (WDT), for more details. 1. In the initial state, the multiplication rate of PLL circuit 1 is 1. 2. Set a value that will become the specified oscillation settling time in the WDT and stop the WDT. The following must be set: WTCSR register TME bit = 0: WDT stops WTCSR register CKS2 to CKS0 bits: Division ratio of WDT count clock WTCNT counter: Initial counter value 3. Set the desired value in the STC2, STC1 and STC0 bits. The division ratio can also be set in the IFC2 to IFC0 bits and PFC2 to PFC0 bits. 4. The processor pauses internally and the WDT starts incrementing. At this time, the internal (I) and peripheral clocks (P) both stop, and the clock is continuously output to the CKIO pin in clock modes 0 to 2. 5. Supply of the clock that has been set begins at WDT count overflow, and the processor begins operating again. The WDT stops after it overflows. 10.5.2 Changing the Division Ratio The WDT will not count unless the multiplication rate is changed simultaneously. 1. In the initial state, IFC2 to IFC0 = 000 and PFC2 to PFC0 = 010. 2. Set the IFC2, IFC1, IFC0, PFC2, PFC1, and PFC0 bits to the new division ratio. The values that can be set are limited by the clock mode and the multiplication rate of PLL circuit 1. Note that if the wrong value is set, the processor will malfunction. 3. The clock is immediately supplied at the new division ratio. Rev. 4.00, 03/04, page 300 of 660 10.6 Usage Note When Using an External Crystal Oscillator: Place the crystal oscillator, capacitors CL1 and CL2, close to the EXTAL and XTAL pins. To prevent induction from interfering with correct oscillation, use a common grounding point for the capacitors connected to the oscillator, and do not locate a wiring pattern near these components. Avoid crossing signal lines CL1 CL2 EXTAL XTAL This LSI Note: The values for CL1, and CL2 should be determined after consultation with the crystal oscillator manufacturer. Figure 10.2 Points for Attention when Using Crystal Oscillator Decoupling Capacitors: As far as possible, insert a laminated ceramic capacitor of 0.1 to 1 F as a passive capacitor for each VSS/VCC pair. Mount the passive capacitors as close as possible to the SH7706 power supply pins, and use components with a frequency characteristic suitable for the chip's operating frequency, as well as a suitable capacitance value. Digital system VSS/VCC pairs: 11 to 13, 19 to 21, 25 to 27, 37 to 39, 49 to 51, 61 to 63, 84 to 86, 93 to 95, 115 to 117, 137 to 139, 148 to 150, 156 to 158 On-chip oscillator VSS/VCC pairs: 1 to 4, 123 to 125, 126 to 128 When Using a PLL Oscillator Circuit: Keep the wiring from the PLL VCC and VSS connection pattern to the power supply pins short, and make the pattern width large, to minimize the inductance component. Ground the oscillation stabilization capacitors C1 and C2 to VSS (PLL1) and VSS (PLL2), respectively. Place C1 and C2 close to the CAP1 and CAP2 pins and do not locate a wiring pattern in the vicinity. In clock mode 7, connect the EXTAL pin to VCCQ or VSS and leave the XTAL pin open. Rev. 4.00, 03/04, page 301 of 660 Avoid crossing signal lines VCC (PLL2) Power supply CAP2 C2 Vss (PLL2) VCC (PLL1) Vss CAP1 C1 Vss (PLL1) VCC Reference values C1 = 470 pF C2 = 470 pF Figure 10.3 Points for Attention when Using PLL Oscillator Circuit Notes on Wiring Power Supply Pins: To avoid crossing signal lines, wire VCC-PLL1, VCC-PLL2, and VSS-PLL2 as three patterns from the power supply source on the board so that they are independent of digital VCC and VSS. Rev. 4.00, 03/04, page 302 of 660 Section 11 Watchdog Timer (WDT) The WDT is a single-channel timer that counts the clock settling time and is used when clearing software standby mode and temporary standbys, such as frequency changes. It can also be used as an ordinary watchdog timer or interval timer. Figure 11.1 shows a block diagram of the WDT. WDT Standby cancellation Internal reset request Interrupt request Standby control Standby mode Peripheral clock Reset control Clock selection Overflow Divider Clock selector Interrupt control WTCSR Clock WTCNT Bus interface Legend WTCSR: WTCNT: Watchdog timer control/status register Watchdog timer counter Figure 11.1 Block Diagram of the WDT 11.1 Feature The WDT has the following features: * Can be used to ensure the clock setting time: Use the WDT to cancel software standby mode and the temporary standbys that occur when the clock frequency is changed. * Can switch between watchdog timer mode and interval timer mode. * Generates internal resets in watchdog timer mode: Internal resets occur after counter overflow. Selection of power-on reset or manual reset. * Generates interrupts in interval timer mode: Internal timer interrupts occur after counter overflow. * Selection of eight counter input clocks. Eight clocks (x1 to x 1/4096) can be obtained by dividing the peripheral clock. Rev. 4.00, 03/04, page 303 of 660 11.2 Register Description The WDT has two registers that select the clock, switch the timer mode, and perform other functions. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Watchdog timer counter (WTCNT) * Watchdog timer control/status register (WTCSR) 11.2.1 Watchdog Timer Counter (WTCNT) The watchdog timer counter (WTCNT) is an 8-bit read/write register that increments on the selected clock. When an overflow occurs, it generates a reset in watchdog timer mode and an interrupt in interval time mode. The WTCNT is initialized to H'00 only by a power-on reset through the RESETP pin. Use a word access to write to the WTCNT, with H'5A in the upper byte. Use a byte access to read WTCNT. Bit 7 to 0 Bit Name Initial Value R/W All 0 R/W Description 8-bit counter Note: The watchdog timer counter (WTCNT) is more difficult to write to than other registers to prevent from the erroneous writing to the register. Refer to section 11.2.3 Notes on Register Access. 11.2.2 Watchdog Timer Control/Status Register (WTCSR) The watchdog timer control/status register (WTCSR) is an 8-bit read/write register composed of bits to select the clock used for the count, bits to select the timer mode, and overflow flags. The WTCSR is initialized to H'00 only by a power-on reset through the RESETP pin. When a WDT overflow causes an internal reset, the WTCSR retains its value. When used to count the clock settling time for canceling a software standby, it retains its value after counter overflow. Use a word access to write to the WTCSR, with H'A5 in the upper byte. Use a byte access to read WTCSR. Rev. 4.00, 03/04, page 304 of 660 Bit 7 Bit Name TME Initial Value R/W 0 R/W Description Timer Enable Starts and stops timer operation. Clear this bit to 0 when using the WDT in software standby mode or when changing the clock frequency. 0: Timer disabled: Count-up stops and WTCNT value is retained 1: Timer enabled 6 WT/IT 0 R/W Timer Mode Select Selects whether to use the WDT as a watchdog timer or an interval timer. 0: Use as interval timer 1: Use as watchdog timer Note: If WT/IT is modified when the WDT is running, the up-count may not be performed correctly. 5 RSTS 0 R/W Reset Select Selects the type of reset when the WTCNT overflows in watchdog timer mode. In interval timer mode, this setting is ignored. 0: Power-on reset 1: Manual reset 4 WOVF 0 R/W Watchdog Timer Overflow Indicates that the WTCNT has overflowed in watchdog timer mode. This bit is not set in interval timer mode. 0: No overflow 1: WTCNT has overflowed in watchdog timer mode 3 IOVF 0 R/W Interval Timer Overflow Indicates that the WTCNT has overflowed in interval timer mode. This bit is not set in watchdog timer mode. 0: No overflow 1: WTCNT has overflowed in interval timer mode Rev. 4.00, 03/04, page 305 of 660 Bit 2 to 0 Bit Name CKS2 to CKS0 Initial Value R/W 0 R/W Description Clock Select 2 to 0 These bits select the clock to be used for the WTCNT count from the eight types obtainable by dividing the peripheral clock. The overflow period in the table is the value when the peripheral clock (P) is 15 MHz. Clock Division Ratio Overflow Period (when P = 15 MHz) 000: 1 001: 1/4 010: 1/16 011: 1/32 100: 1/64 101: 1/256 110: 1/1024 111: 1/4096 17 s 68 s 273 s 546 s 1.09 ms 4.36 ms 17.48 ms 69.91 ms Note: If bits CKS2 to CKS0 are modified when the WDT is running, the up-count may not be performed correctly. Ensure that these bits are modified only when the WDT is not running. Note: The watchdog timer control/status register (WTCSR) is more difficult to write to than other registers to prevent from the erroneous writing to the register. Refer to 11.2.3, Notes on Register Access. 11.2.3 Notes on Register Access The WTCNT and WTCSR are more difficult to write to than other registers. The procedure for writing to these registers are given below. Writing to WTCNT and WTCSR: These registers must be written by a word transfer instruction. They cannot be written by a byte or longword transfer instruction. When writing to WTCNT, set the upper byte to H'5A and transfer the lower byte as the write data, as shown in figure 11.2. When writing to WTCSR, set the upper byte to H'A5 and transfer the lower byte as the write data. This transfer procedure writes the lower byte data to WTCNT or WTCSR. WTCNT write Address: H'FFFFFF84 15 H'5A 8 7 Write data 0 WTCSR write Address: H'FFFFFF86 15 H'A5 8 7 Write data 0 Figure 11.2 Writing to WTCNT and WTCSR Rev. 4.00, 03/04, page 306 of 660 11.3 11.3.1 Operation Canceling Software Standbys The WDT can be used to cancel software standby mode with an NMI or other interrupts. The procedure is described below. (The WDT does not run when resets are used for canceling, so keep the RESETP pin or RESETM pin low until the clock stabilizes.) 1. Before transitioning to software standby mode, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits in WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. Move to software standby mode by executing a SLEEP instruction to stop the clock. 4. The WDT starts counting by detecting the edge change of the NMI signal or detecting interrupts. 5. When the WDT count overflows, the CPG starts supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 6. Since the WDT continues counting from H'00, set the STBY bit in the STBCR register to 0 in the interrupt processing program and this will stop the WDT. When the STBY bit remains 1, the SH7706 again enters the standby mode when the WDT has counted up to H'80. This standby mode can be canceled by power-on resets. 11.3.2 Changing the Frequency To change the frequency used by the PLL, use the WDT. When changing the frequency only by switching the divider, do not use the WDT. 1. Before changing the frequency, always clear the TME bit in WTCSR to 0. When the TME bit is 1, an erroneous reset or interval timer interrupt may be generated when the count overflows. 2. Set the type of count clock used in the CKS2 to CKS0 bits of WTCSR and the initial values for the counter in the WTCNT counter. These values should ensure that the time till count overflow is longer than the clock oscillation settling time. 3. When the frequency control register (FRQCR) is written, the clock stops and the processor enters standby mode temporarily. The WDT starts counting. 4. When the WDT count overflows, the CPG resumes supplying the clock and the processor resumes operation. The WOVF flag in WTCSR is not set when this happens. 5. The counter stops at the values H'00 to H'01. The stop value depends on the clock ratio. 6. Confirm that the value of WTCNT is H'00 before writing WTCNT, when WTCNT is written after the frequency change. Rev. 4.00, 03/04, page 307 of 660 11.3.3 Using Watchdog Timer Mode 1. Set the WT/IT bit in the WTCSR register to 1, set the reset type in the RSTS bit, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in watchdog timer mode. 3. While operating in watchdog timer mode, rewrite the counter periodically to H'00 to prevent the counter from overflowing. 4. When the counter overflows, the WDT sets the WOVF flag in WTCSR to 1 and generates the type of reset specified by the RSTS bit. The counter then resumes counting. When a reset occurs, and a high level is output from the STATUS0 and STATUS1 pins. The signal output period is about one cycle of the count clock for power-on reset, and about five cycles of the peripheral clock for manual reset. 11.3.4 Using Interval Timer Mode When operating in interval timer mode, interval timer interrupts are generated at every overflow of the counter. This enables interrupts to be generated at set periods. 1. Clear the WT/IT bit in the WTCSR register to 0, set the type of count clock in the CKS2 to CKS0 bits, and set the initial value of the counter in the WTCNT counter. 2. Set the TME bit in WTCSR to 1 to start the count in interval timer mode. 3. When the counter overflows, the WDT sets the IOVF flag in WTCSR to 1 and an interval timer interrupt request is sent to INTC. The counter then resumes counting. Rev. 4.00, 03/04, page 308 of 660 Section 12 Timer Unit(TMU) This LSI uses a three-channel (channels 0 to 2) 32-bit timer unit (TMU). Figure 12.1 shows a block diagram of the TMU. 12.1 Feature The TMU has the following features: * Each channel is provided with an auto-reload 32-bit down counter * Channel 2 is provided with an input capture function * All channels are provided with 32-bit constant registers and 32-bit down counters that can be read or written to at any time * All channels generate interrupt requests when the 32-bit down counter underflows (H'00000000 H'FFFFFFFF) * Allows selection between 6 counter input clocks: External clock (TCLK), on-chip RTC output clock (16 kHz), P/4, P/16, P/64, P/256. (P is the internal clock for peripheral modules.) Note: See section 10, Clock Pulse Generator (CPG), for more information. * All channels can operate when this LSI is in software standby mode: When the RTC output clock is being used as the counter input clock, this LSI is still able to count in software standby mode. * Synchronized read: TCNT is a sequentially changing 32-bit register. Since the peripheral module used has an internal bus width of 16 bits, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. To correct the discrepancy in the counter read value caused by this time lag, a synchronization circuit is built into the TCNT so that the entire 32-bit data in the TCNT can be read at once. * The maximum operating frequency of the 32-bit counter is 2 MHz on all channels: Operate the SH7706 so that the clock input to the timer counters of each channel (obtained by dividing the external clock and internal clock with the prescaler) does not exceed the maximum operating frequency. Rev. 4.00, 03/04, page 309 of 660 P Prescaler TOCR TCLK RTCCLK Clock controller TSTR Ch. 0 TCR_0 Counter controller TCNT_0 TCOR_0 TUNI0 Interrupt controller TCR_1 Counter controller TCNT_1 TUNI1 Interrupt controller Ch. 2 TCOR_1 TCR_2 Counter controller TCPR_2 TCNT_2 TUNI2 TICPI2 Legend TOCR: Timer output control register TSTR: Timer start register TCR_n: Timer control register (n: 0, 1, 2) Interrupt controller TCOR_2 Module bus Ch. 1 TMU TCNT_n: 32-bit timer counter TCOR_n: 32-bit timer constant register TCPR_2: 32-bit input capture register Figure 12.1 TMU Block Diagram Rev. 4.00, 03/04, page 310 of 660 Internal bus Bus interface 12.2 Input/Output Pin Table 12.1 shows the pin configuration of the TMU. Table 12.1 Pin Configuration Channel Pin I/O I/O Description External clock input pin/input capture control input pin/realtime clock (RTC) output pin Clock input/clock output TCLK 12.3 Register Description The TMU has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Timer output control register (TOCR) * Timer start register (TSTR) * Timer constant register 0 (TCOR_0) * Timer counter 0 (TCNT_0) * Timer control register 0 (TCR_0) * Timer constant register 1 (TCOR_1) * Timer counter 1 (TCNT_1) * Timer control register 1 (TCR_1) * Timer constant register 2 (TCOR_2) * Timer counter 2 (TCNT_2) * Timer control register 2 (TCR_2) * Input capture register 2 (TCPR_2) Rev. 4.00, 03/04, page 311 of 660 12.3.1 Timer Output Control Register (TOCR) TOCR is an 8-bit read/write register that selects whether to use the external TCLK pin as an external clock or an input capture control usage input pin, or an output pin for the on-chip RTC output clock. TOCR is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode. Bit 7 to 1 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 0 TCOE 0 R/W Timer Clock Pin Control Selects use of the timer clock pin (TCLK) as an external clock output pin or input pin for input capture control for the on-chip timer, or as an output pin for the on-chip RTC output clock. As the TCLK pin is multiplexed as the PTE6 pin, when the TCLK pin is used, bits PE6MD1 and PH7MD0 in the PECR register should be set to 00 (Other function). 0: Timer clock pin (TCLK) used as external clock input or input capture control input pin for the on-chip timer 1: Timer clock pin (TCLK) used as output pin for onchip RTC output clock Rev. 4.00, 03/04, page 312 of 660 12.3.2 Timer Start Register (TSTR) TSTR is an 8-bit read/write register that selects whether to run or halt the timer counters (TCNT_0 to TCNT_2) for channels 0 to 2. TSTR is initialized to H'00 by a power-on reset or manual reset, but is not initialized in standby mode when the input clock selected for the channel is the on-chip RTC clock (RTCCLK). It is initialized in standby mode, changing the multiplying ratio of PLL circuit 1 or MSTP2 bit in STBCR is set to a logic one only when an external clock (TCLK) or the peripheral clock (P) is used as the input clock. Bit 7 to 3 Bit Name -- Initial Value R/W Description All 0 R Reserved These bits are always read 0. The write value should always be 0. 2 STR2 0 R/W Counter Start 2 Selects whether to run or halt timer counter 2 (TCNT_2). 0: Halt TCNT_2 count 1: Start TCNT_2 counting 1 STR1 0 R/W Counter Start 1 Selects whether to run or halt timer counter 1 (TCNT_1). 0: Halt TCNT_1 count 1: Start TCNT_1 counting 0 STR0 0 R/W Counter Start 0 Selects whether to run or halt timer counter 0 (TCNT_0). 0: Halt TCNT_0 count 1: Start TCNT_0 counting Rev. 4.00, 03/04, page 313 of 660 12.3.3 Timer Control Registers 0 to 2 (TCR_0 to TCR_2) The timer control registers (TCR_0 to TCR_2) control the timer counters (TCNT_0 to TCNT_2) and interrupts. The TMU has three TCR_0 to TCR_2 registers for each channel. The TCR_0 to TCR_2R registers are 16-bit read/write registers that control the issuance of interrupts when the flag indicating timer counter (TCNT_0 to TCNT_2) underflow has been set to 1, and also carry out counter clock selection. When the external clock has been selected, they also select its edge. Additionally, TCR_2 controls the channel 2 input capture function and the issuance of interrupts during input capture. The TCR_0 to TCR_2 are initialized to H'0000 by a power-on reset and manual reset. They are not initialized in standby mode. In cases of Channel 0 and 1: Bit 15 to 9 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 8 UNF 0 R/W Underflow Flag Status flag that indicates occurrence of a TCNT_0 and TCNT_1 underflow. 0: TCNT has not underflowed. [Clearing condition] When 0 is written to UNF 1: TCNT has underflowed. [Setting condition] When TCNT_0 and TCNT_1 underflows* Note: * Contents do not change when 1 is written to UNF. 7, 6 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 5 UNIE 0 R/W Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT_0 and TCNT_1 underflow has been set to 1. 0: Interrupt due to UNF (TUNI) is not enabled. 1: Interrupt due to UNF (TUNI) is enabled. Rev. 4.00, 03/04, page 314 of 660 Bit 4 3 Bit Name CKEG1 CKEG0 Initial Value R/W 0 0 R/W R/W Description Clock Edge 1 and 0 These bits select the external clock edge when the external clock is selected, or when the input capture function is used. 00: Count/capture register set on rising edge 01: Count/capture register set on falling edge 1X: Count/capture register set on both rising and falling edge Note: X: Don't care 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescalers 2 to 0 These bits select the TCNT_0 and TCNT_1 count clock. 000: Internal clock: count on P/4 001: Internal clock: count on P/16 010: Internal clock: count on P/64 011: Internal clock: count on P/256 100: Internal clock: count on clock output of on-chip RTC (RTCCLK) 101: External clock: count on TCLK pin input 110: Reserved (Setting prohibited) 111: Reserved (Setting prohibited) Rev. 4.00, 03/04, page 315 of 660 In case of Channel 2: Bit 15 to 10 Bit Name -- Initial Value R/W All 0 R Description Reserved These bits are always read as 0. The write value should always be 0. 9 ICPF 0 R Input Capture Interrupt Flag A function of channel 2 only: the flag is set when input capture is requested via the TCLK pin. 0: No input capture request has been issued. Clearing condition: When 0 is written to ICPF 1: Input capture has been requested via the TCLK pin. Setting condition: When an input capture is requested via the TCLK pin* Note: * Contents do not change when 1 is written to ICPF. 8 UNF 0 R/W Underflow Flag Status flag that indicates occurrence of a TCNT_2 underflow. 0: TCNT has not underflowed. Clearing condition: When 0 is written to UNF 1: TCNT has underflowed. Setting condition: When TCNT_2 underflows* Note: * Contents do not change when 1 is written to UNF. 7 6 ICPE1 ICPE0 0 0 R/W R/W Input Capture Control A function of channel 2 only: determines whether the input capture function can be used, and when used, whether or not to enable interrupts. When using this input capture function it is necessary to set the TCLK pin to input mode with the TCOE bit in the TOCR register. Additionally, use the CKEG bit to designate use of either the rising or falling edge of the TCLK pin to set the value of TCNT_2 in TCPR_2. 00: Input capture function is not used. 01: Reserved (Setting prohibited) 10: Input capture function is used. Interrupt due to ICPF (TICPI2) are not enabled. 11: Input capture function is used. Interrupt due to ICPF (TICPI2) are enabled. Rev. 4.00, 03/04, page 316 of 660 Bit 5 Bit Name UNIE Initial Value R/W 0 R/W Description Underflow Interrupt Control Controls enabling of interrupt generation when the status flag (UNF) indicating TCNT_2 underflow has been set to 1. 0: Interrupt due to UNF (TUNI) is not enabled. 1: Interrupt due to UNF (TUNI) is enabled. 4 3 CKEG1 CKEG0 0 0 R/W R/W Clock Edge These bits select the external clock edge when the external clock is selected, or when the input capture function is used. 00: Count/capture register set on rising edge 01: Count/capture register set on falling edge 1X: Count/capture register set on both rising and falling edge Note: X: Don't care. 2 1 0 TPSC2 TPSC1 TPSC0 0 0 0 R/W R/W R/W Timer Prescalers These bits select the TCNT_2 count clock. 000: Internal clock: count on P/4 001: Internal clock: count on P/16 010: Internal clock: count on P/64 011: Internal clock: count on P/256 100: Internal clock: count on clock output of on-chip RTC (RTCCLK) 101: External clock: count on TCLK pin input 110: Reserved (Setting prohibited) 111: Reserved (Setting prohibited) 12.3.4 Timer Constant Registers 0 to 2 (TCOR_0 to TCOR_2) TCOR_0 to TCOR_2 are specified the setting value for TCNT_0 to TCNT_2 when TCNT_0 to TCNT_2 are underflowed. TMU has 3 timer constant registers, one for each channel. TCOR_0 to TCOR_2 is a 32-bit read/write register. TCOR is initialized to H'FFFFFFFF by a power-on reset or manual reset; it is not initialized in standby mode, and retains its contents. Rev. 4.00, 03/04, page 317 of 660 12.3.5 Timer Counters 0 to 2 (TCNT_0 to TCNT_2) TCNT counts down according to the input of a clock. The timer counters are 32-bit read/write registers. The TMU has three timer counters, one for each channel.The clock input is selected using the TPSC2 to TPSC0 bits in the TCR_0 to TCR_2. When a TCNT count-down results in an underflow (H'00000000 H'FFFFFFFF), the underflow flag (UNF) in the timer control register (TCR) of the relevant channel is set. The TCOR value is simultaneously set in TCNT itself and the count-down continues from that value. Because the internal bus for this LSI on-chip supporting modules is 16 bits wide, a time lag can occur between the time when the upper 16 bits and lower 16 bits are read. Since TCNT counts sequentially, this time lag can create discrepancies between the data in the upper and lower halves. To correct the discrepancy, a buffer register is connected to TCNT so that upper and lower halves are not read separately. The entire 32-bit data in TCNT can thus be read at once. TCNT is initialized to H'FFFFFFFF by a power-on reset or manual reset; it is not initialized in standby mode, and retains its contents. 12.3.6 Input Capture Register 2 (TCPR_2) The input capture register (TCPR_2) is a read-only 32-bit register built only into timer 2. Control of TCPR_2 setting conditions due to the TCLK pin is affected by the input capture function bits (ICPE1/ICPE2 and CKEG1/CKEG0) in TCR2. When a TCPR_2 setting indication due to the TCLK pin occurs, the value of TCNT_2 is copied into TCPR_2. TCNT_2 is not initialized by a power-on reset or manual reset, or in standby mode. Rev. 4.00, 03/04, page 318 of 660 12.4 Operation Each of three channels has a 32-bit timer counter (TCNT_0 to TCNT_2) and a 32-bit timer constant register (TCOR_0 to TCOR_2). The TCNT counts down. The auto-reload function enables synchronized counting and counting by external events. Channel 2 has an input capture function. 12.4.1 Counter Operation When the STR0 to STR2 bits in TSTR are set to 1, the corresponding timer counter (TCNT) starts counting. When a TCNT underflows, the UNF flag of the corresponding timer control register (TCR) is set. At this time, if the UNIE bit in TCR is 1, an interrupt request is sent to the CPU. Also at this time, the value is copied from TCOR to TCNT and the down-count operation is continued. * An example of the count operation setting flow The count operation is shown in figure 12.2. Select operation Select counter clock (1) (1) Select the counter clock with the TPSC0-TPSC2 bits in the timer control register. If the external clock is selected, set the TCLK pin to input mode with the TOCE bit in TOCR, and select its edge with the CKEG1 and CKEG0 bits in the timer control register. (2) Use the UNIE bit in the timer control register to set whether to generate an interrupt when timer counter underflows. (3) When using the input capture function, set the ICPE bits in the timer control register, including the choice of whether or not to use the interrupt function (channel 2 only). (4) Set a value in the timer constant register (the cycle is the set value plus 1). (5) Set the initial value in the timer counter. Set underflow interrupt generation (2) When using input capture function Set interrupt generation (3) Set timer constant register (4) Initialize timer counter (5) (6) Set the STR bit in the timer start register to 1 to start operation. Start counting Note: (6) When an interrupt has been generated, clear the flag in the interrupt handler that caused it. If interrupts are enabled without clearing the flag, another interrupt will be generated. Figure 12.2 Setting the Count Operation Rev. 4.00, 03/04, page 319 of 660 * Auto-reload count operation Figure 12.3 shows the TCNT auto-reload operation. TCOR value set to TCNT during underflow TCNT value TCOR H'00000000 Time STR0 to STR2 UNF Figure 12.3 Auto-Reload Count Operation * TCNT count timing 1. Internal Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select whether peripheral module clock P or one of the four internal clocks created by dividing it is used (P/4, P/16, P/64, P/256). Figure 12.4 shows the timing. P Internal clock Timer counter input clock TCNT N+1 N N-1 Figure 12.4 Count Timing when Internal Clock Is Operating Rev. 4.00, 03/04, page 320 of 660 2. External Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select the external clock (TCLK) as the timer clock. Use the CKEG1 and CKEG0 bits in TCR to select the detection edge. Rise, fall or both may be selected. The pulse width of the external clock must be at least 1.5 peripheral module clock cycles for single edges or 2.5 peripheral module clock cycles for both edges. A shorter pulse width will result in accurate operation. Figure 12.5 shows the timing for both-edge detection. P External clock input pin (TCLK) TCNT input clock TCNT N+1 N N-1 Figure 12.5 Count Timing when External Clock is Operating (Both Edges Detected) 3. On-Chip RTC Clock Operation: Set the TPSC2 to TPSC0 bits in TCR to select the on-chip RTC clock as the timer clock. Figure 12.6 shows the timing. RTC output clock TCNT input clock TCNT N+1 N N-1 Figure 12.6 Count Timing when On-Chip RTC Clock Is Operating Rev. 4.00, 03/04, page 321 of 660 12.4.2 Input Capture Function Channel 2 has an input capture function (figure 12.7). When using the input capture function, set the TCLK pin to input mode with the TCOE bit in the timer output control register (TOCR) and set the timer operation clock to internal clock or on-chip RTC clock with the TPCS2 to TPCS0 bits in the timer control register (TCR_2). Also, designate use of the input capture function and whether to generate interrupts on using it with the IPCE1 and IPCE0 bits in TCR_2, and designate the use of either the rising or falling edge of the TCLK pin to set the timer counter (TCNT_2) value into the input capture register (TCPR_2) with the CKEG1 and CKEG0 bits in TCR_2. The input capture function cannot be used in standby mode. TCNT_2 value TCOR_2 TCOR_2 value set to TCNT_2 during underflow H'00000000 TCLK Time TCPR_2 Set TCNT_2 value ICPI Figure 12.7 Operation Timing when Using the Input Capture Function (Using TCLK Rising Edge) Rev. 4.00, 03/04, page 322 of 660 12.5 Interrupts There are two sources of TMU interrupts: underflow interrupts (TUNI) and interrupts when using the input capture function (TICPI2). 12.5.1 Status Flag Set Timing UNF is set to 1 when the TCNT underflows. Figure 12.8 shows the timing. P TCNT Underflow signal H'00000000 TCOR value UNF TUNI Figure 12.8 UNF Set Timing 12.5.2 Status Flag Clear Timing The status flag can be cleared by writing 0 from the CPU. Figure 12.9 shows the timing. TCR write cycle T1 P Peripheral address bus UNF, ICPF TCR address T2 T3 Figure 12.9 Status Flag Clear Timing Rev. 4.00, 03/04, page 323 of 660 12.5.3 Interrupt Sources and Priorities The TMU produces underflow interrupts for each channel. When the interrupt request flag and interrupt enable bit are both set to 1, the interrupt is requested. Codes are set in the exception event register (INTEVT, INTEVT2) for these interrupts and interrupt processing occurs according to the codes. The relative priorities of channels can be changed using the interrupt controller (see section 4, Exception Processing, and section 6, Interrupt Controller (INTC)). Table 12.2 lists TMU interrupt sources. Table 12.2 TMU Interrupt Sources Channel 0 1 2 Interrupt Source TUNI0 TUNI1 TUNI2 TICPI2 Description Underflow interrupt 0 Underflow interrupt 1 Underflow interrupt 2 Input capture interrupt 2 Low Priority High 12.6 12.6.1 Usage Note Writing to Registers Synchronization processing is not performed for timer counting during register writes. When writing to registers, always clear the appropriate start bits for the channel (STR2 to STR0) in the timer start register (TSTR) to halt timer counting. 12.6.2 Reading Registers Synchronization processing is performed for timer counting during register reads. When timer counting and register read processing are performed simultaneously, the register value before TCNT counting down (with synchronization processing) is read. Rev. 4.00, 03/04, page 324 of 660 Section 13 Realtime Clock (RTC) This LSI has a realtime clock (RTC) with its own 32.768-kHz crystal oscillator. A block diagram of the RTC is shown in figure 13.1. 13.1 Feature The RTC has following features: * Clock and calendar functions (BCD display): seconds, minutes, hours, date, day of the week, month, and year * 1-Hz to 64-Hz timer (binary display) * Start/stop function * 30-second adjust function * Alarm interrupt: frame comparison of seconds, minutes, hours, date, day of the week, and month can be used as conditions for the alarm interrupt * Cyclic interrupts: the interrupt cycle may be 1/256 second, 1/64 second, 1/16 second, 1/4 second, 1/2 second, 1 second, or 2 seconds * Carry interrupt: a carry interrupt indicates when a carry occurs during a counter read * Automatic leap year correction Rev. 4.00, 03/04, page 325 of 660 Externally connected circuit EXTAL2 Reset Oscillator circuit XTAL2 32.768 kHz Prescaler (/ 2) 16.384 kHz RTCCLK Prescaler (/ 128) 128 Hz 30second ADJ RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT ATI PRI RSECAR RMINAR CUI Carry detection circuit RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 Legend R64CNT: RSECCNT: RMINCNT: RHRCNT: RWKCNT: RDAYCNT: RMONCNT: RYRCNT: 64-Hz counter Second counter Minute counter Hour counter Day of the week counter Date counter Month counter Year counter RSECAR: RHRAR: RMINAR: RWKAR: RDAYAR: RMONAR: RCR1: RCR2: Module bus Interrupt control circuit Comparator RTC Second alarm register Minute alarm register Hour alarm register Day of the week alarm register Date alarm register Month alarm register RTC control register 1 RTC control register 2 Figure 13.1 RTC Block Diagram Rev. 4.00, 03/04, page 326 of 660 Internal bus R64CNT Bus interface 13.2 Input/Output Pin Table 13.1 shows the RTC pin configuration. Table 13.1 RTC Pin Configuration Pin RTC oscillator crystal pin RTC oscillator crystal pin Clock input/clock output Abbreviation I/O EXTAL2 XTAL2 TCLK I O I/O Description Connects crystal to RTC oscillator* Connects crystal to RTC oscillator* 2 2 External clock input pin/input capture control input pin/realtime clock (RTC) output pin (shared by TMU) Dedicated power-supply pin for RTC* Dedicated GND pin for RTC* 1 1 Dedicated power-supply pin for RTC VCC-RTC Dedicated GND pin for RTC VSS-RTC -- -- Notes: 1. Except for in hardware standby mode, even if only the RTC is used (software standby mode), power must be supplied to all power supply pins, including these RTC power supply pins. In hardware standby mode, it is possible to stop supplying power to the power supply pins except for the RTC power supply pins. 2. Pull-up (Vcc) EXTAL2, and open (NC) XTAL2 when the RTC is not used. 13.3 Register Description RTC has the registers listed below. Refer to section 23, List ot Registers, for more detail of the address and access size. * * * * * * * * * * * * * * * * 64-Hz counter (R64CNT) Second counter (RSECCNT) Minute counter (RMINCNT) Hour counter (RHRCNT) Day of week counter (RWKCNT) Date counter (RDAYCNT) Month counter (RMONCNT) Year counter (RYRCNT) Second alarm register (RSECAR) Minute alarm register (RMINAR) Hour alarm register (RHRAR) Day of week alarm register (RWKAR) Date alarm register (RDAYAR) Month alarm register (RMONAR) RTC control register 1 (RCR1) RTC control register 2 (RCR2) Rev. 4.00, 03/04, page 327 of 660 13.3.1 64-Hz Counter (R64CNT) The 64-Hz counter (R64CNT) is an 8-bit read-only register that indicates the state of the RTC divider circuit between 64 Hz and 1 Hz. R64CNT is reset to H'00 by setting the RESET bit in RCR2 or the ADJ bit in RCR2 to 1. R64CNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 6 to 0 Bit Name Initial Value R/W 0 R R Description Always read as 0. 64Hz counter Each bit (bits 6 to 0) indicates the state of the RTC divider circuit between 64 and 1Hz. Bit 6: 5: 4: 3: 2: 1: 0: Frequency 1Hz 2Hz 4Hz 8Hz 16Hz 32Hz 64Hz 13.3.2 Second Counter (RSECCNT) The second counter (RSECCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded second section of the RTC. The count operation is performed by a carry for each second of the 64-Hz counter. The range of second can be set is 00 to 59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RSECCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 6 to 4 3 to 0 Bit Name Initial Value R/W 0 R R/W R/W Description Always read as 0. Counter for 10-unit of second in the BCD-code. The range can be set from 0 to 5 (decimal). Counter for 1-unit of second in the BCD-code. The range can be set from 0 to 9 (decimal). Rev. 4.00, 03/04, page 328 of 660 13.3.3 Minute Counter (RMINCNT) The minute counter (RMINCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded minute section of the RTC. The count operation is performed by a carry for each minute of the second counter. The range of minute can be set is 00 to 59 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RMINCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 6 to 4 3 to 0 Bit Name Initial Value R/W 0 R R/W R/W Description Always read as 0. Counter for 10-unit of minute in the BCD-code. The range can be set from 0 to 5 (decimal). Counter for 1-unit of minute in the BCD-code. The range can be set from 0 to 9 (decimal). 13.3.4 Hour Counter (RHRCNT) The hour counter (RHRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded hour section of the RTC. The count operation is performed by a carry for each 1 hour of the minute counter. The range of hour can be set is 00 to 23 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RHRCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7, 6 5, 4 3 to 0 Bit Name Initial Value R/W All 0 R R/W R/W Description Always read as 0. Counter for 10-unit of hour in the BCD-code. The range can be set from 0 to 2 (decimal). Counter for 1-unit of hour in the BCD-code. The range can be set from 0 to 9 (decimal). Rev. 4.00, 03/04, page 329 of 660 13.3.5 Day of the Week Counter (RWKCNT) The day of the week counter (RWKCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded day of week section of the RTC. The count operation is performed by a carry for each day of the date counter. The range for day of the week can be set is 0 to 6 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RWKCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 to 3 2 to 0 Bit Name Initial Value All 0 R/W Description R Always read as 0. R/W Counter for the day of week in the BCD-code. The range can be set from 0 to 6 (decimal). Code 0: 1: 2: 3: 4: 5: 6: Day of Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Rev. 4.00, 03/04, page 330 of 660 13.3.6 Date Counter (RDAYCNT) The date counter (RDAYCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded date section of the RTC. The count operation is performed by a carry for each day of the hour counter. The range of date can be set is 01 to 31 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RDAYCNT is not initialized by a power-on reset or manual reset, or in standby mode. The RDAYCNT range that can be set changes with each month and in leap years. Please confirm the correct setting. Bit 7, 6 5, 4 3 to 0 Bit Name Initial Value All 0 R/W R R/W R/W Description Always read as 0. Counter for 10-unit of date in the BCD-code. The range can be set from 0 to 3 (decimal). Counter for 1-unit of date in the BCD-code. The range can be set from 0 to 9 (decimal). 13.3.7 Month Counter (RMONCNT) The month counter (RMONCNT) is an 8-bit read/write register used for setting/counting in the BCD-coded month section of the RTC. The count operation is performed by a carry for each month of the date counter. The range of month can be set is 00 to 12 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2. RMONCNT is not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 to 5 4 3 to 0 Bit Name Initial Value All 0 R/W R R/W R/W Description Always read as 0. Counter for 10-unit of month in the BCD-code. The range can be set from 0 to 1 (decimal). Counter for 1-unit of month in the BCD-code. The range can be set from 0 to 9 (decimal). Rev. 4.00, 03/04, page 331 of 660 13.3.8 Year Counter (RYRCNT) The year counter (RYRCNT) is an 8-bit read/write register used for setting/counting in the BCDcoded year section of the RTC. The least significant 2 digits of the western calendar year are displayed. The count operation is performed by a carry for each year of the month counter. The range for year can be set is 00 to 99 (decimal). Errant operation will result if any other value is set. Carry out write processing after halting the count operation with the START bit in RCR2 or using a carry flag. RYRCNT is not initialized by a power-on reset or manual reset, or in standby mode. Leap years are recognized by dividing the year counter value by 4 and obtaining a fractional result of 0. Bit 7 to 4 3 to 0 Bit Name Initial Value R/W R/W R/W Description Counter for 10-unit of year in the BCD-code. The range can be set from 0 to 9 (decimal). Counter for 1-unit of year in the BCD-code. The range can be set from 0 to 9 (decimal). 13.3.9 Second Alarm Register (RSECAR) The second alarm register (RSECAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded second section counter RSECCNT of the RTC. When the ENB bit is set to 1, a comparison with the RSECCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of second can be set is 00 to 59 (decimal). Errant operation will result if any other value is set. The ENB bit in RSECAR is initialized to 0 by a power-on reset. The remaining RSECAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Rev. 4.00, 03/04, page 332 of 660 Bit 7 Bit Name Initial Value 0 R/W R/W Description Second Alarm Enable 0: No compared 1: Compared 6 to 4 R/W Setting value for 10-unit of second alarm in the BCD-code. The range can be set from 0 to 5 (decimal). Setting value for 1-unit of second alarm in the BCD-code. The range can be set from 0 to 9 (decimal). 3 to 0 R/W 13.3.10 Minute Alarm Register (RMINAR) The minute alarm register (RMINAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded minute section counter RMINCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMINCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of minute can be set is 00 to 59 (decimal). Errant operation will result if any other value is set. The ENB bit in RMINAR is initialized by a power-on reset. The remaining RMINAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name ENB Initial Value R/W 0 R/W Description Minute Alarm Enable 0: No compared 1: Compared 6 to 4 R/W Setting value for 10-unit of minute alarm in the BCDcode. The range can be set from 0 to 5 (decimal). Setting value for 1-unit of minute alarm in the BCDcode. The range can be set from 0 to 9 (decimal). 3 to 0 R/W Rev. 4.00, 03/04, page 333 of 660 13.3.11 Hour Alarm Register (RHRAR) The hour alarm register (RHRAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded hour section counter RHRCNT of the RTC. When the ENB bit is set to 1, a comparison with the RHRCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of hour can be set is 00 to 23 (decimal). Errant operation will result if any other value is set. The ENB bit in RHRAR is initialized by a power-on reset. The remaining RHRAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name ENB Initial Value R/W Description 0 R/W Hour Alarm Enable 0: No compared 1: Compared 6 5, 4 3 to 0 0 R Always read as 0. R/W Setting value for 10-unit of hour alarm in the BCD-code. The range can be set from 0 to 2 (decimal). R/W Setting value for 1-unit of hour alarm in the BCD-code. The range can be set from 0 to 9 (decimal). Rev. 4.00, 03/04, page 334 of 660 13.3.12 Day of the Week Alarm Register (RWKAR) The day of the week alarm register (RWKAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded day of week section counter RWKCNT of the RTC. When the ENB bit is set to 1, a comparison with the RWKCNT value is performed. From among the RSECAR/RMINAR/RHRAR/RWKAR/RDAYAR/RMONAR registers, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of day of the week can be set 0 to 6 (decimal). Errant operation will result if any other value is set. The ENB bit in RWKAR is initialized by a power-on reset. The remaining RWKAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name ENB Initial Value R/W Description 0 R/W Day of the week Alarm Enable 0: No compared 1: Compared 6 to 3 2 to 0 All 0 R Always read as 0. R/W Setting value for day of the week alarm in the BCD-code. The range can be set from 0 to 6 (decimal). Code 0: 1: 2: 3: 4: 5: 6: Day of the Week Sunday Monday Tuesday Wednesday Thursday Friday Saturday Rev. 4.00, 03/04, page 335 of 660 13.3.13 Date Alarm Register (RDAYAR) The date alarm register (RDAYAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded date section counter RDAYCNT of the RTC. When the ENB bit is set to 1, a comparison with the RDAYCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of date can be set 01 to 31 (decimal). Errant operation will result if any other value is set. The RDAYCNT range that can be set changes with some months and in leap years. Please confirm the correct setting. The ENB bit in RDAYAR is initialized by a power-on reset. The remaining RDAYAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name ENB Initial Value R/W Description 0 R/W Date Alarm Enable 0: No compared 1: Compared 6 5, 4 3 to 0 0 R Always read as 0. R/W Setting value for 10-unit of date alarm in the BCD-code. The range can be set from 0 to 3 (decimal). R/W Setting value for 1-unit of date alarm in the BCD-code. The range can be set from 0 to 9 (decimal). Rev. 4.00, 03/04, page 336 of 660 13.3.14 Month Alarm Register (RMONAR) The month alarm register (RMONAR) is an 8-bit read/write register, and an alarm register corresponding to the BCD-coded month section counter RMONCNT of the RTC. When the ENB bit is set to 1, a comparison with the RMONCNT value is performed. From among the registers RSECAR, RMINAR, RHRAR, RWKAR, RDAYAR, RMONAR, the counter and alarm register comparison is performed only on those with ENB bits set to 1, and if each of those coincide, an RTC alarm interrupt is generated. The range of month can be set 01 to 12 (decimal). Errant operation will result if any other value is set. The ENB bit in RMONAR is initialized by a power-on reset. The remaining RMONAR fields are not initialized by a power-on reset or manual reset, or in standby mode. Bit 7 Bit Name ENB Initial Value R/W Description 0 R/W Month Alarm Enable 0: No compared 1: Compared 6, 5 4 3 to 0 All 0 R Always read as 0. R/W Setting value for 10-unit of month alarm in the BCD-code. The range can be set from 0 to 1 (decimal). R/W Setting value for 1-unit of month alarm in the BCD-code. The range can be set from 0 to 9 (decimal). Rev. 4.00, 03/04, page 337 of 660 13.3.15 RTC Control Register 1 (RCR1) The RTC control register 1 (RCR1) is an 8-bit read/write register that affects carry flags and alarm flags. It also selects whether to generate interrupts for each flag. Because flags are sometimes set after an operand read, do not use this register in read-modify-write processing. RCR1 is initialized to H'00 by a power-on reset. In a manual reset, all bits are initialized to 0 except for the CF flag, which is undefined. When using the CF flag, it must be initialized beforehand. This register is not initialized in standby mode. Bit 7 Bit Name CF Initial Value R/W Description 0 R/W Carry Flag Status flag that indicates that a carry has occurred. CF is set to 1 when a count-up to R64CNT or RSECCNT occurs. A count register value read at this time cannot be guaranteed; another read is required. 0: No count up of R64CNT or RSECCNT. [Clearing condition] When 0 is written to CF 1: Count up of R64CNT or RSECCNT. [Setting condition] When 1 is written to CF 6, 5 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 4 CIE 0 R/W Carry Interrupt Enable Flag When the carry flag (CF) is set to 1, the CIE bit enables interrupts. 0: A carry interrupt is not generated when the CF flag is set to 1 1: A carry interrupt is generated when the CF flag is set to 1 3 AIE 0 R/W Alarm Interrupt Enable Flag When the alarm flag (AF) is set to 1, the AIE bit allows interrupts. 0: An alarm interrupt is not generated when the AF flag is set to 1 1: An alarm interrupt is generated when the AF flag is set to 1 Rev. 4.00, 03/04, page 338 of 660 Bit 2, 1 Bit Name -- Initial Value R/W Description All 0 R Reserved These bits are always read as 0. The write value should always be 0. 0 AF 0 R/W Alarm Flag The AF flag is set to 1 when the alarm time set in an alarm register (only registers with ENB bit set to 1) matches the clock and calendar time. This flag is cleared to 0 when 0 is written, but holds the previous value when 1 is to be written. 0: Clock/calendar and alarm register have not matched since last reset to 0. [Clearing condition] When 0 is written to AF 1: [Setting condition] Clock/calendar and alarm register have matched (only registers that ENB bit is 1) 13.3.16 RTC Control Register 2 (RCR2) The RTC control register 2 (RCR2) is an 8-bit read/write register for periodic interrupt control, 30second adjustment ADJ, divider circuit RESET, and RTC count start/stop control. It is initialized to H'09 by a power-on reset. It is initialized except for RTCEN and START by a manual reset. It is not initialized in standby mode, and retains its contents. Bit 7 Bit Name PEF Initial Value R/W Description 0 R/W Periodic Interrupt Flag Indicates interrupt generation with the period designated by the PES bits. When set to 1, PEF generates periodic interrupts. 0: Interrupts not generated with the period designated by the PES bits. [Clearing condition] When 0 is written to PEF 1: Interrupts generated with the period designated by the PES bits. [Setting condition] When 1 is written to PEF Rev. 4.00, 03/04, page 339 of 660 Bit 6 5 4 Bit Name PES2 PES1 PES0 Initial Value R/W 0 0 0 R/W R/W R/W Description Periodic Interrupt Flags These bits specify the periodic interrupt. 000: No periodic interrupts generated 001: Periodic interrupt generated every 1/256 second 010: Periodic interrupt generated every 1/64 second 011: Periodic interrupt generated every 1/16 second 100: Periodic interrupt generated every 1/4 second 101: Periodic interrupt generated every 1/2 second 110: Periodic interrupt generated every 1 second 111: Periodic interrupt generated every 2 seconds 3 RTCEN 1 R/W Controls the operation of the crystal oscillator for the RTC. 0: Halts the crystal oscillator for the RTC. 1: Runs the crystal oscillator for the RTC. 2 ADJ 0 R/W 30 Second Adjustment When 1 is written to the ADJ bit, times of 29 seconds or less will be rounded to 00 seconds and 30 seconds or more to 1 minute. The divider circuit will be simultaneously reset. This bit always reads 0. 0: Runs normally. 1 : 30-second adjustment. 1 RESET 0 R/W Reset When 1 is written, initializes the divider circuit (RTC prescaler and R64CNT). This bit always reads 0. 0: Runs normally. 1: Divider circuit is reset. 0 START 1 R/W Start Bit Halts and restarts the counter (clock). 0: Second/minute/hour/day/week/month/year counter halts. 1: Second/minute/hour/day/week/month/year counter runs normally. Note: The R64CNT always runs unless stopped with the RTCEN bit. Rev. 4.00, 03/04, page 340 of 660 13.4 13.4.1 RTC Operation Initial Settings of Registers after Power-On All the registers should be set after the power is turned on. 13.4.2 Setting the Time Figure 13.2 shows how to set the time when the clock is stopped. This works when the entire calendar or clock is to be set. It is easy to set the time using a software program. To reset the divider circuit (RTC prescaler and R64CNT) and set the counter Stop clock, reset divider circuit Write 0 to START and 1 to RESET in the RCR2 register Set seconds, minutes, hour, day, day of the week, month and year Order is irrelevant Start clock Write 1 to START in the RCR2 register Figure 13.2 Setting the Time Rev. 4.00, 03/04, page 341 of 660 13.4.3 Reading the Time Figure 13.3 shows how to read the time. If a carry occurs while reading the time, the correct time will not be obtained, so it must be read again. Part (a) in figure 13.3 shows the method of reading the time without using interrupts; part (b) in figure 13.3 shows the method using carry interrupts. To keep programming simple, method (a) should normally be used. (a) To read the time without using interrupts Disable the carry interrupt Clear the carry flag Read counter register Yes Carry flag = 1? No Read RCR1 and check CF Write 0 to CIE in RCR1 Write 0 to CF in RCR1 Note: Set AF in RCR1 to 1 so that alarm flag is not cleared. (b) To use interrupts Enable the carry interrupt Clear the carry flag Read counter register Yes Interrupt generated? No Disable the carry interrupt Write 1 to CIE in RCR1, and write 0 to CF in RCR1 Note: Set AF in RCR1 to 1 so that alarm flag is not cleared. Write 0 to CIE in RCR1 Figure 13.3 Reading the Time Rev. 4.00, 03/04, page 342 of 660 13.4.4 Alarm Function Figure 13.4 shows how to use the alarm function. Alarms can be generated using seconds, minutes, hours, day of the week, date, month, or any combination of these. Set the ENB bit (bit 7) in the register on which the alarm is placed to 1, and then set the alarm time in the lower bits. Clear the ENB bit in the register on which the alarm is placed to 0. When the clock and alarm times match, 1 is set in the AF bit (bit 0) in RCR1. Alarm detection can be checked by reading this bit, but normally it is done by interrupt. If 1 is placed in the AIE bit (bit 3) in RCR1, an interrupt is generated when an alarm occurs. Clock running Set whether to use alarm interrupt Disable interrupt to prevent errorneous interruption (AIE bit in RCR1 is cleared). Then write 1. Set alarm time Always reset, since the flag may have been set while the alarm time was being set (AF bit in RCR1 is cleared). Clear alarm flag Monitor alarm time (wait for interrupt or check alarm flag) Figure 13.4 Using the Alarm Function Rev. 4.00, 03/04, page 343 of 660 13.4.5 Crystal Oscillator Circuit Crystal oscillator circuit constants (recommended values) are shown in table 13.2, and the RTC crystal oscillator circuit in figure 13.5. Table 13.2 Recommended Oscillator Circuit Constants (Recommended Values) fosc 32.768 kHz Cin 10 to 22 pF Cout 10 to 22 pF SH7706 EXTAL2 Rf RD XTAL2 XTAL Cin Cout Notes: 1. 2. 3. 4. 5. Select either the Cin or Cout side for frequency adjustment variable capacitor according to requirements such as frequency range, degree of stability, etc. Built-in resistance value Rf (Typ value) = 10 M, RD (Typ value) = 400 k Cin and Cout values include floating capacitance due to the wiring. Take care when using a ground plane. The crystal oscillation settling time depends on the mounted circuit constants, floating capacitance, etc., and should be decided after consultation with the crystal resonator manufacturer. Place the crystal resonator and load capacitors Cin and Cout as close as possible to the chip. (Correct oscillation may not be possible if there is externally induced noise in the EXTAL2 and XTAL2 pins.) Ensure that the crystal resonator connection pin (EXTAL2, XTAL2) wiring is routed as far away as possible from other power lines (except GND) and signal lines. 6. Figure 13.5 Example of Crystal Oscillator Circuit Connection Rev. 4.00, 03/04, page 344 of 660 13.5 13.5.1 Usage Note Register Writing during RTC Count The following RTC registers cannot be written to during an RTC count (while bit 0 = 1 in RCR2). RSECCNT, RMINCNT, RHRCNT, RDAYCNT, RWKCNT, RMONCNT, RYRCNT The RTC count must be halted before writing to any of the above registers. 13.5.2 Use of Realtime Clock (RTC) Periodic Interrupts The method of using the periodic interrupt function is shown in figure 13.6. A periodic interrupt can be generated periodically at the interval set by the periodic interrupt enable flag (PES0 to PES2) in RCR2. When the time set by the PES0 to PES2 has elapsed, the PEF is set to 1. The PEF is cleared to 0 upon periodic interrupt generation when the periodic interrupt enable flag (PES0 to PES2) is set. Periodic interrupt generation can be confirmed by reading this bit, but normally the interrupt function is used. Set PES0 to PES2, and clear PEF to 0, in RCR2 Set PES, clear PEF Elapse of time set by PES Clear PEF Clear PEF to 0 Figure 13.6 Using Periodic Interrupt Function Rev. 4.00, 03/04, page 345 of 660 13.5.3 Timing for Setting ADJ Bit in RCR2 After the ADJ bit in RCR2 of the RTC is set to 1, it takes a maximum of approximately 91.6 s (when a 32.768-kHz crystal resonator is connected to the EXTAL2 pin) for the setting to affect the value read from the second counter (RSECCNT). If the result of 30-second adjustment by the ADJ bit in RCR2 needs to be reflected in the value read from the second counter, be sure to read from the second counter only after at least 91.6 s (approximately) has passed after the ADJ bit has been set to 1. Note that 30-second adjustment is actually performed for the second counter at the time the ADJ bit is set to 1, so this delay does not affect the RTC operation itself. Rev. 4.00, 03/04, page 346 of 660 Section 14 Serial Communication Interface (SCI) This LSI has an on-chip serial communication interface (SCI) that supports both asynchronous and clock synchronous serial communication. It also has a multiprocessor communication function for serial communication among two or more processors. A block diagram of SCI is shown in figure 14.1, and the I/O ports are shown in figures 14.2 to 14.4. 14.1 Feature The SCI has the following features. * Selectable from asynchronous or clock synchronous as the serial communications mode * Asynchronous mode: Serial data communications are synched by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. It can also communicate with two or more other processors using the multiprocessor communication function. There are 12 selectable serial data communication formats. Data length: Seven or eight bits Stop bit length: One or two bits Parity: Even, odd, or none Multiprocessor bit: 1 or 0 Receive error detection: Parity, overrun, and framing errors Break detection: By reading the RxD0 pin level directly from the port Serial communication port data register (SCPDR) when a framing error occurs * Clock synchronous mode: Serial data communication is synchronized with a clock signal. The SCI can communicate with other chips having a clock synchronous communication function. One serial data communication format is available. Data length: Eight bits Receive error detection: Overrun errors * Full duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use double buffering, so continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source From either baud rate generator (internal) or SCK0 pin (external) Rev. 4.00, 03/04, page 347 of 660 * Four types of interrupts Transmit-data-empty, transmit-end, receive-data-full, and receive-error interrupts are requested independently. * Saving power When the SCI is not in use, it can be stopped by halting the clock supply for the saving power. Figure 14.1 shows a SCI block diagram. Bus interface Module data bus Internal data bus SCRDR SCTDR SCPCR SCPDR SCSSR SCSCR SCSMR Transmit/ receive control SCBRR RxD0 SCRSR SCTSR Baud rate generator P P/4 P/16 P/64 TxD0 Parity generation Parity check Clock External clock TEI TXI RXI ERI SCK0 SCI Legend SCRSR: SCRDR: SCTSR: SCTDR: SCSMR: Receive shift register Receive data register Transmit shift register Transmit data register Serial mode register SCSCR: SCSSR: SCBRR: SCPDR: SCPCR: Serial control register Serial status register Bit rate register SC port data register SC port control register Figure 14.1 SCI Block Diagram Rev. 4.00, 03/04, page 348 of 660 Reset R D SCP1MD0 Q C PCRW Reset R D SCP1MD1 C PCRW Reset SCPT[1]/SCK0 R Q D SCP1DT1 C PDRW Output enable Serial clock output Clock input enable Internal data bus SCI PDRR* Serial clock input Legend PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK0 pin, clear the C/ bit in SCSMR and the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP1MD1 bit in SCPCR to 1. Figure 14.2 SCPT[1]/SCK0 Pin Rev. 4.00, 03/04, page 349 of 660 Reset R D SCP0MD0 Q C PCRW Reset R D SCP0MD1 C PCRW Reset SCPT[0]/TxD0 R Q D SCP0DT1 C PDRW Output enable Legend PCRW: SCPCR write PDRW: SCPDR write Serial transmission output Internal data bus SCI Figure 14.3 SCPT[0]/TxD0 Pin SCI SCPT[0]/RxD0 Serial receive data Internal data bus Legend PDRR: PDR read PDRR* Note: * When reading the RxD0 pin, set the RE bit in SCSCR to 1. Figure 14.4 SCPT[0]/RxD0 Pin Rev. 4.00, 03/04, page 350 of 660 14.2 Input/Output Pin The SCI has the serial pins summarized in table 14.1. Table 14.1 SCI Pins Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation SCK0 RxD0 TxD0 I/O I/O Input Output Function Clock I/O Receive data input Transmit data output Note: They are made to function as serial pins by performing SCI operation settings with the TE, RE, CKEI, and CKEO bits in SCSCR and the C/A bit in SCSMR. Break state transmission and detection can be performed by means of the SCI's SCPDR. 14.3 Register Description The SCI has the registers listed below. These registers select the communication mode (asynchronous or clock synchronous), specify the data format and bit rate, and control the transmitter and receiver sections. SCI has the registers listed below. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Serial mode register (SCSMR) * Bit rate register (SCBRR) * Serial control register (SCSCR) * Transmit data register (SCTDR) * Serial status register (SCSSR) * Receive data register (SCRDR) * SC port control register (SCPCR) * SC port data register (SCPDR) Rev. 4.00, 03/04, page 351 of 660 14.3.1 Receive Shift Register (SCRSR) The receive shift register (SCRSR) is an 8-bit register that receives serial data. Data input at the RxD pin is loaded into the SCRSR in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the SCRDR. The CPU cannot read or write the SCRSR directly. 14.3.2 Receive Data Register (SCRDR) The receive data register (SCRDR) is an 8-bit register that stores serial receive data. The SCI completes the reception of one byte of serial data by moving the received data from the SCRSR into the SCRDR for storage. The SCRSR is then ready to receive the next data. This double buffering allows the SCI to receive data continuously. The CPU can read but not write the SCRDR. The SCRDR is initialized to H'00 by a reset or in standby or module standby modes. 14.3.3 Transmit Shift Register (SCTSR) The transmit shift register (SCTSR) transmits serial data. The SCI loads transmit data from the SCTDR into the SCTSR, then transmits the data serially to the TxD0 pin, LSB (bit 0) first. After transmitting one-byte data, the SCI automatically loads the next transmit data from the SCTDR into the SCTSR and starts transmitting again. If the TDRE bit of the SCSSR is 1, however, the SCI does not load the SCTDR contents into the SCTSR. The CPU cannot read or write the SCTSR directly. 14.3.4 Transmit Data Register (SCTDR) The transmit data register (SCTDR) is an eight-bit register that stores data for serial transmission. When the SCI detects that the SCTSR is empty, it moves transmit data written in the SCTDR into the SCTSR and starts serial transmission. Continuous serial transmission is possible by writing the next transmit data in the SCTDR during serial transmission from the SCTSR. The CPU can always read and write the SCTDR. The SCTDR is initialized to H'FF by a reset or in standby and module standby modes. Rev. 4.00, 03/04, page 352 of 660 14.3.5 Serial Mode Register (SCSMR) The serial mode register (SCSMR) is an eight-bit register that specifies the SCI serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SCSMR. Bit 7 Bit Name C/A Initial Value 0 R/W R/W Description Communication Mode Selects whether the SCI operates in the asynchronous or clock synchronous mode. 0: Asynchronous mode 1: Clock synchronous mode 6 CHR 0 R/W Character Length Selects seven-bit or eight-bit data length in the asynchronous mode. In the clock synchronous mode, the data length is always eight bits, regardless of the CHR setting. 0: Eight-bit data 1: Seven-bit data Note: When seven-bit data is selected, the MSB (bit 7) in the SCTDR is not transmitted. 5 PE 0 R/W Parity Enable Selects whether to add a parity bit to the transmit data or to check the parity of receive data in asynchronous mode. In the clock synchronous mode, a parity bit is neither added nor checked, regardless of the PE setting. 0: Parity bit not added and not checked 1: Parity bit added and checked Note: When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. Rev. 4.00, 03/04, page 353 of 660 Bit 4 Bit Name O/E Initial Value 0 R/W R/W Description Parity Mode Selects even or odd parity when parity bits are added and checked. The O/E setting is available only when the PE is set to 1 to enable parity addition and check in asynchronous mode. The O/E setting is ignored in the clock synchronous mode, or in the asynchronous mode when parity addition and check is disabled. 0: Even parity Note: If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1: Odd parity Note: If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. 3 STOP 0 R/W Stop Bit Length Selects one or two bits as the stop bit length in the asynchronous mode. This setting is used only in the asynchronous mode. It is ignored in the clock synchronous mode because no stop bits are added. 0: One stop bit Note: In transmitting, a single bit of 1 is added at the end of each transmitted character. 1: Two stop bits Note: In transmitting, two bits of 1 are added at the end of each transmitted character. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. Rev. 4.00, 03/04, page 354 of 660 Bit 2 Bit Name MP Initial Value 0 R/W R/W Description Multiprocessor Mode Selects multiprocessor format. When multiprocessor format is selected, settings of the PE and O/E bits are ignored. The MP setting is used available in the asynchronous mode; it is ignored in the clock synchronous mode. For the multiprocessor communication function, see section 14.4.2, Multiprocessor Communication. 0: Multiprocessor function disabled 1: Multiprocessor format selected 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available. P, P/4, P/16 and P/64. For further information on the clock source, bit rate register settings, and baud rate, see section 14.3.10, Bit Rate Register (SCBRR). 00: P 01: P/4 10: P/16 11: P/64 Note: P: Peripheral clock 14.3.6 Serial Control Register (SCSCR) The serial control register (SCSCR) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCSCR. Bit 7 Bit Name TIEs Initial Value 0 R/W R/W Description Transmit Interrupt Enable Enables or disables the TXI request when the serial transmit data is transferred from SCTDR to SCTCR and the TDRE in SCSSR is set to 1. 0: Transmit-data-empty interrupt request (TXI) is disabled Note: The TXI interrupt request can be cleared by reading TDRE after it has been set to 1, then clearing TDRE to 0, or by clearing TIE to 0. 1: Transmit-data-empty interrupt request (TXI) is enabled Rev. 4.00, 03/04, page 355 of 660 Bit 6 Bit Name RIE Initial Value 0 R/W R/W Description Receive Interrupt Enable Enables or disables the receive-data-full interrupt (RXI) request when the serial receive data is transferred from SCRSR to SCRDR and the receive data register full bit (RDRF) in SCSSR is set to 1. It also enables or disables receive-error interrupt (ERI) requests. 0: Receive-data-full interrupt (RXI) and receiveerror interrupt (ERI) requests are disabled Note: RXI and ERI interrupt requests can be cleared by reading 1 from the RDRF flag or error flag (FER, PER, or ORER) then clearing the flag to 0, or by clearing RIE to 0. 1: Receive-data-full interrupt (RXI) and receiveerror interrupt (ERI) requests are enabled 5 TE 0 R/W Transmit Enable Enables or disables the SCI serial transmitter. 0: Transmission disabled Note: The TDRE in SCSSR is fixed to 1. 1: Transmission enabled Note: Serial transmission starts when TDRE bit in SCSSR is cleared to 0 after writing of transmit data into the SCTDR. Specify the transmit format to the SCSMR before setting TE to 1. 4 RE 0 R/W Receive Enable Enables or disables the SCI serial receiver. 0: Reception disabled Note: Clearing RE to 0 does not affect the receive flags (RDRF, FER, PER, ORER). These flags retain their previous values. 1: Reception enabled Note: Serial reception starts when a start bit is detected in the asynchronous mode, or synchronous clock input is detected in the clock synchronous mode. Specify the receive format to the SCSMR before setting RE to 1. Rev. 4.00, 03/04, page 356 of 660 Bit 3 Bit Name MPIE Initial Value 0 R/W R/W Description Multiprocessor Interrupt Enable Enables or disables multiprocessor interrupts. The MPIE setting is used only in the asynchronous mode, and only if the multiprocessor mode bit (MP) in the serial mode register (SCSMR) is set to 1 during reception. The MPIE setting is ignored in the clock synchronous mode or when the MP bit is cleared to 0. 0: Multiprocessor interrupts are disabled (normal receive operation) [Clearing conditions] 1. 2. MPIE is cleared to 0. MPB = 1 is in received data. 1: Multiprocessor interrupts are enabled Receive-data-full interrupt requests (RXI), receive-error interrupt requests (ERI), and setting of the RDRF, FER, and ORER status flags in the serial status register (SCSSR) are disabled until data with a multiprocessor bit of 1 is received. Note: The SCI does not transfer receive data from the SCRSR to the SCRDR, does not detect receive errors, and does not set the RDRF, FER, and ORER flags in the serial status register (SCSSR). When it receives data that includes MPB = 1, the SCSSR's MPB flag is set to 1, and the SCI automatically clears MPIE to 0, generates RXI and ERI interrupts (if the TIE and RIE bits in the SCSCR are set to 1), and allows the FER and ORER bits to be set. 2 TEIE 0 R/W Transmit-End Interrupt Enable Enables or disables the transmit-end interrupt (TEI) requested if SCTDR does not contain new transmit data when the MSB is transmitted. 0: Transmit-end interrupt (TEI) requests are disabled* 1: Transmit-end interrupt (TEI) requests are enabled* Note: * The TEI request can be cleared by reading the TDRE bit in SCSSR after it has been set to 1, then clearing TDRE to 0 and clearing the TEND bit to 0, or by clearing the TEIE bit to 0. Rev. 4.00, 03/04, page 357 of 660 Bit 1 0 Bit Name CKE1 CKE0 Initial Value 0 0 R/W R/W R/W Description Clock Enable 1 and 0 These bits select the SCI clock source and enable or disable clock output from the SCK pin. Depending on the combination of CKE1 and CKE0, the SCK pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only in the asynchronous mode, and only when the SCI is internally clock (CKE1 = 0). The CKE0 setting is ignored in the clock synchronous mode, or when an external clock source is selected (CKE1 = 1). Before selecting the SCI operating mode in the serial mode register (SCSMR), set CKE1 and CKE0. For further details on selection of the SCI clock source, see table 14.9. * Asynchronous mode 00: Internal clock; SCK0 pin is used for input pin 1 (input signal is ignored).* 01: Internal clock; SCK0 pin is used for clock 2 output. * 01: External clock; SCK0 pin is used for clock 3 input. * 11: External clock; SCK0 pin is used for clock 3 input. * * Clock synchronous mode 00: Internal clock; SCK0 pin is used for 1 synchronous clock output.* 01: Internal clock; SCK0 pin is used for synchronous clock output. 01: External clock; SCK0 pin is used for synchronous clock input. 11: External clock; SCK0 pin is used for synchronous clock input. Notes: 1. Initial value 2. The output clock frequency is the same as the bit rate. 3. The input clock frequency is 16 times the bit rate. Rev. 4.00, 03/04, page 358 of 660 14.3.7 Serial Status Register (SCSSR) The serial status register (SCSSR) is an 8-bit register containing multiprocessor bit values, and status flags that indicate SCI operating state. The CPU can always read and write the SCSSR, but cannot write 1 in the status flags (TDRE, RDRF, ORER, PER, and FER). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 2 (TEND) and 1 (MPB) are read-only bits that cannot be written. Bit 7 Bit Name TDRE Initial Value 1 R/W Description Indicates that the SCI has loaded transmit data from the SCTDR into the SCTSR and new serial transmit data can be written in the SCTDR. 0: SCTDR contains valid transmit data [Clearing condition] TDRE is read as 1, then written to with 0. 1: SCTDR does not contain valid transmit data [Setting conditions] 1. 2. 3. 6 RDRF 0 The chip is reset or enters standby mode. TE bit in the serial control register (SCSCR) is 0. SCTDR contents are loaded into SCTSR, so new data can be written in SCTDR. R/(W)* Transmit Data Register Empty R/(W)* Receive Data Register Full Indicates that SCRDR contains received data. 0: SCRDR does not contain valid received data [Clearing conditions] 1. The chip is reset or enters standby mode. 2. RDRF is read as 1, then written to with 0. 1: SCRDR contains valid received data [Setting condition] Serial data is received normally and transferred from SCRSR to SCRDR. Note: The SCRDR and RDRF are not affected by detection of receive errors or by clearing of the RE bit to 0 in the serial control register. They retain their previous contents. If RDRF is still set to 1 when reception of the next data ends, an overrun error (ORER) occurs and the received data is lost. Rev. 4.00, 03/04, page 359 of 660 Bit 5 Bit Name ORER Initial Value 0 R/W Description Indicates that data reception aborted due to an overrun error. 0: Receiving is in progress or has ended 1 normally* [Clearing conditions] 1. The chip is reset or enters standby mode. 2. ORER is read as 1, then written to with 0. 2 1: A receive overrun error occurred* [Setting condition] Reception of the next serial data has ended when RDRF is set to 1. Notes: 1. Clearing the RE bit to 0 in the serial control register does not affect the ORER bit, which retains its previous value. 2. SCRDR continues to hold the data received before the overrun error, so subsequent receive data is lost. Serial receiving cannot continue while ORER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. R/(W)* Overrun Error Rev. 4.00, 03/04, page 360 of 660 Bit 4 Bit Name FER Initial Value 0 R/W Description Indicates that data reception aborted due to a framing error in the asynchronous mode. 0: Receiving is in progress or has ended normally [Clearing conditions] 1. The chip is reset or enters standby mode. 2. FER is read as 1, then written to with 0. Note: Clearing the RE bit to 0 in the serial control register does not affect the FER bit, which retains its previous value. 1: A receive framing error occurred [Setting condition] When the SCI has completed receiving, the stop bit at the end of receive data is checked and found to be 0. Note: When the stop bit length is two bits, only the first bit is checked. The second stop bit is not checked. When a framing error occurs, the SCI transfers the receive data into the SCRDR but does not set RDRF. Serial receiving cannot continue while FER is set to 1. In the clock synchronous mode, serial transmitting is also disabled. R/(W)* Framing Error Rev. 4.00, 03/04, page 361 of 660 Bit 3 Bit Name PER Initial Value 0 R/W Description R/(W)* Parity Error Indicates that data reception (with parity) aborted due to a parity error in the asynchronous mode. 0: Receiving is in progress or has ended normally [Clearing conditions] 1. The chip is reset or enters standby mode. 2. PER is read as 1, then written to with 0. Note: Clearing the RE bit to 0 in the SCSCR does not affect the PER bit, which retains its previous value. 1: A receive parity error occurred [Setting condition] The number of 1s in receive data, including the parity bit, does not match the even or odd parity setting of the parity mode bit (O/E) in SCSMR. When a parity error occurs, the SCI transfers the receive data into the SCRDR but does not set RDRF. Serial receiving cannot continue while PER is set to 1. In the clock synchronous mode, serial transmitting also cannot continue. 2 TEND 1 R Transmit End Indicates that when the last bit of a serial character was transmitted, the SCTDR did not contain valid data, so transmission has ended. TEND is a readonly bit and cannot be written. [Clearing condition] TDRE is read as 1, then written to with 0. [Setting conditions] 1. The chip is reset or enters standby mode. 2. TE bit in SCSCR is 0. 3. TDRE is 1 when the last bit of a one-byte serial character is transmitted. Rev. 4.00, 03/04, page 362 of 660 Bit 1 Bit Name MPB Initial Value 0 R/W R Description Multiprocessor Bit Stores the value of the multiprocessor bit in receive data when a multiprocessor format is selected for receiving in the asynchronous mode. The MPB is a read-only bit and cannot be written. 0: Multiprocessor bit value in receive data is 0 If RE is cleared to 0 when a multiprocessor format is selected, the MPB retains its previous value. 1: Multiprocessor bit value in receive data is 1 Note: Clearing the RE bit to 0 in the maltiprocessor format, which retain its previous value. 0 MPBT 0 R/W Multiprocessor Bit Transfer Stores the value of the multiprocessor bit added to transmit data when a multiprocessor format is selected for transmitting in the asynchronous mode. The MPBT setting is ignored in the clock synchronous mode, when a multiprocessor format is not selected, or when the SCI is not transmitting. 0: Multiprocessor bit value in transmit data is 0 1: Multiprocessor bit value in transmit data is 1 Note: * The only value that can be written is a 0 to clear the flag. Rev. 4.00, 03/04, page 363 of 660 14.3.8 SC Port Control Register (SCPCR) The SC port control register (SCPCR) controls the direction of I/O signals on the SCI and SCIF pins. SCPCR settings are used to perform I/O direction control, enabling data written in SCPDR to be output to the TxD0 pin, data read from the RxD0 pin to be input, and the breaking of serial transmission/reception. It is also possible to read data on and write output data to the SCK0 pin. The I/O controls on the SCI and SCIF pins are performed using bits 3 to 0, and bits 11 to 4 in SCPCR, respectively. Bit 15 to 12 Bit Name Initial Value All 0 R/W Description R Reserved These bits are always read as 0; only 0 should be written here. 11 10 9 8 7 6 5 4 3 2 SCP5MD1 SCP5MD0 SCP4MD1 SCP4MD0 SCP3MD1 SCP3MD0 SCP2MD1 SCP2MD0 SCP1MD1 SCP1MD0 1 0 1 0 1 0 1 0 1 0 R/W See section 17.1.10, SC Port Control Register R/W (SCPCR). R/W R/W R/W R/W R/W R/W R/W Serial clock port I/O R/W These bits specify serial port SCK0 pin I/O. When the SCK0 pin is actually used as a port I/O pin, clear the C/A bit of SCSMR and bits CKE1 and CKE0 of SCSCR to 0. 00: SCP1DT bit value is not output to SCK0 pin. 01: SCP1DT bit value is output to SCK0 pin. 10: SCK0 pin value is read from SCP1DT bit. 11: SCK0 pin value is read from SCP1DT bit. 1 0 SCP0MD1 SCP0MD0 0 0 R/W Serial port break I/O R/W These bits specify the serial port TxD0 pin output condition. When the TxD0 pin is actually used as a port output pin and outputs the value set with the SCP0DT bit, clear the TE bit of SCSCR to 0. 00: SCP0DT bit value is not output to TxD0 pin. 01: SCP0DT bit value is output to TxD0 pin. Rev. 4.00, 03/04, page 364 of 660 14.3.9 SC Port Data Register (SCPDR) The SC port data register (SCPDR) controls data on the SCI and SCIF pins. The data controls on the SCI and SCIF pins are performed using bits 1 and 0, and bits 5 and 2 in SCPDR, respectively. Bit 7, 6 Bit Name Initial Value R/W Description R Reserved These bits are always read as 0; only 0 should be written here. 5 4 3 2 1 SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT 0 0 0 0 R See section 18.10.2, SC Port Data Register R/W (SCPDR). R/W R/W R/W Serial clock port data Specifies the serial port SCK0 pin I/O data. Input or output is specified by the SCP1MD0 and SCP1MD1 bits. In output mode, the value of the SCP1DT bit is output to the SCK0 pin. 0: I/O data is low (0). 1: I/O data is high (1). 0 SCP0DT 0 R/W Serial port break data Specifies the serial port RxD0 pin input data and TxD0 pin output data. The TxD0 pin output condition is specified by the SCP0MD0 and SCP0MD1 bits. When the TxD0 pin is set to output mode, the value of the SCP0DT bit is output to the TxD0 pin. The RxD0 pin value is read from the SCP0DT bit regardless of the values of the SCP0MD0 and SCP0MD1 bits, if RE in the SCSCR is set to 1. The initial value of this bit after a power-on reset is undefined. 0: I/O data is low (0). 1: I/O data is high (1). Rev. 4.00, 03/04, page 365 of 660 14.3.10 Bit Rate Register (SCBRR) The bit rate register (SCBRR) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in SCSMR, determines the serial transmit/receive bit rate. The CPU can always read and write the SCBRR. The SCBRR is initialized to H'FF by a reset or in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in two channels. The SCBRR setting is calculated as follows: Asynchronous mode: N = [P/(64 x 22n - 1 x B)] x 106 - 1 Clock synchronous mode: N = [P/(8 x 22n - 1 x B)] x 106 - 1 B: N: P: n: Bit rate (bit/s) SCBRR setting for baud rate generator (0 N 255) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 14.2.) Table 14.2 SCSMR Settings SCSMR Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Find the bit rate error for the asynchronous mode by the following formula: PB x 10 6 2n-1 Error (%) = (N + 1) x B x 64 x 2 - 1 x 100 Rev. 4.00, 03/04, page 366 of 660 Table 14.3 lists examples of SCBRR settings in the asynchronous mode; table 14.4 lists examples of SCBRR settings in the clock synchronous mode. Table 14.3 Bit Rates and SCBRR Settings in Asynchronous Mode P (MHz) 7.3728 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 n 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 P (MHz) 10 Bit Rate (bits/s) n 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (%) n -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 2 2 2 1 1 0 0 0 0 0 0 N 212 155 77 155 77 155 77 38 19 11 9 12 Error (%) n 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 12.288 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 2 2 1 1 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 7 9.8304 Error (%) -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 Rev. 4.00, 03/04, page 367 of 660 P (MHz) 14.7456 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 2 2 1 1 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 Error (%) 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 16 Error (%) 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 n 3 2 2 1 1 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 Error (%) n 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 3 3 2 2 1 1 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 20 Error (%) -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 -1.70 0 0.00 0 P (MHz) 24 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 Error (%) -0.44 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 n 3 3 2 2 1 1 0 0 0 0 0 24.576 N 108 79 159 79 159 79 159 79 39 24 19 Error (%) 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 n 3 3 2 2 1 1 0 0 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 Error (%) 0.31 0.46 -0.08 0.46 -0.08 0.46 -0.08 0.46 -0.61 -1.03 1.55 n 3 3 2 2 1 1 0 0 0 0 0 N 132 97 194 97 194 97 194 97 48 29 23 30 Error (%) 0.13 -0.35 0.16 -0.35 0.16 -0.35 0.16 -0.35 -0.35 0.00 1.73 Rev. 4.00, 03/04, page 368 of 660 P (MHz) 33.34 Bit Rate (bits/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 3 3 2 2 1 1 0 0 0 0 0 N 147 108 216 108 216 108 216 108 53 32 26 Error (%) 0.00 -0.43 0.03 -0.43 0.03 -0.43 0.03 -0.43 0.49 1.03 0.49 Table 14.4 Bit Rates and SCBRR Settings in Clock Synchronous Mode P (MHz) 8 Bit Rate (bits/s) n 110 250 500 1k 2.5k 5k 10k 25k 50k 100k 250k 500k 1M 2M -- 3 2 2 1 1 0 0 0 0 0 0 0 0 N -- 124 249 124 199 99 199 79 39 19 7 3 1 0* n -- 3 3 2 2 1 1 0 0 0 0 0 0 0 16 N -- 249 124 249 99 199 99 159 79 39 15 7 3 1 n -- -- 3 3 2 2 1 1 0 0 -- -- -- -- 28.7 N -- -- 223 111 178 89 178 71 143 71 -- -- -- -- n -- -- 3 3 2 2 1 1 0 0 0 0 -- -- 30 N -- -- 233 116 187 93 187 74 149 74 29 14 -- -- Rev. 4.00, 03/04, page 369 of 660 Note: Blank: --: *: Settings with an error of 1% or less are recommended. No setting possible Setting possible, but error occurs Continuous transmit/receive not possible Table 14.5 indicates the maximum bit rates in the asynchronous mode when the baud rate generator is used. Tables 14.6 and 14.7 list the maximum rates for external clock input. Table 14.5 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bits/s) 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 Rev. 4.00, 03/04, page 370 of 660 Table 14.6 Maximum Bit Rates during External Clock Input (Asynchronous Mode) P (MHz) 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bits/s) 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 Table 14.7 Maximum Bit Rates during External Clock Input (Clock Synchronous Mode) P (MHz) 8 16 24 28.7 30 External Input Clock (MHz) 1.3333 2.6667 4.0000 4.7833 5.0000 Maximum Bit Rate (bits/s) 1333333.3 2666666.7 4000000.0 4783333.3 5000000.0 Rev. 4.00, 03/04, page 371 of 660 14.4 Operation For serial communication, the SCI has an asynchronous mode in which characters are synchronized individually, and a clock synchronous mode in which communication is synchronized with clock pulses. Asynchronous/clock synchronous mode and the transmission format are selected in SCSMR, as listed in table 14.8. The SCI clock source is selected by the combination of the C/A bit in SCSMR and the CKE1 and CKE0 bits in SCSCR, as listed in table 14.9. Asynchronous Mode: * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors, parity errors , overrun errors and breaks. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates on the clock of the on-chip baud rate generator, and can output a serial clock signal with a frequency matching the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Clock Synchronous Mode: * The transmission/reception format has a fixed eight-bit data length. * In receiving, it is possible to detect overrun errors. * An internal or external clock can be selected as the SCI clock source. When an internal clock is selected, the SCI operates on the clock of the on-chip baud rate generator, and outputs a synchronous clock signal to external devices. When an external clock is selected, the SCI operates on the input synchronous clock. The on-chip baud rate generator is not used. Rev. 4.00, 03/04, page 372 of 660 Table 14.8 Serial Mode Register Settings and SCI Communication Formats SCSMR Settings Mode Asynchronous Bit 7 Bit 6 C/A CHR A 0 0 Bit 5 PE 0 Bit 2 MP 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 Asynchronous (multiprocessor format) 1 0 * * * * Clock synchronous 1 * * * 1 0 1 0 1 * 8-bit Not set 7-bit 8-bit Not set Set Set 7-bit Not set Set SCI Communication Format Data Length 8-bit Parity Bit Not set Multipro- Stop Bit cessor Bit Length Not set 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits None Note: * Don't care Table 14.9 SCSMR and SCSCR Settings and SCI Clock Source Selection SCSMR Bit 7 C/A A Mode Asynchronous 0 mode SCSCR Settings Bit 1 CKE1 0 Bit 0 CKE0 0 1 1 0 1 Clock synchronous mode 1 0 0 1 1 0 1 External Inputs the synchronous clock Internal External Clock Source Internal SCI Transmit/Receive Clock SCK Pin Function SCI does not use the SCK pin Outputs a clock with frequency matching the bit rate Inputs a clock with frequency 16 times the bit rate Outputs the synchronous clock Rev. 4.00, 03/04, page 373 of 660 14.4.1 Operation in Asynchronous Mode In the asynchronous mode, each transmitted or received character begins with a start bit and ends with a stop bit. Serial communication is synchronized one character at a time. The transmitting and receiving sections of the SCI are independent, so full duplex communication is possible. The transmitter and receiver are both double buffered, so data can be written and read while transmitting and receiving are in progress, enabling continuous transmitting and receiving. Figure 14.5 shows the general format of asynchronous serial communication. In asynchronous serial communication, the communication line is normally held in the mark (high) state. The SCI monitors the line and starts serial communication when the line goes to the space (low) state, indicating a start bit. One serial character consists of a start bit (low), data (LSB first), parity bit (high or low), and stop bit (high), in that order. When receiving in the asynchronous mode, the SCI synchronizes on the falling edge of the start bit. The SCI samples each data bit on the eighth pulse of a clock with a frequency 16 times the bit rate. Receive data is latched at the center of each bit. Idling (marking) 1 Serial data Start bit Transmit/receive data 1 bit 7 or 8 bits 1 or no bit 1 or 2 bits Parity bit Stop bit 0 (LSB) D0 D1 D2 D3 D4 D5 D6 (MSB) D7 0/1 1 1 1 One unit of communication data (character or frame) Example: 8-bit data with parity and two stop bits Figure 14.5 Data Format in Asynchronous Communication Rev. 4.00, 03/04, page 374 of 660 Transmit/Receive Formats: Table 14.10 lists the 11 communication formats that can be selected in the asynchronous mode. The format is selected by settings in the SCSMR. Table 14.10 Serial Communication Formats (Asynchronous Mode) SCSMR Bits CHR PE 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 -- -- -- -- MP 0 0 0 0 0 0 0 0 1 1 1 1 STOP 1 0 1 0 1 0 1 0 1 0 1 0 1 START START START START START START START START START START START START Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP MPB MPB MPB MPB STOP STOP STOP STOP STOP STOP STOP STOP STOP 11 12 8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data Legend --: START: STOP: P: MPB: Don't care Start bit Stop bit Parity bit Multiprocessor bit Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK0 pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SCSMR and bits CKE1 and CKE0 in the SCSCR (table 14.9). When an external clock is input on the SCK0 pin, it must have a frequency equal to 16 times the desired bit rate. When the SCI operates on an internal clock, it can output a clock signal on the SCK0 pin. The frequency of this output clock is equal to the bit rate. The phase is aligned as in figure 14.6 so that the rising edge of the clock occurs at the center of each transmit data bit. Rev. 4.00, 03/04, page 375 of 660 0 D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1 1 frame Figure 14.6 Output Clock and Serial Data Timing (Asynchronous Mode) Transmitting and Receiving Data (SCI Initialization (Asynchronous Mode)): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR), then initialize the SCI as follows. When changing the operation mode or communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to 1 and initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags or receive data register (SCRDR), which retain their previous contents. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCI operation becomes unreliable if the clock is stopped. Figure 14.7 is a sample flowchart for initializing the SCI. Initialize Clear TE and RE bits in SCSCR to 0 Set CKE1 and CKE0 bits in SCSCR (TE and RE bits are 0) Select transmit/receive format in SCSMR Set value to SCBRR Wait Has a 1-bit interval elapsed? Yes Set TE and RE bits in SCSCR to 1 and set RIE, TEIE, and MPIE bits No 1. Select the clock source in the SCSCR. Leave RIE, TIE, TEIE, MPIE, TE, and RE cleared to 0. If clock output is selected in asynchronous mode, clock output starts immediately after the setting is made to SCSCR. 2. Select the communication format in the SCSMR. 3. Write the value corresponding to the bit rate in SCBRR unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the SCSCR to 1. Also set RIE, TIE, TEIE, and MPIE as necessary. Setting TE or RE enables the SCI to use the TxD0 or RxD0 pin. The initial states are the mark transmit state, and the idle receive state (waiting for a start bit). End Figure 14.7 Sample Flowchart for SCI Initialization Rev. 4.00, 03/04, page 376 of 660 Transmitting Serial Data (Asynchronous Mode): Figure 14.8 shows a sample flowchart for transmitting serial data. Serial data transmission should be carried out in the following procedure after setting the SCI in a transmission-enabled state. Start transmission Read TDRE bit in SCSSR No 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the SCTDR and clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. 3. To output a break at the end of serial transmission: Set the SCPCR and SCPDR, then clear the TE bit to 0 in SCSCR. For SCPCR and SCPDR settings, see14.3.8, SC Port Control Register (SCPCR), and 14.3.9, SC Port Data Register (SCPDR). TDRE = 1? Yes Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 All data transmitted? Yes Read TEND bit in SCSSR No TEND = 1? Yes Break output? Yes Set SCPDR and SCPCR Clear TE bit SCSCR to 0 End transmission No No Figure 14.8 Sample Flowchart for Transmitting Serial Data Rev. 4.00, 03/04, page 377 of 660 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0, the SCI recognizes that the transmit data register (SCTDR) contains new data, and loads this data from the SCTDR into the SCTSR. 2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) is set to 1 in the SCSCR, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD0 pin: a. Start bit: One 0 bit is output. b. Transmit data: Seven or eight bits of data are output, LSB first. c. Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor bit is output can also be selected. d. Stop bit: One or two 1 bits (stop bits) are output. e. Marking: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads new data from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit to 1 in the SCSSR, outputs the stop bit, then continues output of 1 bits (marking). If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested. Figure 14.9 shows an example of SCI transmit operation in the asynchronous mode. Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 1 Serial data Data Data 1 Idling (marking) TDRE TEND TXI interrupt request generated Writes data to SCTDR with the TXI interrupt processing routine and clear TDRE bit to 0 1 frame TXI interrupt request generated TEI interrupt request generated Example: 8-bit data with parity and one stop bit Figure 14.9 SCI Transmit Operation in Asynchronous Mode Rev. 4.00, 03/04, page 378 of 660 Receiving Serial Data (Asynchronous Mode): Figure 14.10 shows a sample flowchart for receiving serial data. Serial data reception should be carried out in the following procedure after setting the SCI in a reception-enabled state. Start reception Read ORER, PER, and FER bits in SCSSR PER = 1, FER = 1, or ORER = 1? No Read the RDRF bit in SCSSR No Error processing 1. Receive error processing and break detection: If a receive error occurs, read the ORER, PER and FER bits of the SCSSR to identify the error. After executing the necessary error processing, clear ORER, PER and FER all to 0. Receiving cannot resume if ORER, PER or FER remain set to 1. When a framing error occurs, the RxD0 pin can be read to detect the break state. 2. SCI status check and receive-data read: Read the SCSSR, check that RDRF is set to 1, then read receive data from the SCRDR and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue receiving serial data: Clear RDRF to 0 before the stop bit of the current frame is received. Yes RDRF = 1? Yes Read reception data of SCRDR and clear RDRF bit in SCSSR to 0 No All data received? Yes Clear the RE bit in SCSCR to 0 End reception Figure 14.10 Sample Flowchart for Receiving Serial Data Rev. 4.00, 03/04, page 379 of 660 Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 Yes No PER = 1? Yes Parity error processing Clear ORER, PER, and FER bits in SCSSR to 0 End Figure 14.10 Sample Flowchart for Receiving Serial Data (cont) Rev. 4.00, 03/04, page 380 of 660 In receiving, the SCI operates as follows: 1. The SCI monitors the communication line. When it detects a start bit (0), the SCI synchronizes internally and starts receiving. 2. Receive data is stored into the SCRSR in order from the LSB to the MSB. 3. The parity bit and stop bit are received. After receiving these bits, the SCI makes the following checks: a. Parity check: The number of 1s in the receive data must match the even or odd parity setting of the O/E bit in the SCSMR. b. Stop bit check: The stop bit value must be 1. If there are two stop bits, only the first stop bit is checked. c. Status check: RDRF must be 0 so that receive data can be loaded from the SCRSR into the SCRDR. If these checks all pass, the SCI sets RDRF to 1 and stores the received data in the SCRDR. If one of the checks fails (receive error), the SCI operates as indicated in table 14.11. Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is not set to 1. Be sure to clear the error flags. 4. After setting RDRF to 1, if the receive-data-full interrupt enable bit (RIE) is set to 1 in the SCSCR, the SCI requests a receive-data-full interrupt (RXI). If one of the error flags (ORER, PER, or FER) is set to 1 and the receive-data-full interrupt enable bit (RIE) in the SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Table 14.11 Receive Error Conditions and SCI Operation Receive Error Overrun error Abbreviation ORER Condition Data Transfer Receiving of next data ends while Receive data not loaded RDRF is still set to 1 in SCSSR from SCRSR into SCRDR Stop bit is 0 Receive data loaded from SCRSR into SCRDR Framing error Parity error FER PER Parity of receive data differs from Receive data loaded from even/odd parity setting in SCSMR SCRSR into SCRDR Rev. 4.00, 03/04, page 381 of 660 Figure 14.11 shows an example of SCI receive operation in the asynchronous mode. Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 1 Serial data Data Data 1 Idling (marking) RDRF RXI interrupt FER request generated 1 frame Reads data with the RXI interrupt processing routine and clears RDRF Example: 8-bit data with parity and one stop bit bit to 0 ERI interrupt request generated by framing error Figure 14.11 SCI Receive Operation 14.4.2 Multiprocessor Communication The multiprocessor communication function enables several processors to share a single serial communication line. The processors communicate in the asynchronous mode using a format with an additional multiprocessor bit (multiprocessor format). In multiprocessor communication, each receiving processor is addressed by a unique ID. A serial communication cycle consists of an ID-sending cycle that identifies the receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-sending cycles from data-sending cycles. The transmitting processor starts by sending the ID of the receiving processor with which it wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting processor sends transmit data with the multiprocessor bit cleared to 0. Receiving processors skip incoming data until they receive data with the multiprocessor bit set to 1. When they receive data with the multiprocessor bit set to 1, receiving processors compare the data with their IDs. The receiving processor with a matching ID continues to receive further incoming data. Processors with IDs not matching the received data skip further incoming data until they again receive data with the multiprocessor bit set to 1. Multiple processors can send and receive data in this way. Rev. 4.00, 03/04, page 382 of 660 Figure 14.12 shows an example of communication among processors using the multiprocessor format. Transmitting station Serial communications circuit Receiving station A (ID = 01) Receiving station B (ID = 02) Receiving station C (ID = 03) Receiving station D (ID = 04) Serial data H'01 (MPB = 1) ID transmit cycle = specifies receiving station H'AA (MPB = 0) Data transmit cycle = data transmission to receiving station specified by ID MPB: Example: Multiprocessor bit Sending data H'AA to receiving processor A Figure 14.12 Communication Among Processors Using Multiprocessor Format Communication Formats: Four formats are available. Parity-bit settings are ignored when the multiprocessor format is selected. For details see table 14.10. Clock: See the description in the asynchronous mode section. Rev. 4.00, 03/04, page 383 of 660 Transmitting Multiprocessor Serial Data: Figure 14.13 shows a sample flowchart for transmitting multiprocessor serial data. Transmission of multiprocessor serial data should be carried out in the following procedure after setting the SCI in a transmission-enabled state. Start transmission Read TDRE bit in SCSSR No 1. SCI status check and transmit data write: Read the SCSSR, check that the TDRE bit is 1, then write transmit data in the SCTDR. Also set MPBT (multiprocessor bit transfer) to 0 or 1 in SCSSR. Finally, clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. 3. To output a break at the end of serial transmission: Set the SCPDR and SCPCR, then clear the TE bit to 0 in SCSCR. For SCPCR and SCPDR settings, see section 14.3.8, SC Port Control Register (SCPCR), and section 14.3.9, SC Port Data Register (SCPDR). TDRE = 1? Yes Write transmission data to SCTDR and set MPBT bit in SCSSR Clear TDRE bit to 0 Transmission ended? Yes Read TEND bit in SCSSR No TEND = 1? Yes Break output? Yes Set SCPDR and SCPCR Clear TE bit SCSCR to 0 No No End transmission Figure 14.13 Sample Flowchart for Transmitting Multiprocessor Serial Data Rev. 4.00, 03/04, page 384 of 660 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes that the SCTDR contains new data, and loads this data from the SCTDR into the SCTSR. 2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. Serial transmit data is transmitted in the following order from the TxD0 pin: A. Start bit: One 0 bit is output. B. Transmit data: Seven or eight bits are output, LSB first. C. Multiprocessor bit: One multiprocessor bit (MPBT value) is output. D. Stop bit: One or two 1 bits (stop bits) are output. E. Marking: Output of 1 bits continues until the start bit of the next transmit data. 3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, the SCI loads data from the SCTDR into the SCTSR, outputs the stop bit, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, outputs the stop bit, then continues output of 1 bits in the marking state. If the transmit-end interrupt enable bit (TEIE) in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. Figure 14.14 shows SCI transmission in the multiprocessor format. Multiprocessor bit Stop Data D0 D1 D7 0/1 bit 1 Multiprocessor bit Stop Data D0 D1 D7 0/1 bit 1 1 Idling (marking) 1 Serial data Start bit 0 Start bit 0 TDRE TEND TXI interrupt request generated Writes data to TDR with the TXI interrupt processing routine and clears TDRE bit to 0 1 frame TXI interrupt request generated TEI interrupt request generated Example: 8-bit data with multiprocessor bit and one stop bit Figure 14.14 SCI Multiprocessor Transmit Operation Rev. 4.00, 03/04, page 385 of 660 Receiving Multiprocessor Serial Data: Figure 14.15 shows a sample flowchart for receiving multiprocessor serial data. Reception of multiprocessor serial data should be carried out in the following procedure after setting the SCI in a reception-enabled state. Start reception Set MPIE bit in SCSCR to 1 Read ORER and FER bits in SCSSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR No Yes RDRF = 1? Yes Read receive data in SCRDR No Is ID the stations ID? Yes Read ORER and FER bits in SSCSR FER = 1 or ORER = 1? No Read RDRF bit in SCSSR RDRF = 1? Yes Read receive data in SCRDR No Yes 1. ID receive cycle: Set the MPIE bit in SCSCR to 1. 2. SCI status check and compare to ID reception: Read the SCSSR, check that RDRF is set to 1, then read data from the SCRDR and compare with the processor's own ID. If the ID does not match the receive data, set MPIE to 1 again and clear RDRF to 0. If the ID matches the receive data, clear RDRF to 0. 3. SCI status check and data receiving: Read SCSSR, check that RDRF is set to 1, then read data from the SCRDR. 4. Receive error processing and break detection: If a receive error occurs, read the ORER and FER bits in SCSSR to identify the error. After executing the necessary error processing, clear both ORER and FER to 0. Receiving cannot resume if ORER or FER remain set to 1. When a framing error occurs, the RxD0 pin can be read to detect the break state. Error processing No All data received? Yes Clear RE bit in SCSCR to 0 End reception Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data Rev. 4.00, 03/04, page 386 of 660 Error processing No ORER = 1? Yes Overrun error processing No FER = 1? Yes Break? No Framing error processing Clear RE bit in SCSCR to 0 Yes Clear ORER and FER bits in SCSSR to 0 End Figure 14.15 Sample Flowchart for Receiving Multiprocessor Serial Data (cont) Rev. 4.00, 03/04, page 387 of 660 Figure 14.16 shows an example of SCI receive operation using a multiprocessor format. Start bit 0 Data (ID1) D0 D1 D7 Stop Start MPB bit bit 1 1 0 Data (data 1) D0 D1 D7 Stop bit 1 1 Serial data MPB 0 1 Idling (marking) MPIE RDRF RDR value RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 Reads RDR data with the RXI interrupt processing routine and clears RDRF bit to 0 ID1 ID is not station's ID, so MPIE bit is set to 1 again No RXI interrupt, generated RDR state is maintained (a) Own ID does not matches data 1 Serial data Start bit 0 Data (ID2) D0 D1 D7 MPB 1 Stop Start bit bit 1 0 Data (Data 2) D0 D1 D7 MPB 0 Stop bit 1 1 Idling (marking) MPIE RDRF RDR value ID1 ID2 Data2 RXI interrupt request (multiprocessor interrupt) generated, MPIE = 0 Reads RDR data with the RXI interrupt processing routine and clears RDRF bit to 0 ID is that of station, so reception continues unchanged and data is received by the RXI interrupt processing routine MPIE bit set to 1 again (b) Own ID matches data Figure 14.16 Example of SCI Receive Operation Rev. 4.00, 03/04, page 388 of 660 14.4.3 Clock Synchronous Operation In the clock synchronous mode, the SCI transmits and receives data in synchronization with clock pulses. This mode is suitable for high-speed serial communication. The SCI transmitter and receiver are independent, so full-duplex communication is possible while sharing the same clock. The transmitter and receiver are also double buffered, so continuous transmitting or receiving is possible by reading or writing data while transmitting or receiving is in progress. Figure 14.17 shows the general format in clock synchronous serial communication. One unit of communication data (character or frame) * Synchronization clock LSB Serial data Don't care Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 MSB Bit 7 Don't care * Note: * High except in continuous transmitting or receiving Figure 14.17 Data Format in Clock Synchronous Communication In clock synchronous serial communication, each data bit is output on the communication line from one falling edge of the serial clock to the next. Data are guaranteed valid at the rising edge of the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first) to the MSB (last). After output of the MSB, the communication line remains in the state of the MSB. In the clock synchronous mode, the SCI transmits or receives data by synchronizing with the rising edge of the serial clock. Communication Format: The data length is fixed at eight bits. No parity bit or multiprocessor bit can be added. Rev. 4.00, 03/04, page 389 of 660 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK0 pin can be selected as the SCI transmit/receive clock. The clock source is selected by the C/A bit in SCSMR and bits CKE1 and CKE0 in the SCSCR. See table 14.9. When the SCI operates on an internal clock, it outputs the clock signal at the SCK0 pin. Eight clock pulses are output per transmitted or received character. When the SCI is not transmitting or receiving, the clock signal remains in the high state. When only receiving, the SCI receives in 2character units, so a 16 pulse synchronization clock is output. To receive in 1-character units, select an external clock source. Transmitting and Receiving Data (SCI Initialization (clock synchronous mode)): Before transmitting, receiving, or changing the mode or communication format, the software must clear the TE and RE bits to 0 in SCSCR, then initialize the SCI. Clearing TE to 0 sets TDRE to 1 and initializes the SCTSR. Clearing RE to 0, however, does not initialize the RDRF, PER, FER, and ORER flags and SCRDR, which retain their previous contents. Figure 14.18 is a sample flowchart for initializing the SCI. Initialize Clear TE and RE bits in SCSCR to 0 Set RIE, TIE, TEIE, MPIE, CKE1, and CKE0 bits in SCSCR (TE and RE are 0) Set transmit/receive format in SCSMR Set value in SCBRR Wait Has a 1-bit period elapsed? Yes Set TE and RE bits in SCSCR to 1 and set RIE, TIE, TEIE, and MPIE bits No 1. Select the clock source in the SCSCR. Leave RIE, TIE, TEIE, MPIE, TE and RE cleared to 0. 2. Select the communication format in the SCSMR. 3. Write the value corresponding to the bit rate in SCBRR unless an external clock is used. 4. Wait for at least the interval required to transmit or receive one bit, then set TE or RE in the SCSCR to 1. Also set RIE, TIE, TEIE and MPIE. Setting TE and RE allows use of the TxD0 and RxD0 pins. End Figure 14.18 Sample Flowchart for SCI Initialization Rev. 4.00, 03/04, page 390 of 660 Transmitting Serial Data (Clock Synchronous Mode): Figure 14.19 shows a sample flowchart for transmitting serial data. Transmission of serial data should be carried out in the following procedure after setting the SCI in a transmission-enabled state. Start transmission Read TDRE bit in SCSSR No TDRE = 1? Yes Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 1. SCI status check and transmit data write: Read the serial status register (SCSSR), check that the TDRE bit is 1, then write transmit data in the transmit data register (SCTDR) and clear TDRE to 0. 2. To continue transmitting serial data: Read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0. All data transmitted? Yes Read TEND bit in SCSSR No TEND = 1? Yes Clear TE bit in SCSCR to 0 End transmission No Figure 14.19 Sample Flowchart for Serial Transmitting Rev. 4.00, 03/04, page 391 of 660 In transmitting serial data, the SCI operates as follows: 1. The SCI monitors the TDRE bit in the SCSSR. When TDRE is cleared to 0 the SCI recognizes that the SCTDR contains new data and loads this data from the SCTDR into the SCTSR. 2. After loading the data from the SCTDR into the SCTSR, the SCI sets the TDRE bit to 1 and starts transmitting. If the transmit-data-empty interrupt enable bit (TIE) in the SCSCR is set to 1, the SCI requests a transmit-data-empty interrupt (TXI) at this time. If clock output mode is selected, the SCI outputs eight synchronous clock pulses. If an external clock source is selected, the SCI outputs data in synchronization with the input clock. Data are output from the TxD0 pin in order from the LSB (bit 0) to the MSB (bit 7). 3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI loads data from the SCTDR into the SCTSR, then begins serial transmission of the next frame. If TDRE is 1, the SCI sets the TEND bit in the SCSSR to 1, transmits the MSB, then holds the transmit data pin (TxD0) in the MSB state. If the TEIE in the SCSCR is set to 1, a transmit-end interrupt (TEI) is requested at this time. 4. After the end of serial transmission, the SCK0 pin is held in the high state. Figure 14.20 shows an example of SCI transmit operation. Transfer direction Synchronization clock LSB Serial data Bit 0 Bit 1 MSB Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Writes data to TDR with the TXI interrupt processing routine and clears TDRE bit to 0 1 frame TXI interrupt request generated TEI interrupt request generated Figure 14.20 Example of SCI Transmit Operation Rev. 4.00, 03/04, page 392 of 660 Receiving Serial Data (Clock Synchronous Mode): Figure 14.21 shows a sample flowchart for receiving serial data. Serial data reception should be carried out in the procedure described below after setting the SCI in a reception-enabled state. When switching from the asynchronous mode to the clock synchronous mode, make sure that ORER, PER, and FER are cleared to 0. If PER or FER is set to 1, the RDRF bit will not be set and both transmitting and receiving will be disabled. Start reception Read ORER bit in SCSSR Yes ORER = 1? No Read RDRF bit in SCSSR No Error processing RDRF = 1? Yes No ORER = 1? Yes Overrun error processing Read receive data in SCRDR and clear RDRF bit in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End reception Clear ORER bit in SCSSR to 0 End 1. Receive error processing: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 2. SCI status check and receive data read: Read the SCSSR, check that RDRF is set to 1, then read receive data from the SCRDR and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 3. To continue receiving serial data: Read SCRDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Figure 14.21 Sample Flowchart for Serial Data Receiving Rev. 4.00, 03/04, page 393 of 660 In receiving, the SCI operates as follows: 1. The SCI synchronizes with serial clock input or output and initializes internally. 2. Receive data is stored into the SCRSR in order from the LSB to the MSB. After receiving the data, the SCI checks that RDRF is 0 so that receive data can be loaded from the SCRSR into the SCRDR. If this check is passed, the SCI sets RDRF to 1 and stores the received data in the SCRDR. If the check is not passed (receive error), the SCI operates as indicated in table 14.11. This state prevents further transmission or reception. While receiving, the RDRF bit is not set to 1. Be sure to clear the error flag. 3. After setting RDRF to 1, if the RIE is set to 1 in the SCSCR, the SCI requests a receive-datafull interrupt (RXI). If the ORER bit is set to 1 and the RIE in the SCSCR is also set to 1, the SCI requests a receive-error interrupt (ERI). Figure 14.22 shows an example of the SCI receive operation. Transfer direction Synchronization clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 RDRF ORER RXI interrupt request generated Reads data with the RXI interrupt processing routine and clears RDRF bit to 0 1 frame RXI interrupt request generated ERI interrupt request generated by overrun error Figure 14.22 Example of SCI Receive Operation Rev. 4.00, 03/04, page 394 of 660 Transmitting and Receiving Serial Data Simultaneously (Clock Synchronous Mode): Figure 14.23 shows a sample flowchart for transmitting and receiving serial data simultaneously. Simultaneous transmission and reception of serial data should be carried out in the following procedure after setting the SCI in a transmission/reception-enabled state. Start transmission/reception Read TDRE bit in SCSSR No TDRE = 1? Yes Write transmission data to SCTDR and clear TDRE bit in SCSSR to 0 Read ORER bit in SCSSR Yes ORER = 1? No Error processing 1. SCI status check and transmit data write: Read the SCSSR, check that the TDRE bit is 1, then write transmit data in the SCTDR and clear TDRE to 0. The TXI interrupt can also be used to determine if the TDRE bit has changed from 0 to 1. 2. Receive error processing: If a receive error occurs, read the ORER bit in SCSSR to identify the error. After executing the necessary error processing, clear ORER to 0. Transmitting/receiving cannot resume if ORER remains set to 1. 3. SCI status check and receive data read: Read the SCSSR, check that RDRF is set to 1, then read receive data from the SCRDR and clear RDRF to 0. The RXI interrupt can also be used to determine if the RDRF bit has changed from 0 to 1. 4. To continue transmitting and receiving serial data: Read the RDRF bit and SCRDR, and clear RDRF to 0 before the frame MSB (bit 7) of the current frame is received. Also read the TDRE bit to check whether it is safe to write (if it reads 1); if so, write data in SCTDR, then clear TDRE to 0 before the MSB (bit 7) of the current frame is transmitted. Read RDRF bit in SCSSR No RDRF = 1? Yes Read receive data of SCRDR and clear RDRF bit in SCSSR to 0 No All data transmitted/received? Yes Clear TE and RE bits in SCSCR to 0 End transmission/reception Note: In switching from transmitting or receiving to simultaneous transmitting and receiving, clear both TE and RE to 0, then set both TE and RE to 1. Figure 14.23 Sample Flowchart for Serial Data Transmitting/Receiving Rev. 4.00, 03/04, page 395 of 660 14.5 SCI Interrupt Sources The SCI has four interrupt sources in each channel: Transmit-end (TEI), receive-error (ERI), receive-data-full (RXI), and transmit-data-empty (TXI). Table 14.12 lists the interrupt sources and indicates their priority. These interrupts can be enabled and disabled by the TIE, RIE, and TEIE bits in SCSCR. Each interrupt request is sent separately to the interrupt controller. TXI is requested when the TDRE bit in the SCSSR is set to 1. RXI is requested when the RDRF bit in the SCSSR is set to 1. ERI is requested when the ORER, PER, or FER bit in the SCSSR is set to 1. TEI is requested when the TEND bit in the SCSSR is set to 1. Where the TXI interrupt indicates that transmit data writing is enabled, the TEI interrupt indicates that the transmit operation is complete. Table 14.12 SCI Interrupt Sources Interrupt Source ERI RXI TXI TEI Description Receive error (ORER, PER, or FER) Receive data full (RDRF) Transmit data empty (TDRE) Transmit end (TEND) Low Priority When Reset Is Cleared High See section 4, Exception Processing, for information on the priority order and relationship to nonSCI interrupts. Rev. 4.00, 03/04, page 396 of 660 14.6 Usage Note Note the following points when using the SCI. SCTDR Writing to and TDRE Flag: The TDRE bit in SCSSR is a status flag indicating loading of transmit data from the SCTDR into the SCTSR. The SCI sets TDRE to 1 when it transfers data from the SCTDR to the SCTSR. Data can be written to the SCTDR regardless of the TDRE bit state. If new data is written in the SCTDR when TDRE is 0, however, the old data stored in the SCTDR will be lost because the data has not yet been transferred to the SCTSR. Before writing transmit data to the SCTDR, be sure to check that TDRE is set to 1. Simultaneous Multiple Receive Errors: Table 14.13 indicates the state of the SCSSR status flags when multiple receive errors occur simultaneously. When an overrun error occurs, the SCRSR contents cannot be transferred to the SCRDR, so receive data is lost. Table 14.13 SCSSR Status Flags and Transfer of Receive Data SCSSR Status Flags Receive Error Status Overrun error Framing error Parity error Overrun error + framing error Overrun error + parity error Framing error + parity error Overrun error + framing error + parity error RDRF 1 0 0 1 1 0 1 ORER 1 0 0 1 1 0 1 FER PER 0 1 0 1 0 1 1 0 0 1 0 1 1 1 Receive Data Transfer SCRSR SCRDR X O O X X O X Notes: X: Receive data is not transferred from SCRSR to SCRDR. O: Receive data is transferred from SCRSR to SCRDR. Break Detection and Processing: Break signals can be detected by reading the RxD0 pin directly when a framing error (FER) is detected. In the break state, the input from the RxD0 pin consists of all 0s, so FER is set and the parity error flag (PER) may also be set. In the break state, the SCI receiver continues to operate, so if the FER bit is cleared to 0, it will be set to 1 again. Sending a Break Signal: The TxD0 pin I/O condition and level can be determined by means of the SCP0DT bit of the SCPDR and bits SCP0MD0 and SCP0MD1 of the SCPCR. These bits can be used to send breaks. To send a break during serial transmission, clear the SCP0DT bit to 0 (designating low level), then clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD0 pin. Rev. 4.00, 03/04, page 397 of 660 TEND Flag and TE Bit Processing: The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is confirmed. Receive Error Flags and Transmitter Operation (Clock Synchronous Mode Only): When a receive error flag (ORER, PER, or FER) is set to 1, the SCI will not start transmitting even if TDRE is set to 1. Be sure to clear the receive error flags to 0 before starting to transmit. Note that clearing RE to 0 does not clear the receive error flags. Receive Data Sampling Timing and Receive Margin in the Asynchronous Mode: In the asynchronous mode, the SCI operates on a base clock of 16 times the transfer rate frequency. In receiving, the SCI synchronizes internally with the falling edge of the start bit, which it samples on the base clock. Receive data is latched on the rising edge of the eighth base clock pulse (figure 14.24). 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Basic clock -7.5 clocks Receive data (RxD0) Synchronization sampling timing Start bit +7.5 clocks D0 D1 Data sampling timing Figure 14.24 Receive Data Sampling Timing in Asynchronous Mode Rev. 4.00, 03/04, page 398 of 660 The receive margin in the asynchronous mode can therefore be expressed as in equation 1. Equation 1: M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5)F - 2N N Where: M = Receive margin (%) N = Ratio of clock frequency to bit rate (N = 16) D = Clock duty cycle (D = 0 to 1.0) L = Frame length (L = 9 to 12) F = Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as in equation 2. Equation 2: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20 to 30%. Cautions for Clock Synchronous External Clock Mode: * Set TE = RE = 1 only when the external clock SCK0 is 1. * Do not set TE = RE = 1 until at least four clocks after the external clock SCK0 has changed from 0 to 1. * When receiving, RDRF is 1 when RE is set to zero 2.5-3.5 clocks after the rising edge of the SCK0 input of the D7 bit in RxD0, but it cannot be copied to SCRDR. Caution for Clock Synchronous Internal Clock Mode: In the receiving, RDRF become 1 when RE is set to 0, 1.5 clocks after the rising edge of the SCK0 output of the D7 bit in RxD0, but it cannot be copied to SCRDR. Rev. 4.00, 03/04, page 399 of 660 Rev. 4.00, 03/04, page 400 of 660 Section 15 Smart Card Interface As an added serial communications interface function, the SCI supports an IC card (smart card) interface that conforms to the data transfer protocol (asynchronous half-duplex character transmission protocol) of the ISO/IEC standard 7816-3 for identification of cards. Register settings are used to switch between the ordinary serial communication interface and the smart card interface. Figure 15.1 is the block diagram of the smart card interface. 15.1 Feature The smart card interface has the following features: * Asynchronous mode Data length: Eight bits Parity bit generation and check Receive mode error signal detection (parity error) Transmit mode error signal detection and automatic re-transmission of data Supports both direct convention and inverse convention * Bit rate can be selected using on-chip baud rate generator. * Three types of interrupts: Transmit-data-empty, receive-data-full, and communication-error interrupts are requested independently. Bus interface Module data bus Internal data bus SCRDR SCTDR SCSCMR SCSSR SCSCR SCSMR Transmit/ receive control SCBRR RxD0 SCRSR SCTSR Baud rate generator P P/4 P/16 P/64 TxD0 Parity generation Parity check Clock External clock TXI RXI ERI SCK0 SCI Legend SCSCMR: SCRSR: SCRDR: SCTSR: SCTDR: Smart card mode register Receive shift register Receive data register Transmit shift register Transmit data register SCSMR: SCSCR: SCSSR: SCBRR: Serial mode register Serial control register Serial status register Bit rate register Figure 15.1 Smart Card Interface Block Diagram Rev. 4.00, 03/04, page 401 of 660 15.2 Input/Output Pin Table 15.1 summarizes the smart card interface pins. Table 15.1 Pin Configuration Pin Name Serial clock pin Receive data pin Transmit data pin Abbreviation I/O SCK0 RxD0 TxD0 Output Input Output Function Clock output Receive data input Transmit data output 15.3 Register Description The smart card interface has the following registers. The SCSMR, SCBRR, SCSCR, SCTDR, and SCRDR registers are the same as those of the SCI. So see the register description in section 14, Serial Communication Interface. Refer to see section 23, List of Registers, for more details of the addresses and access sizes. * Smart card mode register (SCSCMR) * Serial status register (SCSSR) * Serial mode register (SCSMR) * Bit rate register (SCBRR) * Serial control register (SCSCR) * Transmit data register (SCTDR) * Receive data register (SCRDR) Rev. 4.00, 03/04, page 402 of 660 15.3.1 Smart Card Mode Register (SCSCMR) The smart card mode register (SCSCMR) is an 8-bit read/write register that selects smart card interface functions. Bit 7 to 4 3 Bit Name -- SDIR Initial Value -- 0 R/W R R/W Description Reserved An undefined value are read from these bits. Smart Card Data Transfer Direction Selects the serial/parallel conversion format. 0: Contents of SCTDR are transferred as LSB first, receive data is stored in SCRDR as LSB first. 1: Contents of SCTDR are transferred as MSB first, receive data is stored in SCRDR as MSB first. 2 SINV 0 R/W Smart Card Data Inversion Specifies whether to invert the logic level of the data. This function is used in combination with bit 3 for transmitting and receiving with an inverse convention card. SINV does not affect the logic level of the parity bit. See section 15.4.4, Register Settings, for information on how parity is set. 0: Contents of SCTDR are transferred unchanged, receive data is stored in SCRDR unchanged. 1: Contents of SCTDR are inverted before transfer, receive data is inverted before storage in SCRDR. 1 0 -- SMIF -- 0 R R/W Reserved An undefined value is read from this bit. Smart Card Interface Mode Select Enables the smart card interface function. 0: Smart card interface function disabled 1: Smart card interface function enabled Rev. 4.00, 03/04, page 403 of 660 15.3.2 Serial Status Register (SCSSR) In the smart card interface mode, the function of bit 4 in SCSSR of the SCI is changed as shown blow. Relating to this, the setting conditions for bit 2, the TEND bit, are also changed. Bit 7 6 5 Bit Name TDRE RDRF ORER Initial Value 1 0 0 R/W Description R/(W)* Transmit Data Register Empty R/(W)* Receive Register Full R/(W)* Overrun Error These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. 4 ERS 0 R/(W)* Error Signal Status In the smart card interface mode, bit 4 indicates the state of the error signal returned from the receiving side during transmission. The smart card interface cannot detect framing errors. 0: Receiving ended normally with no error signal. [Clearing conditions] 1. The chip is reset or enters standby mode. 2. ERS is read as 1, then written to with 0. 1: An error signal indicating a parity error was transmitted from the receiving side. [Setting condition] The error signal sampled is low. Note: The ERS flag maintains its state even when the TE bit in SCSCR is cleared to 0. Rev. 4.00, 03/04, page 404 of 660 Bit 3 2 1 0 Bit Name PER TEND MPB MPBT Initial Value 0 1 0 0 R/W Description R/(W)* Parity error R R R/W Transmission end Multiprocessor bit Multiprocessor bit transfer These bits have the same function as in the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. The setting conditions for bit 2, the transmit end bit (TEND), are changed as follows. 0: Transmission is in progress. [Clearing condition] TDRE is read as 1, then written to with 0. 1: End of transmission. [Setting conditions] 1. The chip is reset or enters standby mode. 2. TE bit in SCSCR is 0 and the FER/ERS bit is also 0. 3. C/A bit in SCSMR is 0, and TDRE = 1 and FER/ERS = 0 (normal transmission) 2.5 etu after a one-byte serial character is transmitted. 4. C/A bit in SCSMR is 1, and TDRE = 1 and FER/ERS = 0 (normal transmission) 1.0 etu after a one-byte serial character is transmitted. Note: etu is an abbreviation of elementary time unit, which is the period for the transfer of 1 bit. Note: * Only 0 can be written, to clear the flag. Rev. 4.00, 03/04, page 405 of 660 15.4 15.4.1 Operation Overview The primary functions of the smart card interface are described below. 1. Each frame consists of 8-bit data and a parity bit. 2. During transmission, the card leaves a guard time of at least 2 etu (elementary time units: the period for 1 bit to transfer) from the end of the parity bit to the start of the next frame. 3. During reception, the card outputs an error signal low level for 1 etu after 10.5 etu has elapsed from the start bit if a parity error was detected. 4. During transmission, it automatically transmits the same data after allowing at least 2 etu from the time the error signal is sampled. 5. Only start-stop type asynchronous communication functions are supported; no synchronous communication functions are available. 15.4.2 Pin Connections Figure 15.2 shows the pin connection diagram for the smart card interface. During communication with an IC card, transmission and reception are both carried out over the same data transfer line, so connect the TxD and RxD pins on the chip. Pull up the data transfer line to the power supply VCC side with a resistor. When using the clock generated by the smart card interface on an IC card, input the SCK pin output to the IC card's CLK pin. This connection is not necessary when the internal clock is used on the IC card. Use the chip's port output as the reset signal. Apart from these pins, the power and ground pin connections are usually also required. Note: When the IC card is not connected and both RE and TE are set to 1, closed communication is possible and self-diagnosis can be performed. Rev. 4.00, 03/04, page 406 of 660 VCC TxD0 Data line RxD0 SCK0 Px (port) Clock line IO CLK LSI Reset line RST IC card Connected device Figure 15.2 Pin Connection Diagram for the Smart Card Interface 15.4.3 Data Format Figure 15.3 shows the data format for the smart card interface. In this mode, parity is checked every frame while receiving and error signals sent to the transmitting side whenever an error is detected so that data can be re-transmitted. During transmission, if an error signal is sampled, the same data is re-transmitted. With no parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Transmitting station output With parity error Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Transmitting station output Receiving station output Ds: D0 to D7: Dp: DE: Start bit Data bits Parity bit Error signal Figure 15.3 Data Format for Smart Card Interface Rev. 4.00, 03/04, page 407 of 660 The operating sequence is: 1. The data line is high impedance when not in use and is fixed high with a pull-up resistor. 2. The transmitting side starts one frame of data transmission. The data frame starts with a start bit (Ds, low level). The start bit is followed by eight data bits (D0 to D7) and a parity bit (Dp). 3. On the smart card interface, the data line returns to high impedance after this. The data line is pulled high with a pull-up resistor. 4. The receiving side checks parity. When the data is received normally with no parity errors, the receiving side then waits to receive the next data. When a parity error occurs, the receiving side outputs an error signal (DE, low level) and requests re-transfer of data. The receiving station returns the signal line to high impedance after outputting the error signal for a specified period. The signal line is pulled high with a pull-up resistor. 5. The transmitting side transmits the next frame of data unless it receives an error signal. If it does receive an error signal, it returns to step 2 to re-transmit the erroneous data. 15.4.4 Register Settings Table 15.2 shows the bit map of the registers that the smart card interface uses. Bits shown as 1 or 0 must be set to the indicated value. The settings for the other bits are described below. Table 15.2 Register Settings for the Smart Card Interface Register SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR Address H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A Bit 7 C/A BRR7 TIE TDR7 TDRE RDR7 -- Bit 6 0 BRR6 RIE TDR6 RDRF RDR6 -- Bit 5 1 BRR5 TE TDR5 ORER RDR5 -- Bit 4 O/E BRR4 RE TDR4 FER/ ERS RDR4 -- Bit 3 1 BRR3 0 TDR3 PER RDR3 SDIR Bit 2 0 BRR2 0 TDR2 TEND RDR2 SINV Bit 1 CKS1 BRR1 CKE1 TDR1 0 RDR1 -- Bit 0 CKS0 BRR0 CKE0 TDR0 0 RDR0 SMIF SCSCMR H'FFFFFE8C Note: Dashes indicate unused bits. 1. Setting the serial mode register (SCSMR): The C/A bit selects the set timing of the TEND flag, and selects the clock output state with the combination of bits CKE1 and CKE0 in the SCSCR. Set the O/E bit to 0 when the IC card uses the direct convention or to 1 when it uses the inverse convention. Select the on-chip baud rate generator clock source with the CKS1 and CKS0 bits (see section 15.4.5, Clock). 2. Setting the bit rate register (SCBRR): Set the bit rate. See section 15.4.5, Clock, to see how to calculate the set value. Rev. 4.00, 03/04, page 408 of 660 3. Setting the serial control register (SCSCR): The TIE, RIE, TE and RE bits function as they do for the ordinary SCI. See section 14, Serial Communication Interface (SCI), for more information. The CKE0 bit specifies the clock output. When no clock is output, set 0; when a clock is output, set 1. 4. Setting the smart card mode register (SCSCMR): The SDIR and SINV bits are both set to 0 for IC cards that use the direct convention and both to 1 when the inverse convention is used. The SMIF bit is set to 1 for the smart card interface. Figure 15.4 shows sample waveforms for register settings of the two types of IC cards (direct convention and inverse convention) and their start characters. In the direct convention type, the logical 1 level is state Z, the logical 0 level is state A, and communication is LSB first. The start character data is H'3B. The parity bit is even (as specified in the smart card standards), and thus 1. In the inverse convention type, the logical 1 level is state A, the logical 0 level is state Z, and communication is MSB first. The start character data is H'3F. The parity bit is even (as specified in the smart card standards), and thus 0, which corresponds to state Z. Only data bits D7 to D0 are inverted by the SINV bit. To invert the parity bit, set the O/E bit in SCSMR to odd parity mode. This applies to both transmission and reception. (Z) A Ds Z D0 Z D1 A D2 Z D3 Z D4 Z D5 A D6 A D7 Z Dp (Z) State a. Direct convention (SDIR, SINV, and O/ are all 0) (Z) A Ds Z D7 Z D6 A D5 A D4 A D3 A D2 A D1 A D0 Z Dp (Z) State b. Inverse convention (SDIR, SINV, and O/ are all 1) Figure 15.4 Waveform of Start Character Rev. 4.00, 03/04, page 409 of 660 15.4.5 Clock Only the internal clock generated by the on-chip baud rate generator can be used as the communication clock in the smart card interface. The bit rate for the clock is set by the SCBRR and the CKS1 and CKS0 bits in the SCSMR, and is calculated using the equation below. Table 15.4 shows sample bit rates. If clock output is then selected by setting CKE0 to 1, a clock with a frequency 372 times the bit rate is output from the SCK0 pin. B= P x 106 1488 x 22n-1 x (N + 1) Where: N = Value set in SCBRR (0 N 255) B = Bit rate (bit/s) P = Peripheral module operating frequency (MHz) n = 0 to 3 (table 15.3) Table 15.3 Relationship of n to CKS1 and CKS0 n 0 1 2 3 CKS1 0 0 1 1 CKS0 0 1 0 1 Table 15.4 Examples of Bit Rate B (Bit/s) for SCBRR Settings (n = 0) P (MHz) N 0 1 2 7.1424 9600.0 4800.0 3200.0 10.00 13440.9 6720.4 4480.3 10.7136 14400.0 7200.0 4800.0 13.00 17473.1 8736.6 5824.4 14.2848 19200.0 9600.0 6400.0 16.00 21505.4 10752.7 7168.5 18.00 24193.5 12096.8 8064.5 Note: The bit rate is rounded to two decimal places. Calculate the value to be set in the bit rate register (SCBRR) from the operating frequency and the bit rate. N is an integer in the range 0 N 255, specifying a smallish error. N= P x 106 - 1 1488 x 22n-1 x B Rev. 4.00, 03/04, page 410 of 660 Table 15.5 Examples of SCBRR Settings for Bit Rate B (Bit/s) (n = 0) (MHz) (9600 Bits/s) 7.1424 N 0 Error 0.00 N 1 10.00 Error 30.00 N 1 10.7136 Error 25.00 N 1 13.00 Error 8.99 N 1 14.2848 Error 0.00 N 1 16.00 Error 12.01 N 2 18.00 Error 15.99 Table 15.6 Maximum Bit Rates for Frequencies (Smart Card Interface Mode) P (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 Maximum Bit Rate (Bit/s) 9600 13441 14400 17473 19200 21505 24194 N 0 0 0 0 0 0 0 n 0 0 0 0 0 0 0 The bit rate error is found as follows: Error (%) = ( P x 106 - 1) x 100 1488 x 22n-1 x B x (N + 1) Table 15.5 shows example settings of SCBRR, and table 15.6 shows the maximum bit rate for each frequency. Table 15.7 shows the relationship between transmit/receive clock register set values and output states on the smart card interface. Rev. 4.00, 03/04, page 411 of 660 Table 15.7 Register Set Values and SCK Pin Register Value Setting 1* 1 SCK Pin CKE0 0 1 0 1 0 1 High output Low output Output Port State Determined by setting of port register SCP1MD1 and SCP1MD0 bits SCK0 (serial clock) output state Low output state SCK0 (serial clock) output state High output state SCK0 (serial clock) output state SMIF 1 1 C/A A 0 0 1 1 1 1 CKE1 0 0 0 0 1 1 2* 2 1 1 3* 2 1 1 Notes: 1. The SCK0 output state changes as soon as the CKE0 bit is modified. The CKE1 bit should be cleared to 0. 2. The clock duty remains constant despite stopping and starting of the clock by modification of the CKE0 bit. 15.4.6 Data Transmission and Reception Initialization: Initialize the SCI using the following procedure before sending or receiving data. Initialization is also required for switching from transmit mode to receive mode or from receive mode to transmit mode. Figure 15.5 shows an example of initialization process flowchart. 1. Clear TE and RE in SCSCR to 0. 2. Clear error flags FER/ERS, PER, and ORER to 0 in SCSSR. 3. Set the C/A bit, parity bit (O/E bit), and baud rate generator select bits (CKS1 and CKS0 bits) in SCSMR. At this time also clear the CHR and MP bits to 0 and set the STOP and PE bits to 1. 4. Set the SMIF, SDIR, and SINV bits in SCSCMR. When the SMIF bit is set to 1, the TxD and RxD pins both switch from ports to SCI pins and become high impedance. 5. Set the value corresponding to the bit rate in SCBRR. 6. Set the clock source select bits (CKE1 and CKE0 bits) in SCSCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0. When the CKE0 bit is set to 1, a clock is output from the SCK pin. 7. After waiting at least 1 bit, set the TIE, RIE, TE, and RE bits in SCSCR. Do not set the TE and RE bits simultaneously unless performing self-diagnosis. Rev. 4.00, 03/04, page 412 of 660 Initialize Clear TE and RE bits in SCSCR to 0 Clear SCSSR's FER/ERS, PER and ORER flags to 0 Set SCSMR's O/ bit to parity, set CKS1 and CKS0 bits to the clock and set C/ Set SCSMR's SMIF, SDIR, and SINV bits Set value in SCBRR Set SCSCR's CKE1 and CKE0 bits to the clock and clear TIE, RIE, TE, RE, MPIE, and TEIE bits to 0 Wait Has a 1-bit interval elapsed? Yes Set SCSCR's TIE, RIE, TE, and RE bits No End Figure 15.5 Initialization Flowchart (Example) Serial Data Transmission: The processing procedures in the smart card mode differ from ordinary SCI processing because data is retransmitted when an error signal is sampled during a data transmission. An example of transmission processing flowchart is shown in figure 15.6. 1. Initialize the smart card interface mode as described in Initialization above. 2. Check that the FER/ERS bit in SCSSR is cleared to 0. 3. Repeat steps 2 and 3 until the TEND flag in SCSSR is set to 1. 4. Write the transmit data into SCTDR, clear the TDRE flag to 0 and start transmitting. The TEND flag will be cleared to 0. 5. To transmit more data, return to step 2. 6. To end transmission, clear the TE bit to 0. Rev. 4.00, 03/04, page 413 of 660 This processing can be interrupted. When the TIE bit is set to 1 and interrupt requests are enabled, a transmit-data-empty interrupt (TXI) will be requested when the TEND flag is set to 1 at the end of the transmission. When the RIE bit is set to 1 and interrupt requests are enabled, a communication error interrupt (ERI) will be requested when the ERS flag is set to 1 when an error occurs in transmission. See Interrupt Operation below for more information. Start Initialize Start transmission FER/ERS = 0? Yes No Error processing No TEND = 1? Yes Write transmit data in SCTDR and clear TDRE flag in SCSSR to 0 No All data transmitted? Yes No FER/ERS = 0? Yes Error processing No TEND = 1? Yes Clear TE bit in SCSCR to 0 End transmission Figure 15.6 Transmission Flowchart Serial Data Reception: The processing procedures in the smart card mode are the same as in ordinary SCI processing. The reception processing flowchart is shown in figure 15.7. Rev. 4.00, 03/04, page 414 of 660 1. Initialize the smart card interface mode as described above in Initialization and in figure 15.5. 2. Check that the ORER and PER flags in SCSSR are cleared to 0. If either flag is set, clear both to 0 after performing the appropriate error processing procedures. 3. Repeat steps 2 and 3 until the RDRF flag is set to 1. 4. Read the receive data from SCRDR. 5. To receive more data, clear the RDRF flag to 0 and return to step 2. 6. To end reception, clear the RE bit to 0. This processing can be interrupted. When the RIE bit is set to 1 and interrupt requests are enabled, a receive-data-full interrupt (RXI) will be requested when the RDRF flag is set to 1 at the end of the reception. When an error occurs during reception and either the ORER or PER flag is set to 1, a communication error interrupt (ERI) will be requested. See Interrupt Operation below for more information. The received data will be transferred to SCRDR even when a parity error occurs during reception and PER is set to 1, so this data can still be read. Start Initialize Start reception ORER = 0 or PER = 0? Yes No Error processing No RDRF = 1? Yes Write receive data from SCRDR and clear RDRF flag in SCSSR to 0 No All data received? Yes Clear RE bit in SCSCR to 0 End reception Figure 15.7 Reception Flowchart (Example) Rev. 4.00, 03/04, page 415 of 660 Switching Modes: When switching from receive mode to transmit mode, check that the receive operation is completed before starting initialization and setting RE to 0 and TE to 1. The RDRF, PER, and ORER flags can be used to check if reception is completed. When switching from transmit mode to receive mode, check that the transmit operation is completed before starting initialization and setting TE to 0 and RE to 1. The TEND flag can be used to check if transmission is completed. Interrupt Operation: In the smart card interface mode, there are three types of interrupts: transmit-data-empty (TXI), communication error (ERI) and receive-data-full (RXI). In this mode, the transmit-end interrupt (TEI) cannot be requested. Set the TEND flag in SCSSR to 1 to request a TXI interrupt. Set the RDRF flag in SCSSR to 1 to request an RXI interrupt. Set the ORER, PER, or FER/ERS flag in SCSSR to 1 to request an ERI interrupt (table 15.8). Table 15.8 Smart Card Mode Operating State and Interrupt Sources Mode Transmit mode State Normal Error Receive mode Normal Error Flag TEND FER/ERS RDRF PER, ORER Mask Bit TIE RIE RIE RIE Interrupt Source TXI ERI RXI ERI 15.5 Usage Note When the SCI is used as a smart card interface, be sure that all criteria in sections 15.4.1 and 15.4.2 are applied. Receive Data Timing and Receive Margin in Asynchronous Mode: In asynchronous mode, the SCI runs on a basic clock with a frequency of 372 times the transfer rate. During reception, the SCI samples the falling of the start bit using the base clock to achieve internal synchronization. Receive data is latched internally on the rising edge of the 186th basic clock cycle (figure 15.8). Rev. 4.00, 03/04, page 416 of 660 372 clock cycles 186 clock cycles 0 Base clock 185 371 0 185 371 0 Receive data (RxD) Synchronization sampling timing Start bit D0 D1 Data sampling timing Figure 15.8 Receive Data Sampling Timing in Smart Card Mode The receive margin is found from the following equation: For smart card mode: M = (0.5 - 1 D - 0.5 (1 + F) x 100% ) - (L - 0.5)F - 2N N Where: M = Receive margin (%) N = Ratio of bit rate to clock (N = 372) D = Clock duty (D = 0 to 1.0) L = Frame length (L = 10) F = Absolute value of clock frequency deviation Using this equation, the receive margin when F = 0 and D = 0.5 is as follows: When D = 0.5 and F = 0: M = (0.5 - 1/2 x 372) x 100% = 49.866% Rev. 4.00, 03/04, page 417 of 660 Retransmission (Receive and Transmit Modes): Retransmission by the SCI in Receive Mode: Figure 15.9 shows the retransmission operation in the SCI receive mode. 1. When the received parity bit is checked and an error is found, the PER bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the PER bit before the next parity bit is sampled. 2. The RDRF bit in SCSSR is not set in the frame that caused the error. 3. When the received parity bit is checked and no error is found, the PER bit in SCSSR is not set. 4. When the received parity bit is checked and no error is found, reception is considered to have been completed normally and the RDRF bit in SCSSR is automatically set to 1. If the RIE bit in SCSCR is enabled at this time, an RXI interrupt is requested. 5. When a normal frame is received, the pin maintains a three-state state when it transmits the error signal. nth transfer frame Retransmitted frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE RDRF *2 PER *1 *3 *4 Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp *5 Ds D0 D1 D2 D3 D4 Transfer frame n + 1 Notes: 1. 2. 3. 4. 5. This portion corresponds to the This portion corresponds to the This portion corresponds to the This portion corresponds to the This portion corresponds to the above explanation 1. above explanation 2. above explanation 3. above explanation 4. above explanation 5. Figure 15.9 Retransmission in SCI Receive Mode Rev. 4.00, 03/04, page 418 of 660 Retransmission by the SCI in Transmit Mode: Figure 15.10 shows the retransmission operation in the SCI transmit mode. 1. After transmission of one frame is completed, the FER/ERS bit in SCSSR is set to 1 when a error signal is returned from the receiving side. If the RIE bit in SCSCR is enabled at this time, an ERI interrupt is requested. Be sure to clear the FER/ERS bit before the next parity bit is sampled. 2. The TEND bit in SCSSR is not set in the frame that received the error signal that indicated the error. 3. The FER/ERS bit in SCSSR is not set when no error signal is returned from the receiving side. 4. When no error signal is returned from the receiving side, the TEND bit in SCSSR is set to 1 when the transmission of the frame that includes the retransmission is considered completed. If the TIE bit in SCSCR is enabled at this time, a TXI interrupt will be requested. nth transfer frame Retransmitted frame (DE) Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp Ds D0 D1 D2 D3 D4 Transfer frame n + 1 TDRE Transfer from TDR to TRS TEND *2 FER/ERS *1 *3 *4 Transfer from TDR to TRS Transfer from TDR to TRS Notes: 1. 2. 3. 4. This portion corresponds to the above explanation 1. This portion corresponds to the above explanation 2. This portion corresponds to the above explanation 3. This portion corresponds to the above explanation 4. Figure 15.10 Retransmission in SCI Transmit Mode Support for Block Transfer Mode : This smart card interface conforms to the T = 0 (character transfer) protocols of ISO/IEC7816-3. As a result, this smart card interface does not support block transfer, in which error signals are neither sent nor detected, and data is not automatically retransmitted. Rev. 4.00, 03/04, page 419 of 660 Rev. 4.00, 03/04, page 420 of 660 Section 16 Serial Communication Interface with FIFO (SCIF) This LSI has single-channel serial communication interface with FIFO (SCIF) that supports asynchronous serial communication. It also has 16-stage FIFO registers for both transfer and receive that enables this LSI efficient high-speed continuous communication. Figure 16.1 shows a diagram of the SCIF, and figures 16.2 to 16.4 show the I/O ports. 16.1 Feature * Asynchronous serial communication Serial data communications are performed by start-stop in character units. The SCI can communicate with a universal asynchronous receiver/transmitter (UART), an asynchronous communication interface adapter (ACIA), or any other communications chip that employs a standard asynchronous serial system. There are eight selectable serial data communication formats. Data length: Seven or eight bits Stop bit length: One or two bits Parity: Even, odd, or none Receive error detection: Parity and framing errors Break detection: * Full duplex communication The transmitting and receiving sections are independent, so the SCI can transmit and receive simultaneously. Both sections use 16-stage FIFO buffering, so high-speed continuous data transfer is possible in both the transmit and receive directions. * On-chip baud rate generator with selectable bit rates * Internal or external transmit/receive clock source From either baud rate generator (internal) or SCK2 pin (external) * Four types of interrupts Transmit-FIFO-data-empty, break, receive-FIFO-data-full, and receive-error interrupts are requested independently. The direct memory access controller (DMAC) can be activated to execute a data transfer by a transmit-FIFO-data-empty or receive-FIFO-data-full interrupt. * When the SCIF is not in use, it can be stopped by halting the clock supplied to it, saving power. * On-chip modem control functions (RTS2 and CTS2) * The quantity of data in the transmit and receive FIFO registers and the number of receive errors of the receive data in the receive FIFO register can be known. * The time-out error (DR) can be detected in receiving. Rev. 4.00, 03/04, page 421 of 660 Bus interface Module data bus Internal data bus SCPCR SCFRDR2 (16 stages) SCFTDR2 (16 stages) SCPDR SCFDR2 SCFCR2 SCSSR2 SCSCR2 RxD2 SCRSR2 SCTSR2 SCSMR2 Transmit/ receive control TxD2 Parity generation Parity check External clock SCK2 TEI TXI RXI BVRI SCIF Legend SCRSR2: SCFRDR2: SCTSR2: SCFTDR2: SCSMR2: SCSCR2: Receive shift register 2 Receive FIFO data register 2 Transmit shift register 2 Transmit FIFO data register 2 Serial mode register 2 Serial control register 2 SCSSR2: SCBRR2: SCFCR2: SCFDR2: SCPDR: SCPCR: Serial status register 2 Bit rate register 2 FIFO control register 2 Number of FIFO data register 2 Port SC data register Port SC control register Clock Baud rate generator P P/4 P/16 P/64 SCBRR2 Figure 16.1 SCIF Block Diagram Rev. 4.00, 03/04, page 422 of 660 Reset R D SCP3MD0 Q C PCRW Reset R D SCP3MD1 C PCRW Reset SCPT[3]/SCK2 R Q D SCP3DT1 C PDRW Output enable Serial clock output Clock input enable Internal data bus SCIF PDRR* Serial clock input Legend PDRW: SCPDR write PDRR: SCPDR read PCRW: SCPCR write Note: * When reading the SCK2 pin, clear the CKE1 and CKE0 bits in SCSCR to 0, and set the SCP3MD1 bit in SCSPR to 1. Figure 16.2 SCPT[3]/SCK2 Pin Rev. 4.00, 03/04, page 423 of 660 Reset R D SCP2MD0 Q C PCRW Reset Internal data bus 3 R D SCP2MD1 C PCRW Reset SCPT[2]/TxD2 R Q D SCP2DT1 C PDRW Output enable Legend PCRW: SCPCR write PDRW: SCPDR write Serial transmission output SCIF Figure 16.3 SCPT[2]/TxD2 Pin SCIF SCPT[2]/RxD2 Serial receive data Internal data bus Legend PDRR: SCPDR read PDRR* Note: * When reading the RxD2 pin, set the RE bit in SCSCR to 1. Figure 16.4 SCPT[2]/RxD2 Pin Rev. 4.00, 03/04, page 424 of 660 16.2 Input/Output Pin The SCIF has the I/O pins summarized in table 16.1. Table 16.1 SCIF Pins Pin Name Serial clock pin Receive data pin Transmit data pin Request to send pin Clear to send pin Abbreviation SCK2 RxD2 TxD2 RTS2 CTS2 I/O I/O Input Output Output Input Function Clock I/O Receive data input Transmit data output Request to send Clear to send 16.3 Register Description SCIF has the registers listed below. These registers specify the data format and bit rate, and control the transmitter and receiver sections. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Serial mode register 2 (SCSMR2) * Bit rate register 2 (SCBRR2) * Serial control register 2 (SCSCR2) * Transmit FIFO data register 2 (SCFTDR2) * Serial status register 2 (SCSSR2) * Receive data FIFO register 2 (SCFRDR2) * FIFO control register 2 (SCFCR2) * FIFO data count set register 2 (SCFDR2) * SC port control register (SCPCR) * SC port data register (SCPDR) Rev. 4.00, 03/04, page 425 of 660 16.3.1 Receive Shift Register 2 (SCRSR2) The receive shift register 2 (SCRSR2) is an eight-bit register taht receives serial data. The CPU cannot read from or write to the SCRSR2 directly. Data input at the RxD pin is loaded into the SCRSR2 in the order received, LSB (bit 0) first, converting the data to parallel form. When one byte has been received, it is automatically transferred to the SCFRDR2, which is a receive FIFO register. 16.3.2 Receive FIFO Data Register 2 (SCFRDR2) The 16-byte receive FIFO data register2(SCFRDR2) stores serial receive data. The SCIF completes the reception of one byte of serial data by moving the received data from the SCRSR2 into the SCFRDR2 for storage. Continuous receive is possible until 16 bytes are stored. The CPU can read but not write the SCFRDR2. When data is read without received data in the SCFRFR2, the value is undefined. When the received data in this register becomes full, the subsequent serial data is lost. 16.3.3 Transmit Shift Register 2 (SCTSR2) The transmit shift register 2 (SCTSR2) is an eight-bit register that transmits serial data. The CPU cannot read from or write to the SCTSR2 directly. The SCI loads transmit data from the SCFTDR2 into the SCTSR2, then transmits the data serially from the TxD pin, LSB (bit 0) first. After transmitting one data byte, the SCI automatically loads the next transmit data from the SCFTDR2 into the SCTSR2 and starts transmitting again. 16.3.4 Transmit FIFO Data Register 2 (SCFTDR2) The transmit FIFO data register 2 (SCFTDR2) is a 16-byte FIFO register that stores data for serial transmission. When the SCIF detects that the SCTSR is empty, it moves transmit data written in the SCFTDR2 into the SCTSR2 and starts serial transmission. Continuous serial transmission is performed until the transmit data in the SCFTDR2 becomes empty. The CPU can always write to the SCFTDR2. When the transmit data in the SCFTDR2 is full (16 bytes), next data cannot be written. If attempted to write, the data is ignored. 16.3.5 Serial Mode Register 2 (SCSMR2) The serial mode register2 (SCSMR2) is an eight-bit register that specifies the SCIF serial communication format and selects the clock source for the baud rate generator. The CPU can always read and write the SCSMR2. Rev. 4.00, 03/04, page 426 of 660 Bit 7 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read 0. The write value should always be 0. 6 CHR 0 R/W Character Length Selects seven-bit or eight-bit data in the asynchronous mode. 0: Eight-bit data. 1: Seven-bit data. Note: When seven-bit data is selected, the MSB (bit 7) in SCFTPR2 is not transmitted. 5 PE 0 R/W Parity Enable Selects whether to add a parity bit to transmit data and to check the parity of receive data. 0: Parity bit not added or checked. 1: Parity bit added and checked. Note: When PE is set to 1, an even or odd parity bit is added to transmit data, depending on the parity mode (O/E) setting. Receive data parity is checked according to the even/odd (O/E) mode setting. 4 O/E 0 R/W Parity Mode Selects even or odd parity when parity bits are added and checked. The O/E setting is used only when the PE is set to 1 to enable parity addition and check. The O/E setting is ignored when parity addition and check is disabled. 0: Even parity. Note: If even parity is selected, the parity bit is added to transmit data to make an even number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an even number of 1s in the received character and parity bit combined. 1: Odd parity. Note: If odd parity is selected, the parity bit is added to transmit data to make an odd number of 1s in the transmitted character and parity bit combined. Receive data is checked to see if it has an odd number of 1s in the received character and parity bit combined. Rev. 4.00, 03/04, page 427 of 660 Bit 3 Bit Name STOP Initial Value 0 R/W R/W Description Stop Bit Length Selects one or two bits as the stop bit length. In receiving, only the first stop bit is checked, regardless of the STOP bit setting. If the second stop bit is 1, it is treated as a stop bit, but if the second stop bit is 0, it is treated as the start bit of the next incoming character. 0: One stop bit. Note: In transmitting, a single bit of 1 is added at the end of each transmitted character. 1: Two stop bits. Note:In transmitting, two bits of 1 are added at the end of each transmitted character. 2 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 1 0 CKS1 CKS0 0 0 R/W R/W Clock Select 1 and 0 These bits select the internal clock source of the on-chip baud rate generator. Four clock sources are available. P, P/4, P/16 and P/64. For further information on the clock source, bit rate register settings, and baud rate, see section 16.3.8, Bit Rate Register 2 (SCBRR2). 00: P 01: P/4 10: P/16 11: P/64 Note: P: Peripheral clock Rev. 4.00, 03/04, page 428 of 660 16.3.6 Serial Control Register 2 (SCSCR2) The serial control register 2 (SCSCR2) operates the SCI transmitter/receiver, selects the serial clock output in the asynchronous mode, enables/disables interrupt requests, and selects the transmit/receive clock source. The CPU can always read and write the SCSCR2. Bit 7 Bit Name TIE Initial Value 0 R/W R/W Description Transmit Interrupt Enable Enables or disables the transmit-FIFO-data-empty interrupt (TXI) requested when the serial transmit data is transferred from the SCFTDR2 to SCTSR2, and the quantity of data in the SCFTDR2 becomes less than the specified number of transmission triggers, and then the TDFE flag in the SCSSR2 is set to1. 0: Transmit-FIFO-data-empty interrupt request (TXI) is disabled. Note: The TXI interrupt request can be cleared by writing the greater quantity of transmit data than the specified number of transmission triggers to SCFTDR2 and by clearing TDFE to 0 after reading 1 from TDFE, or can be cleared by clearing TIE to 0. 1: Transmit-FIFO-data-empty interrupt request (TXI) is enabled. 6 RIE 0 R/W Receive Interrupt Enable Enables or disables the receive-data-full (RXI) and receive-error (ERI) interrupts requested when the serial receive data is transferred from the SCRSR2 to SCFRDR2, when the quantity of data in the SCFRDR2 becomes more than the specified number of receive triggers, and when the RDRF flag of SCSSR2 is set to1. 0: Receive-data-full interrupt (RXI), receive-error interrupt (ERI), and receive break interrupt (BRI) requests are disabled. Note: RXI and ERI interrupt requests can be cleared by reading the DR, ER, or RDF flag after it has been set to 1, then clearing the flag to 0, or by clearing RIE to 0. At RDF, read 1 from the RDF flag and clear it to 0, after reading the received data from SCFRDR2 until the quantity of received data becomes less than the specified number of the receive triggers. 1: Receive-data-full interrupt (RXI) and receiveerror interrupt (ERI) requests are enabled. Rev. 4.00, 03/04, page 429 of 660 Bit 5 Bit Name TE Initial Value 0 R/W R/W Description Transmit Enable Enables or disables the SCIF serial transmitter. 0: Transmitter disabled. 1: Transmitter enabled. Note: Serial transmission starts after writing of transmit data into the SCFTDR2. Select the transmit format in the SCSMR2 and SCFCR2 and reset the TFIFO before setting TE to 1. Receive Enable Enables or disables the SCIF serial receiver. 0: Receiver disabled. Note: Clearing RE to 0 does not affect the receive flags (DR, ER, BRK, FER and PER). These flags retain their previous values. 1: Receiver enabled. Note: Serial reception starts when a start bit is detected. Select the receive format in the SCSMR2 before setting RE to 1. Reserved These bits are always read as 0. The write value should always be 0. Clock Enable These bits select the SCIF clock source and enable or disable clock output from the SCK2 pin. Depending on the combination of CKE1 and CKE0, the SCK2 pin can be used for serial clock output or serial clock input. The CKE0 setting is valid only when the SCI is operating with the internal clock (CKE1 = 0). The CKE0 setting is ignored when an external clock source is selected (CKE1 = 1). Always select the SCIF operating mode in the SCSMR2, before setting CKE1 and CKE0. For further details on selection of the SCIF clock source, see table 16.7 in section 16.4, Operation. 00: Internal clock, SCK pin used for input pin (input signal is ignored) 1 01: Internal clock, SCK2 pin used for clock output* 2 10: External clock, SCK2 pin used for clock input* 2 11: External clock, SCK2 pin used for clock input* Notes: 1. The output clock frequency is 16 times the bit rate. 2. The input clock frequency is 16 times the bit rate. 4 RE 0 R/W 3, 2 -- All 0 R/W 1 0 CKE1 CKE0 0 0 R/W R/W Rev. 4.00, 03/04, page 430 of 660 16.3.7 Serial Status Register 2 (SCSSR2) The serial status register 2 (SCSSR2) is a 16-bit register. The upper 8 bits indicate the number of receive errors in the data of the SCFRDR2, and the lower 8 bits indicate SCIF operating state. The CPU can always read and write the SCSSR2, but cannot write 1 to the status flags (ER, TEND, TDFE, BRK, OPER, and DR). These flags can be cleared to 0 only if they have first been read (after being set to 1). Bits 3 (FER) and 2 (PER) are read-only bits and cannot be written. Bit Bit Name Initial Value All 0 R/W R Description Number of parity errors These bits indicate the number of data items that contain a parity error in the receive data stored in the SCFRDR2. (The number of parity errors in the SCFRDR2) All 0 R Number of framing errors These bits indicate the number of data items that contain a framing error in the receive data stored in the SCFRDR2. (The number of framing errors in the SCFRDR2) 15 to 12 PER3 to PER0 11 to 8 FER3 to FER0 Rev. 4.00, 03/04, page 431 of 660 Bit 7 Bit Name ER Initial Value 0 R/W Description R/(W)* Receive error Indicates that a framing error or a parity error, when receiving data containing parity bits, has occurred. 0: Receive is in progress, or receive is normally 1 completed.* [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2. ER is read as 1, then written to with 0. 1: A framing error or a parity error has occurred during receiving. ER is set to 1 when the stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one-data receive*, or when the total number of 1's in the received data and in the parity bit does not match the even/odd parity specification specified by the O/E bit of the SCSMR. [Setting conditions] 1. The stop bit is 0 after checking whether or not the last stop bit of the received data is 1 at the end of one-data 2 receive.* The total number of 1's in the received data and in the parity bit does not match the even/odd parity specification specified by the O/E bit of the SCSMR2. 2. Notes: 1. Clearing the RE bit to 0 in SCSCR2 does not affect the ER bit, which retains its previous value. Even if a receive error occurs, the received data is transferred to SCFRDR2 and the receive operation is continued. Whether or not the data read from SCRDR2 includes a receive error can be detected by the FER and PER bits of SCSSR2. 2. n the stop mode, only the first stop bit is checked; the second stop bit is not checked. Rev. 4.00, 03/04, page 432 of 660 Bit 6 Bit Name TEND Initial Value 1 R/W Description R/(W)* Transmit End Indicates that when the last bit of a serial character was transmitted, the SCFTDR2 did not contain valid data, so transmission has ended. 0: Transmission is in progress. [Clearing condition] Data is written to SCFTDR2. 1: End of transmission [Setting conditions] 1. When the chip is reset or enters standby mode, TE in the SCSCR2 is cleared to 0. 2. SCFTDR2 contains no transmit data when the last bit of a one-byte serial character is transmitted. Rev. 4.00, 03/04, page 433 of 660 Bit 5 Bit Name TDFE Initial Value 1 R/W Description R/(W)* Transmit FIFO Data Empty Indicates that data is transferred from SCFTDR2 to SCTSR2, the quantity of data in SCFTDR2 becomes less than the number of transmission triggers specified by the TTRG1 and TTRG0 bits in SCFCR2, and writing the transmit data to SCFTDR is enabled. 0: The quantity of transmit data written to SCFTDR2 is equal to or greater than the specified number of transmission triggers. [Clearing condition] When data exceeding the specified number of transmission triggers is written to SCFTDR2, software reads TDFE after it has been set to 1, then writes 0 to TDFE 1: End of transmission [Setting conditions] 1. The chip is power-on reset or enters standby mode. 2. The quantity of transmission data in SCFTDR2 becomes less than the specified number of transmission triggers as a result of transmission. Note: Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be written when TDFE is 1 is "16 minus the specified number of transmission triggers". If attempted to write additional data, the data is ignored. The quantity of data in SCFTDR2 is indicated by the upper 8 bits of SCFTDR2. Rev. 4.00, 03/04, page 434 of 660 Bit 4 Bit Name BRK Initial Value 0 R/W Description R/(W)* Break Detection Indicates that a break signal is detected in received data. 0: No break signal is being received. [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2. BRK is read as 1, then written to with 0. 1: A break signal is received. [Setting conditions] 1. Data including a framing error is received. 2. A framing error with space 0 occurs in the subsequent received data. Note: When a break is detected, transfer of the received data (H'00) to SCFRDR2 stops after detection. When the break ends and the receive signal becomes mark 1, the transfer of the received data resumes. The received data of a frame in which a break signal is detected is transferred to SCFRDR2. After this, however, no received data is transferred until a break ends with the received signal being mark 1 and the next data is received. 3 FER 0 R Framing Error Indicates a framing error in the data read from the SCFRDR2. 0: No framing error occurred in the data read from SCFRDR2. [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2. No framing error is present in the data read from SCFRDR2. 1: A framing error occurred in the data read from SCFRDR2. [Setting condition] A framing error is present in the data read from SCFRDR2 Rev. 4.00, 03/04, page 435 of 660 Bit 2 Bit Name PER Initial Value 0 R/W R Description Parity Error Indicates a parity error in the data read from the SCFRDR2. 0: No parity error occurred in the data read from SCFRDR2. [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2. No parity error is present in the data read from SCFRDR2. 1: A parity error occurred in the data read from SCFRDR2. [Setting condition] A parity error is present in the data read from SCFRDR2 Rev. 4.00, 03/04, page 436 of 660 Bit 1 Bit Name RDF Initial Value 0 R/W Description R/(W)* Receive FIFO Data Full Indicates that received data is transferred to the SCFRDR2, the quantity of data in SCFRDR becomes more than the number of receive triggers specified by the RTRG1 and RTRG0 bits in SCFCR2. 0: The quantity of transmit data written to SCFRDR2 is less than the specified number of receive triggers. [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2. When SCFRDR2 is read until the quantity of receive data in SCFRDR2 becomes less than the specified number of receive triggers, software reads RDF after it has been set to 1, and then writes 0 to RDF. 1: The quantity of receive data in SCFRDR2 is more than the specified number of receive triggers. [Setting condition] The quantity of receive data which is greater than the specified number of receive triggers is being stored to SCFRDR2.* Note: * Since SCFTDR2 is a 16-byte FIFO register, the maximum quantity of data which can be read when RDF is 1 is the specified number of receive triggers. If attempted to read after all data in the SCFRDR2 have been read, the data is undefined. The quantity of receive data in SCFRDR2 is indicated by the lower 8 bits of SCFTDR2. Rev. 4.00, 03/04, page 437 of 660 Bit 0 Bit Name DR Initial Value 0 R/W Description R/(W)* Receive Data Ready Indicates that the SCFRDR2 stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 etu has elapsed from the last stop bit. 0: Receive is in progress, or no received data remains in SCFRDR2 after the receive ended normally. [Clearing conditions] 1. The chip is power-on reset or enters standby mode. 2. DR is read as 1, then written to with 0. 1: Next receive data is not received. [Setting condition] SCFRDR2 stores the data which is less than the specified number of receive triggers, and that next data is not yet received after 15 etu has elapsed from the last stop bit.* Note: * This is equivalent to 1.5 frames with the 8-bit 1-stop-bit format. (etu: Elementary Time Unit) Note: * The only value that can be written is 0 to clear the flag. Rev. 4.00, 03/04, page 438 of 660 16.3.8 Bit Rate Register 2 (SCBRR2) The bit rate register 2 (SCBRR2) is an eight-bit register that, together with the baud rate generator clock source selected by the CKS1 and CKS0 bits in the SCSMR2, determines the serial transmit/receive bit rate. The CPU can always read and write the SCBRR2. The SCBRR2 is initialized to H'FF by a reset or in module standby or standby mode. Each channel has independent baud rate generator control, so different values can be set in two channels. The SCBRR2 setting is calculated as follows: Asynchronous mode: N = B: N: P: n: P 64 x 2 2n - 1 xB x 106 - 1 Bit rate (bit/s) SCBRR2 setting for baud rate generator (0 N 255) Operating frequency for peripheral modules (MHz) Baud rate generator clock source (n = 0, 1, 2, 3) (for the clock sources and values of n, see table 16.2.) Table 16.2 SCSMR2 Settings SCSMR2 Settings n 0 1 2 3 Clock Source P P/4 P/16 P/64 CKS1 0 0 1 1 CKS0 0 1 0 1 Note: Find the bit rate error by the following formula: Error (%) = P x 106 (N+1) x 64 x 22n-1 x B -1 x 100 Rev. 4.00, 03/04, page 439 of 660 Table 16.3 lists examples of SCBRR2 settings. Table 16.3 Bit Rates and SCBRR2 Settings P (MHz) 7.3728 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 1 1 0 0 0 0 0 0 0 N 130 95 191 95 191 95 47 23 11 6 5 Error (%) n % -0.07 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 5.33 0.00 2 2 1 1 0 0 0 0 0 0 0 N 141 103 207 103 207 103 51 25 12 7 6 8 Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -6.99 P (MHz) 10 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 n 2 2 2 1 1 0 0 0 0 0 0 N 177 129 64 129 64 129 64 32 15 9 7 Error (%) n % -0.25 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 1.73 0.00 1.73 1 1 1 0 0 0 0 0 0 0 0 N 212 155 77 155 77 38 19 9 4 2 9 12 Error (%) n % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 -2.34 2 2 2 1 1 0 0 0 0 0 0 N 217 159 79 159 79 159 79 39 19 11 9 12.288 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 2.40 0.00 1 1 0 0 0 0 0 0 0 0 0 N 174 127 255 127 255 127 63 31 15 9 1 9.8304 Error (%) % -0.26 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 -1.70 0.00 Rev. 4.00, 03/04, page 440 of 660 P (MHz) 14.7456 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 115200 500000 n 3 2 2 1 1 0 0 0 0 0 0 0 0 N 64 191 95 191 95 191 95 47 23 14 11 3 0 Error (%) % 0.70 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 2 2 1 1 0 0 0 0 0 0 N 70 207 103 207 103 207 103 51 25 15 12 3 0 16 Error (%) % 0.03 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 0.16 8.51 0.00 n 3 2 2 1 1 0 0 0 0 0 0 0 0 19.6608 N 86 255 127 255 127 255 127 63 31 19 15 4 0 Error (%) % 0.31 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 6.67 22.9 n 3 2 2 1 1 0 0 0 0 0 0 0 N 88 64 129 64 129 64 129 64 32 19 15 4 0 20 Error (%) % -0.25 0.16 0.16 0.16 0.16 0.16 0.16 0.16 -1.36 0.00 1.73 8.51 25.0 -1.70 0 -1.70 0 -7.84 0 P (MHz) 24 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 115200 500000 n 3 3 2 2 1 1 0 0 0 0 0 0 0 N 106 77 155 77 155 77 155 77 38 23 19 6 1 Error (%) % 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.16 0.00 n 24.576 N 108 79 159 79 159 79 159 79 39 24 19 6 1 Error (%) % 0.08 0.00 0.00 0.00 0.00 0.00 0.00 0.00 0.00 n 3 3 2 2 1 1 0 0 0 28.7 N 126 92 186 92 186 92 186 92 46 28 22 7 1 Error (%) % 0.31 0.46 n 3 3 N 132 97 194 97 194 97 194 97 48 29 23 7 1 30 Error (%) % 0.13 -0.35 0.16 -0.35 0.16 -0.35 -1.36 -0.35 -0.35 0.00 1.73 1.73 -6.25 -0.44 3 3 2 2 1 1 0 0 0 0 -0.08 2 0.46 2 -0.08 1 0.46 1 -0.08 0 0.46 0 -0.61 0 -1.03 0 1.55 0 -1.70 0 0.00 0 -2.34 0 -6.99 0 -25.0 0 -4.76 0 -23.2 0 -2.68 0 -10.3 0 Rev. 4.00, 03/04, page 441 of 660 P (MHz) 33.34 Bit Rate (bit/s) 110 150 300 600 1200 2400 4800 9600 19200 31250 38400 11520 500000 0 0 n 3 3 2 2 1 1 0 0 0 0 N 147 108 216 108 216 108 216 108 53 32 26 8 1 Error (%) % 0.00 -0.43 0.03 -0.43 0.03 -0.43 0.03 -0.43 0.49 1.03 0.49 0.49 4.19 Table 16.4 lists the maximum bit rates in the asynchronous mode when the baud rate generator is used. Table 16.5 lists the maximum bit rates when an external clock input is used. Table 16.4 Maximum Bit Rates for Various Frequencies with Baud Rate Generator (Asynchronous Mode) Settings P (MHz) 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 Maximum Bit Rate (bit/s) 250000 307200 375000 460800 500000 614400 625000 750000 768000 896875 937500 n 0 0 0 0 0 0 0 0 0 0 0 N 0 0 0 0 0 0 0 0 0 0 0 Rev. 4.00, 03/04, page 442 of 660 Table 16.5 Maximum Bit Rates during External Clock Input (Asynchronous Mode) P (MHz) 8 9.8304 12 14.7456 16 19.6608 20 24 24.576 28.7 30 External Input Clock (MHz) 2.0000 2.4576 3.0000 3.6864 4.0000 4.9152 5.0000 6.0000 6.1440 7.1750 7.5000 Maximum Bit Rate (bit/s) 125000 153600 187500 230400 250000 307200 312500 375000 384000 448436 468750 16.3.9 FIFO Control Register 2 (SCFCR2) The FIFO control register 2 (SCFCR2) resets the number of data in the SCFTDR2 and SCFRDR2, sets the number of trigger data, and contains an enable bit for the loop back test. The SCFCR2 is always read and written by the CPU. Bit 7 6 Bit Name Initial Value RTRG1 RTRG0 0 0 R/W Description R/W R/W Trigger of the Number of Receive FIFO Data Set the reference number of the receive data full. The RDF in SCSSR2 is set to 1, when the receiving data count has exceeded the following trigger number. Trigger number of receive data. 00: 01: 10: 11: 1 4 8 14 Rev. 4.00, 03/04, page 443 of 660 Bit 5 4 Bit Name TTRG1 TTRG0 Initial Value R/W 0 0 R/W R/W Description Trigger of the Number of Transmit FIFO Data Set the reference number of the send data empty. The TDFE in SCSSR2 is set to 1, when the transmitting data count has fallen the following trigger number. Trigger number of transmit data. 00: 01: 10: 11: 8 (8) 4 (12) 2 (14) 1 (15) Note: Values in brackets mean the number of empty bytes in SCFTDR when the TDFE is set. 3 MCE 0 R/W Modem Control Enable Enables the modem control signals CTS2 and RTS2. 0: Disables the modem signal* 1: Enables the modem signal Note: * The CTS2 is fixed to active 0 regardless of the input value, and the RTS2 is also fixed to 0. 2 TFRST 0 R/W Transmit FIFO Data Register Reset Cancels the transmit data in the SCFTDR2 and resets the data to the empty state. 0: Disables reset operation* 1: Enables reset operation Note: * The reset is executed in a hardware reset or the standby mode. 1 RFRST 0 R/W Receive FIFO Data Register Reset Cancels the receive data in the SCFRDR2 and resets the data to the empty state. 0: Disables reset operation* 1: Enables reset operation Note: * The reset is executed in a hardware reset or the standby mode. 0 LOOP 0 R/W Loop Back Test Internally connects the transmit output pin (TXD2) and receive input pin (RXD2) and enables the loop back test. 0: Disables the loop back test 1: Enables the loop back test Rev. 4.00, 03/04, page 444 of 660 16.3.10 FIFO Data Count Set Register 2 (SCFDR2) The SCFDR2 is a 16-bit register which indicates the number of data stored in the SCFTDR2 and SCFRDR2. The SCFDR2 is always read from the CPU. The upper eight bits of this register indicate the number of transmit data items stored in the SCFTDR2 that have not yet been transmitted. The H'00 means no transmit data, and the H'10 means that the full of transmit data are stored in the SCFTDR2. The lower eight bits of this register indicate the number of receive data items stored in the SCFRDR2. The H'00 means no receive data, and the H'10 means that the full of receive data are stored in the SCFRDR2. Bit 15 to 13 12 to 8 7 to 5 4 to 0 Bit Name -- T4 to T0 -- R4 to R0 Initial Value All 0 All 0 All 0 All 0 R/W Description R R R R Reserved These bits are always read as 0. Number of non-transmitted data. Reserved These bits are always read as 0. Number of received data. 16.3.11 SC Port Control Register (SCPCR) For information about the SC port control register (SCPCR), see section 14.3.8, SC Port Control Register (SCPCR). 16.3.12 SC Port Data Register (SCPDR) For information about the SC port data register (SCPDR), see section 14.3.9, SC Port Data Register (SCPDR). Rev. 4.00, 03/04, page 445 of 660 16.4 Operation For serial communication, the SCIF has an asynchronous mode in which characters are synchronized individually. Refer to section 14.4.1, Operation in Asynchronous Mode (SCI). The SCIF has the 16-byte FIFO buffer for both transmit and receive, reduces an overhead of the CPU, and enables continuous high-speed communication. Moreover, it has the RTS2 and CTS2 signals as the modem control signals. The transmission format is selected in the SCSMR2, as listed in table 16.6. The SCI clock source is selected by the combination of the CKE1 and CKE0 bits in SCSCR2, as listed in table 16.6. * Data length is selectable: seven or eight bits. * Parity and multiprocessor bits are selectable. So is the stop bit length (one or two bits). The combination of the preceding selections constitutes the communication format and character length. * In receiving, it is possible to detect framing errors (FER), parity errors (PER), receive FIFO data full, receive data ready, and breaks. * In transmitting, it is possible to detect transmit FIFO data empty. * The number of stored data for both the transmit and receive FIFO registers is displayed. * An internal or external clock can be selected as the SCIF clock source. When an internal clock is selected, the SCIF operates using the on-chip baud rate generator, and can output a serial clock signal with a frequency 16 times the bit rate. When an external clock is selected, the external clock input must have a frequency 16 times the bit rate. (The on-chip baud rate generator is not used.) Table 16.6 SCSMR2 Settings and SCIF Communication Formats SCSMR2 Settings Mode Asynchronous Bit 6 CHR 0 Bit 5 PE 0 Bit 3 STOP 0 1 1 0 1 1 0 0 1 1 0 1 Set 7-bit Not set Set Data Length 8-bit Parity Bit Not set SCIF Communication Format Stop Bit Length 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits 1 bit 2 bits Rev. 4.00, 03/04, page 446 of 660 Table 16.7 SCSCR2 and SCSCR2 Settings and SCIF Clock Source Selection SCSCR2 Settings Mode Bit 1 CKE1 Bit 0 CKE0 0 1 0 1 External Clock Source Internal SCIF Transmit/Receive Clock SCK2 Pin Function SCIF does not use the SCK2 pin Outputs a clock with a frequency 16 times the bit rate Inputs a clock with frequency 16 times the bit rate Asynchronous 0 mode 1 16.4.1 Serial Operation Transmit/Receive Formats: Table 16.8 lists eight communication formats that can be selected. The format is selected by settings in the SCSMR2. Table 16.8 Serial Communication Formats SCSMR2 Bits CHR 0 0 0 0 1 1 1 1 PE 0 0 1 1 0 0 1 1 STOP 0 1 0 1 0 1 0 1 1 START START START START START START START START Serial Transmit/Receive Format and Frame Length 2 3 4 5 6 7 8 9 10 STOP STOP STOP P P STOP STOP STOP P P STOP STOP STOP STOP STOP STOP 11 12 8-Bit data 8-Bit data 8-Bit data 8-Bit data 7-Bit data 7-Bit data 7-Bit data 7-Bit data START: Start bit STOP: Stop bit P: Parity bit Rev. 4.00, 03/04, page 447 of 660 Clock: An internal clock generated by the on-chip baud rate generator or an external clock input from the SCK2 pin can be selected as the SCIF transmit/receive clock. The clock source is selected by bits CKE1 and CKE0 in the serial control register (SCSCR2) (table 16.7). When an external clock is input at the SCK2 pin, it must have a frequency equal to 16 times the desired bit rate. When the SCIF operates on an internal clock, it can output a clock signal at the SCK2 pin. The frequency of this output clock is 16 times the bit rate. Transmitting and Receiving Data (SCIF Initialization): Before transmitting or receiving, clear the TE and RE bits to 0 in the serial control register (SCSCR2), then initialize the SCIF as follows. When changing the communication format, always clear the TE and RE bits to 0 before following the procedure given below. Clearing TE to 0 initializes the transmit shift register (SCTSR2). Clearing TE and RE to 0, however, does not initialize the serial status register (SCSSR2), transmit FIFO data register (SCFTDR2), or receive FIFO data register (SCFRDR2), which retain their previous contents. Clear TE to 0 after all transmit data are transmitted and the TEND flag in the SCSSR2 is set. The transmitting data enters the high impedance state after clearing to 0 although the bit can be cleared to 0 in transmitting. Set the TFRST bit in the SCFCR2 to 1 and reset the SCFTDR2 before TE is set again to start transmission. When an external clock is used, the clock should not be stopped during initialization or subsequent operation. SCIF operation becomes unreliable if the clock is stopped. Figure 16.5 is a sample flowchart for initializing the SCIF. The procedure for initializing the SCIF is: Rev. 4.00, 03/04, page 448 of 660 Initialization Clear TE and RE bits in SCSCR2 to 0 Set TFRST and RFRST bits in SCFCR2 to 1 Set CKE1 and CKE0 bits in SCSCR2 (leaving TE and RE bits cleared to 0) Set data transfer format in SCSMR2 Set value in SCBRR2 Wait 1-bit interval elapsed? Yes Set RTRG1-0, TTRG1-0, and MCE in SCFCR2 Clear TFRST and RFRST bits to 0 Set TE and RE bits in SCSCR2 to 1,and set RIE, TIE, TEIE, and MPIE bits No 1. Set the clock selection in SCSCR2. Be sure to clear bits RIE TIE, TE, and RE to 0. When clock output is selected, it is output immediately after SCSCR2 settings are made. 2. Set the data transfer format in SCSMR2. 3. Write a value corresponding to the SCBRR2. (Not necessary if an external clock is used.) 4. Wait at least one bit interval, then set the TE bit or RE bit in SCSR2 to 1. Also set the RIE and TIE bits. Setting the TE and RE bits enables the TxD2 and RxD2 pins to be used. When transmitting, the SCIF will go to the mark state; when receiving, it will go to the idle state, waiting for a start bit. End Figure 16.5 Sample SCIF Initialization Flowchart Rev. 4.00, 03/04, page 449 of 660 * Serial data transmission Figure 16.6 shows a sample flowchart for serial transmission. Use the following procedure for serial data transmission after enabling the SCIF for transmission. Start transmission 1. SCIF status check and transmit data write: Read SCSSR2 and check that the TDFE flag is set to 1, then write transmit data to the SCFTDR2, read 1 from the TDFE and TEND flags, then clear these flags to 0. The number of transmit data bytes that can be written is 16 - (transmit trigger set number). 2. Serial transmission continuation procedure: To continue serial transmission, read 1 from the TDFE flag to confirm that writing is possible, then write data to SCFTDR2, and then clear the TDFE flag to 0. 3. Break output at the end of serial transmission: To output a break in serial transmission, set the SCPDR and SCPCR, then clear the TE bit to 0 in the SCSCR2. For information on SCPDR and SCPCR, see 16.3.11, SC Port Control Register (SCPCR), and 16.3.12, SC Port Data Register (SCPDR). In steps 1 and 2, it is possible to ascertain the number of data bytes that can be written from the number of transmit data bytes in SCFTDR2 indicated by the upper 8 bits of the SCFDR2. Read TDFE bit in SCSSR2 TDFE= 1? Yes No Write transmit data (16 - transmit trigger set number) to SCFTDR2, read 1 from TDFE bit and TEND flag in SCSSR2, then clear to 0 All data transmitted? Yes Read TEND bit in SCSSR2 No TEND= 1? Yes Break output? Yes Set SCPDR and SCPCR Clear TE bit in SCSCR2 to 0 No No End of transmission Figure 16.6 Sample Serial Transmission Flowchart Rev. 4.00, 03/04, page 450 of 660 In serial transmission, the SCIF operates as described below. 1. When data is written into the SCFTDR2, the SCIF transfers the data from SCFTDR2 to the transmit shift register (SCTSR2) and starts transmitting. Confirm that the TDFE flag in SCSSR2 is set to 1 before writing transmit data to SCFTDR2. The number of data bytes that can be written is (16 - transmit trigger setting). 2. When data is transferred from SCFTDR2 to SCTSR2 and transmission is started, consecutive transmit operations are performed until there is no transmit data left in SCFTDR2. When the number of transmit data bytes in SCFTDR2 falls below the transmit trigger number set in the SCFCR2, the TDFE flag is set. If the TIE bit in SCSCR2 is set to 1 at this time, a transmitFIFO-data-empty interrupt (TXI) request is generated. The serial transmit data is sent from the TxD2 pin in the following order. A. Start bit: One-bit 0 is output. B. Transmit data: 8-bit or 7-bit data is output in LSB-first order. C. Parity bit: One parity bit (even or odd parity) is output. (A format in which a parity bit is not output can also be selected.) D. Stop bit(s): One- or two-bit 1s (stop bits) are output. E. Mark state: 1 is output continuously until the start bit that starts the next transmission is sent. 3. The SCIF checks the SCFTDR2 transmit data at the timing for sending the stop bit. If data is present, the data is transferred from SCFTDR2 to SCTSR2, the stop bit is sent, and then serial transmission of the next frame is started. If there is no transmit data, the TEND flag in SCSSR2 is set to 1, the stop bit is sent, and then the line goes to the mark state in which 1 is output continuously. Rev. 4.00, 03/04, page 451 of 660 Figure 16.7 shows an example of the operation for transmission. 1 Serial data Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 Start bit 0 D0 D1 Data D7 Parity bit 0/1 Stop bit 1 1 Idling (marking) Data TDFE TEND TXI interrupt request Data written to SCFTDR2 and TDFE flag read as 1 then cleared to 0 by TXI interrupt handler TXI interrupt request One frame Figure 16.7 Example of Transmit Operation (Example with 8-Bit Data, Parity, One Stop Bit) 4. When modem control is enabled, transmission can be stopped and restarted in accordance with the CTS2 input value. When CTS2 is set to 1, if transmission is in progress, the line goes to the mark state after transmission of one frame. When CTS2 is set to 0, the next transmit data is output starting from the start bit. Figure 16.8 shows an example of the operation when modem control is used. Start bit Serial data TXD2 0 D0 D1 D7 Parity bit 0/1 Stop bit Start bit 0 D0 D1 D7 0/1 Rise this point before a stop bit Figure 16.8 Example of Operation Using Modem Control (CTS2 CTS2) CTS2 Rev. 4.00, 03/04, page 452 of 660 * Serial data reception Figure 16.9 shows a sample flowchart for serial reception. Use the following procedure for serial data reception after enabling the SCIF for reception. Start reception Read ORER, PER, FER flags in SCSSR2 Yes 1. Receive error handling and break detection: Read the DR, ER, and BRK flags in SCSSR2 to identify any error, perform the appropriate error handling, then clear the DR, ER, and BRK flags to 0. In the case of a framing error, a break can also be detected by reading the value of the RxD2 pin. 2. SCIF status check and receive data read : Read the SCSSR2 and check that RDF = 1, then read the receive data in SCFRDR2, read 1 from the RDF flag, and then clear the RDF flag to 0. The transition of the RDF flag from 0 to 1 can be identified by an RXI interrupt. 3. Serial reception continuation procedure: To continue serial reception, read at least the receive trigger set number of receive data bytes from SCFRDR2, read 1 from the RDF flag, then clear the RDF flag to 0. The number of receive data bytes in SCFRDR2 can be ascertained by reading the lower bits of SCFDR2. PER = 1 or FER = 1? No Error processing Read RDF flag in SCSSR2 No RDF = 1? Yes Read receive data in SCFRDR2, and clear RDF flag in SCSSR2 to 0 No All data received? Yes Clear RE bit in SCSCR2 to 0 End reception Figure 16.9 Sample Serial Reception Flowchart (1) Rev. 4.00, 03/04, page 453 of 660 Error processing No 1. Whether a framing error or parity error has occurred in the receive data read from SCFRDR2 can be ascertained from the FER and PER bits in SCSSR2. 2. When a break signal is received, receive data is not transferred to SCFRDR2 while the BRK flag is set. However, note that the last data in SCFRDR2 is H'00 and the break data in which a framing error occurred is stored. ER = 1? Yes Receive error processing No BRK= 1? Break processing No DR= 1? Yes Read receive data in SCFRDR2 Clear DR, ER, BRK flags in SCSSR2 to 0 End Figure 16.10 Sample Serial Reception Flowchart (2) In serial reception, the SCIF operates as described below. 1. The SCIF monitors the transmission line, and if a 0 start bit is detected, performs internal synchronization and starts reception. 2. The received data is stored in SCRSR2 in LSB-to-MSB order. 3. The parity bit and stop bit are received. After receiving these bits, the SCIF carries out the following checks. A. Stop bit check: The SCIF checks whether the stop bit is 1. If there are two stop bits, only the first is checked. B. The SCIF checks whether receive data can be transferred from the receive shift register (SCRSR2) to SCFRDR2. C. Break check: The SCIF checks that the BRK flag is 0, indicating that the break state is not set. If all the above checks are passed, the receive data is stored in SCFRDR2. Note: Reception is not suspended when a receive error occurs. Rev. 4.00, 03/04, page 454 of 660 4. If the RIE bit in SCSCR2 is set to 1 when the RDF or DR flag changes to 1, a receive-FIFOdata-full interrupt (RXI) request is generated. If the RIE bit in SCSCR2 is set to 1 when the ER flag changes to 1, a receive-error interrupt (ERI) request is generated. If the RIE bit in SCSCR2 is set to 1 when the BRK flag changes to 1, a break reception interrupt (BRI) request is generated. Figure 16.11 shows an example of the operation for reception. Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 Start bit 0 D0 D1 Parity bit D7 0/1 Stop bit 1 1 Serial data Data Data 1 Idling (marking) RDF RXI interrupt FER request One frame Data read and RDF flag read as 1 then cleared to 0 by RXI interrupt handler ERI interrupt request generated by receive error Figure 16.11 Example of SCIF Receive Operation (Example with 8-Bit Data, Parity, One Stop Bit) 5. When modem control is enabled, the RTS2 signal is output when SCFRDR2 is empty. When RTS2 is 0, reception is possible. When RTS2 is 1, this indicates that SCFRDR2 is full and reception is not possible. Figure 16.12 shows an example of the operation when modem control is used. Start bit Serial data RXD2 0 D0 D1 D2 D7 Parity bit 0/1 1 Start 0 Figure 16.12 Example of Operation Using Modem Control (RTS2 RTS2) RTS2 Rev. 4.00, 03/04, page 455 of 660 16.4.2 SCIF Interrupts The SCIF has four interrupt sources: transmit-FIFO-data-empty (TXI), receive-error (ERI), receive-data-full (RXI), and break (BRI). Table 16.9 shows the interrupt sources and their order of priority. The interrupt sources are enabled or disabled by means of the TIE and RIE bits in SCSCR2. A separate interrupt request is sent to the interrupt controller for each of these interrupt sources. When the TDFE flag in the SCSSR2 is set to 1, a TXI interrupt request is generated. The DMAC can be activated and data transfer performed when this interrupt is generated. The TDFE flag is cleared to 0 when data exceeding the number of transmit triggers is written to SCFTDR2 by the DMAC, the TDFE flag is read as 1, then 0 is written to the TDFE flag. When the RDF flag in SCSSR2 is set to 1, an RXI interrupt request is generated. The DMAC can be activated and data transfer performed when the RDF flag in SCSSR2 is set to 1. The RDF flag is cleared to 0 when SCFRDR2 is read until the quantity of receive data in SCFRDR2 becomes less than the specified number of receive triggers by the DMAC, the RDF flag is read as 1, then 0 is written to the RDF flag. When the ER flag in SCSSR2 is set to 1, an ERI interrupt request is generated. When the BRK flag in SCSSR2 is set to 1, a BRI interrupt request is generated. The TXI interrupt indicates that transmit data can be written, and the RXI interrupt indicates that there is receive data in SCFRDR2. Table 16.9 SCIF Interrupt Sources Interrupt Source ERI RXI BRI TXI Description Interrupt initiated by receive error flag (ER) Interrupt initiated by receive data FIFO full flag (RDF) or data ready flag (DR) Interrupt initiated by break flag (BRK) DMAC Activation Not possible Possible (RDF only) Not possible Low Priority on Reset Release High Interrupt initiated by transmit FIFO data empty flag Possible (TDFE) See section 4, Exception Processing, for priorities and the relationship with non-SCIF interrupts. Rev. 4.00, 03/04, page 456 of 660 16.5 Usage Notes Note the following when using the SCIF. 1. SCFTDR2 Writing and the TDFE Flag The TDFE flag in SCSSR2 is set when the number of transmit data bytes written in the SCFTDR2 has fallen below the transmit trigger number set by bits TTRG1 and TTRG0 in the SCFCR2. After TDFE is set, transmit data up to the number of empty bytes in SCFTDR2 can be written, allowing efficient continuous transmission. If the number of data bytes written in SCFTDR2 is equal to or less than the transmit trigger number, the TDFE flag will be set to 1 again after being cleared to 0. TDFE clearing should therefore be carried out after data more than the specified number of transmit triggers has been written to SCFTDR2. The number of transmit data bytes in SCFTDR2 can be found from the upper 8 bits of the SCFDR2. SCFRDR2 Reading and the RDF Flag The RDF flag in SCSSR2 is set when the number of receive data bytes in the SCFRDR2 has become equal to or greater than the receive trigger number set by bits RTRG1 and RTRG0 in SCFCR2. After RDF is set, receive data equivalent to the trigger number can be read from SCFRDR2, allowing efficient continuous reception. However, if the number of data bytes in SCFRDR2 is greater than the trigger number, the RDF flag will be set to 1 again even if it is cleared to 0. The RDF flag should therefore be cleared to 0 after being read as 1 after all the receive data has been read. The number of receive data bytes in SCFRDR2 can be found from the lower 8 bits of the FIFO data count register (SCFDR2). Break Detection and Processing Break signals can be detected by reading the RxD2 pin directly when a framing error (FER) is detected. In the break state the input from the RxD2 pin consists of all 0s, so the FER flag is set and the parity error flag (PER) may also be set. Note that, although transfer of receive data to SCFRDR2 is halted in the break state, the SCIF receiver continues to operate, so if the BRK flag is cleared to 0 it will be set to 1 again. Sending a Break Signal The I/O condition and level of the TxD2 pin are determined by the SCP2DT bit in SCPDR and bits SCP2MD0 and SCP2MD1 in the SCPCR. This feature can be used to send a break signal. To send a break signal during serial transmission, clear the SCP2DT bit to 0 (designating low level), then set the SCP2MD0 and SCP2MD1 bits to 0 and 1, respectively, and finally clear the TE bit to 0 (halting transmission). When the TE bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, and 0 is output from the TxD2 pin. TEND Flag and TE Bit Processing The TEND flag is set to 1 during transmission of the stop bit of the last data. Consequently, if the TE bit is cleared to 0 immediately after setting of the TEND flag has been confirmed, the stop bit will be in the process of transmission and will not be transmitted normally. Therefore, the TE bit should not be cleared to 0 for at least 0.5 serial clock cycles (or 1.5 cycles if two stop bits are used) after setting of the TEND flag setting is confirmed. Rev. 4.00, 03/04, page 457 of 660 2. 3. 4. 5. 6. Receive Data Sampling Timing and Receive Margin The SCIF operates on a base clock with a frequency of 16 times the transfer rate. In reception, the SCIF synchronizes internally with the fall of the start bit, which it samples on the base clock. Receive data is latched at the rising edge of the eighth base clock pulse. The timing is shown in figure 16.13. 16 clocks 8 clocks 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 6 7 8 9 10111213 1415 0 1 2 3 4 5 Base clock -7.5 clocks Receive data (RxD2) Synchronization sampling timing Data sampling timing Start bit +7.5 clocks D0 D1 Figure 16.13 Receive Data Sampling Timing in Asynchronous Mode The receive margin in asynchronous mode can therefore be expressed as shown in equation 1. Equation 1: M = 0.5 - 1 D - 0.5 (1 + F) x 100% - (L - 0.5) F - 2N N M: Receive margin (%) N: Ratio of clock frequency to bit rate (N = 16) D: Clock duty cycle (D = 0 to 1.0) L: Frame length (L = 9 to 12) F: Absolute deviation of clock frequency From equation 1, if F = 0 and D = 0.5, the receive margin is 46.875%, as given by equation 2. Equation 2: When D = 0.5 and F = 0: M = (0.5 - 1/(2 x 16)) x 100% = 46.875% This is a theoretical value. A reasonable margin to allow in system designs is 20% to 30%. Rev. 4.00, 03/04, page 458 of 660 Section 17 Pin Function Controller (PFC) The pin function controller (PFC) is composed of registers for selecting the function of multiplexed pins and the direction of input/output. The pin function and I/O direction can be selected for each pin individually without regard to the operating mode of the LSI. Table 17.1 lists the multiplexed pins. Table 17.1 List of Multiplexed Pins Port A A A A A A A A B B B B B B B B Port Function (Related Module) PTA7 I/O (port) PTA6 I/O (port) PTA5 I/O (port) PTA4 I/O (port) PTA3 I/O (port) PTA2 I/O (port) PTA1 I/O (port) PTA0 I/O (port) PTB7 I/O (port) PTB6 I/O (port) PTB5 I/O (port) PTB4 I/O (port) PTB3 I/O (port) PTB2 I/O (port) PTB1 I/O (port) PTB0 I/O (port) Other Function (Related Module) D23 I/O (data bus) D22 I/O (data bus) D21 I/O (data bus) D20 I/O (data bus) D19 I/O (data bus) D18 I/O (data bus) D17 I/O (data bus) D16 I/O (data bus) D31 I/O (data bus) D30 I/O (data bus) D29 I/O (data bus) D28 I/O (data bus) D27 I/O (data bus) D26 I/O (data bus) D25 I/O (data bus) D24 I/O (data bus) Rev. 4.00, 03/04, page 459 of 660 Port C C C C C C C C D D D D D D D D E E E E E E E E Port Function (Related Module) PTC7 I/O (port) PTC6 I/O (port) PTC5 I/O (port) PTC4 I/O (port) PTC3 I/O (port) PTC2 I/O (port) PTC1 I/O (port) PTC0 I/O (port) PTD7 I/O (port) PTD6 I/O (port) PTD5 I/O (port) PTD4 I/O (port) PTD3 I/O (port) PTD2 I/O (port) PTD1 I/O (port) PTD0 I/O (port) PTE7 I/O (port) PTE6 I/O (port) PTE5 I/O (port) PTE4 I/O (port) PTE3 I/O (port) PTE2 I/O (port) PTE1 I/O (port) PTE0 I/O (port) Other Function (Related Module) CS6 output (BSC) / CE1B output (BSC) CS5 output 9BSC) / CE1A output (BSC) CS4 output (BSC) CS3 output (BSC) CS2 output (BSC) WE3 output (BSC) / DQMUU output (BSC) / ICIOWR output (BSC) WE2 output (BSC) / DQMUL output (BSC) / ICIORD output (BSC) BS output (BSC) CE2B output (PCMCIA) CE2A output (PCMCIA) IOIS16 input (PCMCIA) CKE output (BSC) CASU output (BSC) CASL output (BSC) RASU output (BSC) RASL output (BSC) IRQOUT output TCLK I/O (Timer) STATUS1 output (CPG) STATUS0 output (CPG) DRAK1 output (DMAC) DRAK0 output (DMAC) DACK1 output (DMAC) DACK0 output (DMAC) Rev. 4.00, 03/04, page 460 of 660 Port F F F F F F F G G G G G G H H H H H H H J J J J Port Function (Related Module) PTF6 I/O (port) PTF5 I/O (port) PTF4 I/O (port) PTF3 I/O (port) PTF2 I/O (port) PTF1 I/O (port) PTF0 I/O (port) PTG5 input (port) PTG4 input (port) PTG3 input (port) PTG2 input (port) PTG1 input (port) PTG0 input (port) PTH6 I/O (port) PTH5 I/O (port) PTH4 I/O (port) PTH3 I/O (port) PTH2 I/O (port) PTH1 I/O (port) PTH0 I/O (port) PTJ3 I/O (port) PTJ2 I/O (port) PTJ1 I/O (port) PTJ0 I/O (port) Other Function (Related Module) ASEBRKAK output (AUD) TDO output (H-UDI) AUDSYNC output (AUD) AUDATA[3] I/O (AUD) AUDATA[2] I/O (AUD) AUDATA[1] I/O (AUD) AUDATA[0] I/O (AUD) ADTRG input (ADC) AUDCK input (AUD) TRST input (AUD)/(H-UDI) TMS input (H-UDI) TCK input (H-UDI) TDI input (H-UDI) DREQ1 input (DMAC) DREQ0 input (DMAC) IRQ4 input (INTC) IRQ3 input (INTC) / IRL3 input (INTC) IRQ2 input (INTC) / IRL2 input (INTC) IRQ1 input (INTC) / IRL1 input (INTC) IRQ0 input (INTC) / IRL0 input (INTC) AN3 input (ADC)/ DA0 output (DAC) AN2 input (ADC)/ DA1 output (DAC) AN1 input (ADC) AN0 input (ADC) Rev. 4.00, 03/04, page 461 of 660 Port SCPT SCPT SCPT SCPT Port Function (Related Module) SCPT5 input (port) SCPT4 I/O (port) SCPT3 I/O (port) SCPT2 input (port) SCPT2 output (port) Other Function (Related Module) CTS2 input (SCIF)/ IRQ5 input (INTC) RTS2 output (SCIF) SCK2 I/O (SCIF) RxD2 input (SCIF) TxD2 output (SCIF) SCK0 I/O (SCI) RxD0 input (SCI) TxD0 output (SCI) SCPT SCPT SCPT1 I/O (port) SCPT0 input (port) SCPT0 output (port) Notes: SCPT0, and SCPT2 have the same data register to be accessed although they have different input pins and output pins. 17.1 Register Description The pin function controller has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port A control register (PACR) * Port B control register (PBCR) * Port C control register (PCCR) * Port D control register (PDCR) * Port E control register (PECR) * Port F control register (PFCR) * Port G control register (PGCR) * Port H control register (PHCR) * Port J control register (PJCR) * SC port control register (SCPCR) Rev. 4.00, 03/04, page 462 of 660 17.1.1 Port A Control Register (PACR) Port A Control Register (PACR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit 15 14 Bit Name Initial Value PA7MD1 PA7MD0 0 0 R/W R/W R/W Description PA7 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 13 12 PA6MD1 PA6MD0 0 0 R/W R/W PA6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 11 10 PA5MD1 PA5MD0 0 0 R/W R/W PA5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 9 8 PA4MD1 PA4MD0 0 0 R/W R/W PA4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PA3MD1 PA3MD0 0 0 R/W R/W PA3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 463 of 660 Bit 5 4 Bit Name Initial Value PA2MD1 PA2MD0 0 0 R/W R/W R/W Description PA2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 3 2 PA1MD1 PA1MD0 0 0 R/W R/W PA1 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PA0MD1 PA0MD0 0 0 R/W R/W PA0 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 17.1.2 Port B Control Register (PBCR) Port B Control Register (PBCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit 15 14 Bit Name Initial Value PB7MD1 PB7MD0 0 0 R/W R/W R/W Description PB7 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 13 12 PB6MD1 PB6MD0 0 0 R/W R/W PB6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 464 of 660 Bit 11 10 Bit Name Initial Value PB5MD1 PB5MD0 0 0 R/W R/W R/W Description PB5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 9 8 PB4MD1 PB4MD0 0 0 R/W R/W PB4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PB3MD1 PB3MD0 0 0 R/W R/W PB3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 5 4 PB2MD1 PB2MD0 0 0 R/W R/W PB2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 3 2 PB1MD1 PB1MD0 0 0 R/W R/W PB1 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PB0MD1 PB0MD0 0 0 R/W R/W PB0 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 465 of 660 17.1.3 Port C Control Register (PCCR) Port C Control Register (PCCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit 15 14 Bit Name Initial Value PC7MD1 PC7MD0 0 0 R/W R/W R/W Description PC7 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 13 12 PC6MD1 PC6MD0 0 0 R/W R/W PC6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 11 10 PC5MD1 PC5MD0 0 0 R/W R/W PC5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 9 8 PC4MD1 PC4MD0 0 0 R/W R/W PC4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PC3MD1 PC3MD0 0 0 R/W R/W PC3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 5 4 PC2MD1 PC2MD0 0 0 R/W R/W PC2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 466 of 660 Bit 3 2 Bit Name Initial Value PC1MD1 PC1MD0 0 0 R/W R/W R/W Description PC1 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PC0MD1 PC0MD0 0 0 R/W R/W PC0 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 17.1.4 Port D Control Register (PDCR) Port D Control Register (PDCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit 15 14 Bit Name PD7MD1 PD7MD0 Initial Value 0 0 R/W R/W R/W Description PD7 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 13 12 PD6MD1 PD6MD0 0 0 R/W R/W PD6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 11 10 PD5MD1 PD5MD0 0 0 R/W R/W PD5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 467 of 660 Bit 9 8 Bit Name PD4MD1 PD4MD0 Initial Value 0 0 R/W R/W R/W Description PD4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PD3MD1 PD3MD0 0 0 R/W R/W PD3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 5 4 PD2MD1 PD2MD0 0 0 R/W R/W PD2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 3 2 PD1MD1 PD1MD0 0 0 R/W R/W PD1 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PD0MD1 PD0MD0 0 0 R/W R/W PD0 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 468 of 660 17.1.5 Port E Control Register (PECR) Port E Control Register (PECR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit 15 14 Bit Name PE7MD1 PE7MD0 Initial Value 0 0 R/W R/W R/W Description PE7 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 13 12 PE6MD1 PE6MD0 0 0 R/W R/W PE6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 11 10 PE5MD1 PE5MD0 0 0 R/W R/W PE5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 9 8 PE4MD1 PE4MD0 0 0 R/W R/W PE4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PE3MD1 PE3MD0 0 0 R/W R/W PE3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 5 4 PE2MD1 PE2MD0 0 0 R/W R/W PE2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 469 of 660 Bit 3 2 Bit Name PE1MD1 PE1MD0 Initial Value 0 0 R/W R/W R/W Description PE1 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PE0MD1 PE0MD0 0 0 R/W R/W PE0 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 17.1.6 Port F Control Register (PFCR) Port F Control Register (PFCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. PFCR is initialized to H'AAAA (in case of ASEMD0 = 1) or H'0000 (in case of ASEMD0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bit 15 Bit Name -- Initial Value 1/0 R/W R Description Reserved When ASEMD0 = 0, this bit is always read as 0 and must only be written with 0. When ASEMD0 = 1, this bit is always read as 1 and must only be written with 1. 14 -- 0 R Reserved This bit is always read as 0 and must only be written with 0. 13 12 PF6MD1 PF6MD0 1/0 0 R/W R/W PF6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 11 10 PF5MD1 PF5MD0 1/0 0 R/W R/W PF5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 470 of 660 Bit 9 8 Bit Name PF4MD1 PF4MD0 Initial Value 1/0 0 R/W R/W R/W Description PF4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PF3MD1 PF3MD0 1/0 0 R/W R/W PF3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 5 4 PF2MD1 PF2MD0 1/0 0 R/W R/W PF2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 3 2 PF1MD1 PF1MD0 1/0 0 R/W R/W PF1 Mode 1 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PF0MD1 PF0MD0 1/0 0 R/W R/W PF0 Mode 1 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 471 of 660 17.1.7 Port G Control Register (PGCR) Port G Control Register (PGCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. PGCR is initialized to H'AAAA (in case of ASEMD0 = 1) or H'A800 (in case of ASEMD0 = 0) by power-on resets; however, it is not initialized by manual resets, in standby mode, or in sleep mode. Bit 15, 13 Bit Name -- Initial Value All 1 R/W R Description Reserved These bits are always read as 1. The write value should always be 0. 14, 12 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. 11 10 PG5MD1 PG5MD0 1 0 R/W R/W PG5 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 9 8 PG4MD1 PG4MD0 1/0 0 R/W R/W PG4 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PG3MD1 PG3MD0 1/0 0 R/W R/W PG3 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 5 4 PG2MD1 PG2MD0 1/0 0 R/W R/W PG2 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 3 2 PG1MD1 PG1MD0 1/0 0 R/W R/W PG1 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 472 of 660 Bit 1 0 Bit Name PG0MD1 PG0MD0 Initial Value 1/0 0 R/W R/W R/W Description PG0 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Note: The bit number are out of sequence. 17.1.8 Port H Control Register (PHCR) Port H Control Register (PHCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. Bit 15, 14 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 13 12 PH6MD1 PH6MD0 0 0 R/W R/W PH6 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 11 10 PH5MD1 PH5MD0 0 0 R/W R/W PH5 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 9 8 PH4MD1 PH4MD0 0 0 R/W R/W PH4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 PH3MD1 PH3MD0 0 0 R/W R/W PH3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 473 of 660 Bit 5 4 Bit Name PH2MD1 PH2MD0 Initial Value 0 0 R/W R/W R/W Description PH2 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 3 2 PH1MD1 PH1MD0 0 0 R/W R/W PH1 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 PH0MD1 PH0MD0 0 0 R/W R/W PH0 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 474 of 660 17.1.9 Port J Control Register (PJCR) Port J Control Register (PJCR) is a 16-bit read/write register that selects the pin functions. When D/A output is enabled, port input settings should not be made in PJCR. When selecting port input, confirm that D/A output is disabled in DACR before making port input settings in PJCR. Bit 15 to 8 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 7 6 PJ3MD1 PJ3MD0 0 0 R/W R/W PJ3 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input 11: Port input 5 4 PJ2MD1 PJ2MD0 0 0 R/W R/W PJ2 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input 11: Port input 3 2 PJ1MD1 PJ1MD0 0 0 R/W R/W PJ1 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input 11: Port input 1 0 PJ0MD1 PJ0MD0 0 0 R/W R/W PJ0 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input 11: Port input Rev. 4.00, 03/04, page 475 of 660 17.1.10 SC Port Control Register (SCPCR) SC Port Control Register (SCPCR) is a 16-bit read/write register that selects the pin functions and the input pull-up MOS control. The setting of SCPCR is valid only when the transmit/receive operation is disabled in the setting of the SCSCR register. When the TE bit in SCSCR is set to 1, the other function output state has a higher priority than the SCPCR setting of the TxD2 or TxD0 pin. When the RE bit in SCSCR is set to 1, the input state has a higher priority than the SCPCR setting of the RxD2 or RxD0 pin. Bit 15 to 12 Bit Name -- Initial Value All 0 R/W R Description Reserved These bits are always read as 0. The write value should always be 0. 11 10 SCP5MD1 SCP5MD0 1 0 R/W R/W SCP5 Mode 00: Other function (See table 17.1) 01: Reserved (Setting prohibited) 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 9 8 SCP4MD1 SCP4MD0 1 0 R/W R/W SCP4 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 7 6 SCP3MD1 SCP3MD0 1 0 R/W R/W SCP3 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) Rev. 4.00, 03/04, page 476 of 660 Bit 5 4 Bit Name SCP2MD1 SCP2MD0 Initial Value 0 0 R/W R/W R/W Description SCP2 Mode 00: Transmit data output 1 (TxD2) Receive data input 1 (RxD2) 01: General output (SCPT[2] output pin) Receive data input 1 (RxD2) 10: SCPT[2] input pin pull-up (input pin) Transmit data output 1 (TxD2) 11: General input (SCPT[2] input pin) Transmit data output 1 (TxD2) Note: There is no combination of simultaneous I/O of SCPT[2] because one bit (SCP2DT) is accessed using two pins of TxD2 and RxD2. When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD1 pin is in the output state. When the TE bit is cleared to 0, the TxD2 pin is in the high-impedance state. 3 2 SCP1MD1 SCP1MD0 1 0 R/W R/W SCP1 Mode 00: Other function (See table 17.1) 01: Port output 10: Port input (Pull-up MOS: on) 11: Port input (Pull-up MOS: off) 1 0 SCP0MD1 SCP0MD0 0 0 R/W R/W SCP0 Mode 00: Transmit data output 0 (TxD0) Receive data input 0 (RxD0) 01: General output (SCPT[0] output pin) Receive data input 0 (RxD0) 10: SCPT[0] input pin pull-up (input pin) Transmit data output 0 (TxD0) 11: General input (SCPT[0] input pin) Transmit data output 0 (TxD0) Note: There is no combination of simultaneous I/O of SCPT[0] because one bit (SCP0DT) is accessed using two pins of TxD0 and RxD0. When the port input is set (bit SCPnMD1 is set to 1) and when the TE bit in SCSCR is set to 1, the TxD0 pin is in the output state. When the TE bit is cleared to 0, the TxD0 pin is in the high-impedance state. Rev. 4.00, 03/04, page 477 of 660 Rev. 4.00, 03/04, page 478 of 660 Section 18 I/O Ports This LSI has 10 ports (ports A to J and SC). All port pins are multiplexed with other pin functions (Pin Function Controller (PFC) maintains the selection of the pin functions and pull-up MOS control). Each port has a data register which stores the data to the pins. 18.1 Port A Port A is an 8-bit I/O port with the pin configuration shown in figure 18.1. Each pin has an input pull-up MOS, which is controlled by Port A Control Register (PACR) in PFC. PTA7 (I/O) / D23 (I/O) PTA6 (I/O) / D22 (I/O) PTA5 (I/O) / D21 (I/O) Port A PTA4 (I/O) / D20 (I/O) PTA3 (I/O) / D19 (I/O) PTA2 (I/O) / D18 (I/O) PTA1 (I/O) / D17 (I/O) PTA0 (I/O) / D16 (I/O) Figure 18.1 Port A 18.1.1 Register Description Port A has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port A data register (PADR) 18.1.2 Port A Data Register (PADR) Port A data Register (PADR) is an 8-bit read/write register that stores data for pins PTA7 to PTA0. PA7DT to PA0DT bit corresponds to PTA7 to PTA0 pin. When the pin function is general output port, if the port is read the value of the corresponding PADR bit is returned directly. When the function is general input port, if the port is read the corresponding pin level is read. Rev. 4.00, 03/04, page 479 of 660 Bit 7 6 5 4 3 2 1 0 Bit Name PA7DT PA6DT PA5DT PA4DT PA3DT PA2DT PA1DT PA0DT Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Table 18.1 shows the function of PADR. Table 18.1 Read/Write Operation of the Port A Data Register (PADR) PAnMD1 PAnMD0 Pin State 0 0 1 1 0 1 Read Write Value is written to PADR, but does not affect pin state. Write value is output from pin. Value is written to PADR, but does not affect pin state. Value is written to PADR, but does not affect pin state. (n = 0 to 7) Other function PADR value Output Input (Pull-up MOS on) Input (Pull-up MOS off) PADR value Pin state Pin state 18.2 Port B Port B is an 8-bit I/O port with the pin configuration shown in figure 18.2. Each pin has an input pull-up MOS, which is controlled by Port B Control Register (PBCR) in PFC. PTB7 (I/O) / D31 (I/O) PTB6 (I/O) / D30 (I/O) PTB5 (I/O) / D29 (I/O) Port B PTB4 (I/O) / D28 (I/O) PTB3 (I/O) / D27 (I/O) PTB2 (I/O) / D26 (I/O) PTB1 (I/O) / D25 (I/O) PTB0 (I/O) / D24 (I/O) Figure 18.2 Port B Rev. 4.00, 03/04, page 480 of 660 18.2.1 Register Description Port B has the following register. Refer to section 23, List of Registers, for more details of the addresses and access size. * Port B data register (PBDR) 18.2.2 Port B Data Register (PBDR) Port B data register (PBDR) is an 8-bit read/write register that stores data for pins PTB7 to PTB0. PB7DT to PB0DT bit corresponds to PTB7 to PTB0 pin. When the pin function is general output port, if the port is read the value of the corresponding PBDR bit is returned directly. When the function is general input port, if the port is read the corresponding pin level is read. Bit 7 6 5 4 3 2 1 0 Bit Name PB7DT PB6DT PB5DT PB4DT PB3DT PB2DT PB1DT PB0DT Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Table 18.2 shows the function of PBDR. Table 18.2 Read/Write Operation of the Port B Data Register (PBDR) Read Write Value is written to PBDR, but does not affect pin state. Write value is output from pin. Value is written to PBDR, but does not affect pin state. Value is written to PBDR, but does not affect pin state. (n = 0 to 7) PBnMD1 PBnMD0 Pin State 0 0 1 1 0 1 Other function PBDR value Output Input (Pull-up MOS on) Input (Pull-up MOS off) PBDR value Pin state Pin state Rev. 4.00, 03/04, page 481 of 660 18.3 Port C Port C is an 8-bit I/O port with the pin configuration shown in figure 18.3. Each pin has an input pull-up MOS, which is controlled by Port C Control Register (PCCR) in PFC. PTC7 (I/O) / PTC6 (I/O) / PTC5 (I/O) / Port C PTC4 (I/O) / PTC3 (I/O) / PTC2 (I/O) / PTC1 (I/O) / PTC0 (I/O) / (output) / (output) / (output) (output) (output) (output) / (output) / (output) (output) (output) (output) / (output) / (output) (output) Figure 18.3 Port C 18.3.1 Register Description Port C has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port C data register (PCDR) 18.3.2 Port C Data Register (PCDR) Port C data register (PCDR) is an 8-bit read/write register that stores data for pins PTC7 to PTC0. PC7DT to PC0DT bit corresponds to PTC7 to PTC0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PCDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Table 18.3 shows the function of PCDR. PCDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and sleep mode, and in a manual reset. Rev. 4.00, 03/04, page 482 of 660 Bit 7 6 5 4 3 2 1 0 Bit Name PC7DT PC6DT PC5DT PC4DT PC3DT PC2DT PC1DT PC0DT Initial Value 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W Description Table 18.3 shows the function of PCDR. Table 18.3 Read/Write Operation of the Port C Data Register (PCDR) PCnMD1 PCnMD0 Pin State 0 0 1 1 0 1 Read Write Value is written to PCDR, but does not affect pin state. Write value is output from pin. Value is written to PCDR, but does not affect pin state. Value is written to PCDR, but does not affect pin state. (n = 0 to 7) Other function PCDR value Output Input (Pull-up MOS: on) Input (Pull-up MOS: off) PCDR value Pin state Pin state 18.4 Port D Port D is an 8-bit I/O port with the pin configuration shown in figure 18.4. Each pin has an input pull-up MOS, which is controlled by Port D Control Register (PDCR) in PFC. PTD7 (I/O) / PTD6 (I/O) / PTD5 (I/O) / Port D (output) (output) (input) PTD4 (I/O) / CKE (output) PTD3 (I/O) / PTD2 (I/O) / PTD1 (I/O) / PTD0 (I/O) / (output) (output) (output) (output) Figure 18.4 Port D Rev. 4.00, 03/04, page 483 of 660 18.4.1 Register Description Port D has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port D data register (PDDR) 18.4.2 Port D Data Register (PDDR) Port D data register (PDDR) is an 8-bit read/write register that stores data for pins PTD7 to PTD0. PD7DT to PD0DT bit corresponds to PTD7 to PTD0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PDDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. PDDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and sleep mode, and in a manual reset. Bit 7 6 5 4 3 2 1 0 Bit Name PD7DT PD6DT PD5DT PD4DT PD3DT PD2DT PD1DT PD0DT Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Table 18.4 shows the function of PDDR. Table 18.4 Read/Write Operation of the Port D Data Register (PDDR) Read Write Value is written to PDDR, but does not affect pin state. Write value is output from pin. Value is written to PDDR, but does not affect pin state. Value is written to PDDR, but does not affect pin state. (n = 0 to 7) PDnMD1 PDnMD0 Pin State 0 0 1 1 0 1 Other function PDDR value Output Input (Pull-up MOS: on) Input (Pull-up MOS: off) PDDR value Pin state Pin state Rev. 4.00, 03/04, page 484 of 660 18.5 Port E Port E is an 8-bit I/O port with the pin configuration shown in figure 18.5. Each pin has an input pull-up MOS, which is controlled by Port E Control Register (PECR) in PFC. PTE7 (I/O) / (output) PTE6 (I/O) / TCLK (I/O) PTE5 (I/O) / STATUS1 (output) Port E PTE4 (I/O) / STATUS0 (output) PTE3 (I/O) / DRAK1 (output) PTE2 (I/O) / DRAK0 (output) PTE1 (I/O) / PTE0 (I/O) / (output) (output) Figure 18.5 Port E 18.5.1 Register Description Port E has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port E data register (PEDR) 18.5.2 Port E Data Register (PEDR) Port E data register (PEDR) is an 8-bit read/write register that stores data for pins PTE7 to PTE0. PE7DT to PE0DT bit corresponds to PTE7 to PTE0 pin. When the pin function is general output port, if the port is read the value of the corresponding PEDR bit is returned directly. When the function is general input port, if the port is read the corresponding pin level is read. PEDR is initialized to H'00 by a power-on reset, after which the general input port function (pullup MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains its previous value in standby mode and sleep mode, and in a manual reset. Rev. 4.00, 03/04, page 485 of 660 Bit 7 6 5 4 3 2 1 0 Bit Name PE7DT PE6DT PE5DT PE4DT PE3DT PE2DT PE1DT PE0DT Initial Value R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Description Table 18.5 shows the function of PEDR. Table 18.5 Read/Write Operation of the Port E Data Register (PEDR) PEnMD1 PEnMD0 Pin State 0 0 1 1 0 1 Read Write Value is written to PEDR, but does not affect pin state. Write value is output from pin. Value is written to PEDR, but does not affect pin state. Value is written to PEDR, but does not affect pin state. (n = 0 to 7) Other function PEDR value Output Input (Pull-up MOS: on) Input (Pull-up MOS: off) PEDR value Pin state Pin state 18.6 Port F Port F is a 7-bit input/output port with the pin configuration shown in figure 18.6. Each pin has an input pull-up MOS, which is controlled by Port F Control Register (PFCR) in PFC. PTF6 (I/O) / (output) PTF5 (I/O) / TDO (output) PTF4 (I/O) / AUDSYNC (output) Port F PTF3 (I/O) / AUDATA3 (I/O) PTF2 (I/O) / AUDATA2 (I/O) PTF1 (I/O) / AUDATA1 (I/O) PTF0 (I/O) / AUDATA0 (I/O) Figure 18.6 Port F Rev. 4.00, 03/04, page 486 of 660 18.6.1 Register Description Port F has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port F data register (PFDR) 18.6.2 Port F Data Register (PFDR) Port F data register (PFDR) is an 8-bit register composed of a 1-bit readable register and a 7-bit readable/writable register. This register stores data for pins PTF6 to PTF0. PF6DT to PF0DT bit corresponds to PTF6 to PTF0 pin. When the function is general input port, if the port is read the corresponding pin level is read. PFDR is initialized by a power-on reset, after which the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains its previous value in standby mode and sleep mode, and in a manual reset. Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W PF6DT PF5DT PF4DT PF3DT PF2DT PF1DT PF0DT 0 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W Description Reserved Table 18.6 shows the function of PFDR. Table 18.6 Read/Write Operation of the Port F Data Register (PFDR) PFnMD1 PFnMD0 Pin State 0 0 1 1 0 1 Read Write Can be written to PFDR but does not affect the pin state. A value to be written is output from the pin. Can be written to PFDR but does not affect the pin state. Can be written to PFDR but does not affect the pin state. (n = 0 to 6) Other functions PFDR value Output Input (Pull-up MOS: on) Input (Pull-up MOS: off) PFDR value Pin state Pin state Rev. 4.00, 03/04, page 487 of 660 18.7 Port G Port G is a 6-bit input port with the pin configuration shown in figure 18.7. Each pin has an input pull-up MOS, which is controlled by Port G Control Register (PGCR) in PFC. PTG5 (input) / (input) PTG4 (input) / AUDCK (input) Port G PTG3 (input) / (input) PTG2 (input) / TMS (input) PTG1 (input) / TCK (input) PTG0 (input) / TDI (input) Figure 18.7 Port G 18.7.1 Register Description Port G has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port G data register (PGDR) 18.7.2 Port G Data Register (PGDR) Port G data register (PGDR) is an 8-bit read register that stores data for pins PTG5 to PTG0. PG5DT to PG0DT bit corresponds to PTG5 to PTG0 pin. When the function is general input port, if the port is read the corresponding pin level is read. PGDR is initialized by a power-on reset, after which the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read. It retains its previous value in standby mode and sleep mode, and in a manual reset. Rev. 4.00, 03/04, page 488 of 660 Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W PG5DT PG4DT PG3DT PG2DT PG1DT PG0DT * * * * * * * * R R R R R R R R Description Reserved Table 18.7 shows the function of PGDR. Note: * Undefined Table 18.7 Read/Write Operation of the Port G Data Register (PGDR) PGnMD1 PGnMD0 Pin State 0 0 1 1 0 1 Read Pin state Pin state Write Ignored (no affect on pin state) Ignored (no affect on pin state) Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 0 to 5) Other function Low level Reserved Input (Pull-up MOS: on) Input (Pull-up MOS: off) 18.8 Port H Port H is a 7-bit I/O and port with the pin configuration shown in figure 18.8. Each pin has an input pull-up MOS, which is controlled by Port H Control Register (PHCR) in PFC. PTH6 (I/O) / PTH5 (I/O) / Port H (input) (input) (input) (input) (input) (input) PTH4 (I/O) / IRQ4 (input) PTH3 (I/O) / IRQ3 (input) / PTH2 (I/O) / IRQ2 (input) / PTH1 (I/O) / IRQ1 (input) / PTH0 (I/O) / IRQ0 (input) / Figure 18.8 Port H Rev. 4.00, 03/04, page 489 of 660 18.8.1 Register Description Port H has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port H data register (PHDR) 18.8.2 Port H Data Register (PHDR) Port H data register (PHDR) is a 7-bit read/write and 1-bit read register that stores data for pins PTH6 to PTH0. PH6DT to PH0DT bit corresponds to PTH6 to PTH0 pin. When the pin function is general output port, if the port is read, the value of the corresponding PHDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. PHDR is initialized to H'00 by a power-on reset. It retains its previous value in standby mode and sleep mode, and in a manual reset. Note that the low level is read if bits 6 to 0 are read except in general-purpose input. Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W PH6DT PH5DT PH4DT PH3DT PH2DT PH1DT PH0DT * 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W Description Reserved Table 18.8 shows the function of PHDR. Note: * Undefined Rev. 4.00, 03/04, page 490 of 660 Table 18.8 Read/Write Operation of the Port H Data Register (PHDR) PHnMD1 PHnMD0 Pin State 0 0 1 1 0 1 Read Write Value is written to PHDR, but does not affect pin state. Write value is output from pin. Value is written to PHDR, but does not affect pin state. Value is written to PHDR, but does not affect pin state. (n = 0 to 6) Other function PHDR value Output Input (Pull-up MOS: on) Input (Pull-up MOS: off) PHDR value Pin state Pin state 18.9 Port J Port J is a 4-bit input port with the pin configuration shown in figure 18.9. PTJ3 (input) / AN3 (input) / DA0 (output) Port J PTJ2 (input) / AN2 (input) / DA1 (output) PTJ1 (input) / AN1 (input) PTJ0 (input) / AN0 (input) Figure 18.9 Port J 18.9.1 Register Description Port J has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Port J data register (PJDR) Rev. 4.00, 03/04, page 491 of 660 18.9.2 Port J Data Register (PJDR) Port J data register (PJDR) is an 8-bit read register that stores data for pins PTJ7 to PTJ0. PJ3DT to PJ0DT bit corresponds to PTJ3 to PTJ0 pin. When the pin function is general output port, if the port is read the value of the corresponding PJDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W PJ3DT PJ2DT PJ1DT PJ0DT 0 0 0 0 0 0 0 0 R R R R R R R R Table 18.9 shows the function of PJDR. Description Reserved Table 18.9 Read/Write Operation of the Port J Data Register (PJDR) PJnMD1 0 PJnMD0 0 1 Pin State Read Write Ignored (no affect on pin state) Ignored (no affect on pin state) Other function Low level Reserved (Setting prohibited) Input Input 1 0 1 Pin state Pin state Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 0 to 3) Rev. 4.00, 03/04, page 492 of 660 18.10 SC Port SC port is a 3-bit I/O, 2-bit output and 4-bit input port with the pin configuration shown in figure 18.10. Each pin has an input pull-up MOS, which is controlled by SC port Control Register (SCPCR) in PFC. SCPT5 (input) / SCPT4 (I/O) / (input) / IRQ5 (input) (output) SCPT3 (I/O) / SCK2 (I/O) SC Port SCPT2 (input) / RxD2 (input) SCPT2 (output) / TxD2 (output) SCPT1 (I/O) / SCK0 (I/O) SCPT0 (input) / RxD0 (input) SCPT0 (output) / TxD0 (output) Figure 18.10 SC Port 18.10.1 Register Description Port SC has the following register. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * SC Port data register (SCPDR) 18.10.2 SC Port Data Register (SCPDR) SC Port data register (SCPDR) is a 5-bit read/write and 3-bit read register that stores data for pins SCPT5 to SCPT0. SCP5DT to SCP0DT bit corresponds to SCPT5 to SCPT0 pin. When the pin function is general output port, if the port is read, the value of the corresponding SCPDR bit is returned directly. When the function is general input port, if the port is read, the corresponding pin level is read. SCPDR is initialized to B'***00000 by a power-on reset. After initialization, the general input port function (pull-up MOS on) is set as the initial pin function, and the corresponding pin levels are read from bits SCP5DT to SCP3DT and SCP1DT. SCPDR retains its previous value in standby mode and sleep mode, and in a manual reset. Note that the low level is read if bit 7 is read except in general-purpose input. When reading the state of the RxD2 and RxD0 pins of the SCP2DT and SCP0DT bits in SCPDR without clearing the TE or RE bit in SCSCR to 0, set the RE bit in SCSCR to 1. When the RE bit is set to 1, the RxD pin is for input and the pin state can be read before the setting of SCPCR. Rev. 4.00, 03/04, page 493 of 660 Bit 7 6 5 4 3 2 1 0 Bit Name Initial Value R/W SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT * * * 0 0 0 0 0 R R R R/W R/W R/W R/W R/W Description Reserved Table 18.10 shows the function of SCPDR Note: * Undefined Table 18.10 Read/Write Operation of the SC Port Data Register (SCPDR) * For SCP4DT to SCP0DT SCPnMD1 SCPnMD0 Pin State 0 0 1 1 0 1 Other function Output Input (Pull-up MOS: on) Input (Pull-up MOS: off) Read SCPDR value SCPDR value Pin state Pin state Write Value is written to SCPDR, but does not affect pin state. Write value is output from pin. Value is written to SCPDR, but does not affect pin state. Value is written to SCPDR, but does not affect pin state. (n = 0 to 4) * For SCP5DT SCPnMD1 SCPnMD0 Pin State 0 0 1 Other function Reserved (Setting prohibited) Input (Pull-up MOS: on) Input (Pull-up MOS: off) Read Low level Write Ignored (no affect on pin state) Ignored (no affect on pin state) 1 0 1 Pin state Pin state Ignored (no affect on pin state) Ignored (no affect on pin state) (n = 5) Rev. 4.00, 03/04, page 494 of 660 Section 19 A/D Converter (ADC) This LSI includes a 10-bit successive-approximation A/D converter with a selection of up to four analog input channels. Figure 19.1 shows the block diagram of the A/D converter. 19.1 Features A/D converter features are listed below. * 10-bit resolution * 4 input channels * High-speed conversion Conversion time: minimum 15 s per channel (with P = 33-MHz peripheral clock) * Three conversion modes Single mode: A/D conversion of one channel Multi mode: A/D conversion on one to four channels Scan mode: Continuous A/D conversion on one to four channels * Four 16-bit data registers A/D conversion results are transferred for storage into data registers corresponding to the channels. * Sample-and-hold function * A/D conversion can be externally triggered * A/D interrupt requested at the end of conversion At the end of A/D conversion, an A/D end interrupt (ADI) can be requested. Rev. 4.00, 03/04, page 495 of 660 Peripheral data bus AVCC 10-bit D/A Successive approximation register ADDRC ADDRD ADDRA ADDRB ADCSR AVSS AN0 AN1 AN2 AN3 Analog multiplexer Sample-andhold circuit + /4 - Control circuit Comparator /8 ADCR Bus interface Internal data bus ADI interrupt signal A/D converter Legend: ADCR: A/D control register ADCSR: A/D control/status register ADDRA: A/D data register A ADDRB: A/D data register B ADDRC: A/D data register C ADDRD: A/D data register D Figure 19.1 A/D Converter Block Diagram Rev. 4.00, 03/04, page 496 of 660 19.2 Input/Output Pin Table 19.1 summarizes the A/D converter's input pins. AVCC and AVSS are the power supply for the analog circuits in the A/D converter. AVcc also functions as the A/D converter reference voltage. Table 19.1 A/D Converter Pins Pin Name Analog power-supply pin Analog ground pin Analog input pin 0 Analog input pin 1 Analog input pin 2 Analog input pin 3 A/D external trigger input pin Abbreviation AVcc AVss AN0 AN1 AN2 AN3 ADTRG I/O Input Input Input Input Input Input Input External trigger input for starting A/D conversion Function Analog power supply Analog ground and reference voltage Group 0 analog inputs 19.3 Register Description The A/D converter has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * A/D data register A (ADDRA) The upper and lower bytes of ADDRA may be represented by ADDRAH and ADDRAL, respectively. * A/D data register B(ADDRB) The upper and lower bytes of ADDRB may be represented by ADDRBH and ADDRBL, respectively. * A/D data register C (ADDRC) The upper and lower bytes of ADDRC may be represented by ADDRCH and ADDRCL, respectively. * A/D data register D (ADDRD) The upper and lower bytes of ADDRD may be represented by ADDRDH and ADDRDL, respectively. * A/D control/status register (ADCSR) * A/D control register (ADCR) Rev. 4.00, 03/04, page 497 of 660 19.3.1 A/D Data Registers A to D (ADDRA to ADDRD) The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the results of A/D conversion. An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper byte (bits 15 to 8) of the A/D data register. The lower 2 bits are stored in the lower byte (bits 7 and 6). Bits 5 to 0 of an A/D data register are reserved bits that always read 0. For the reading of the data, see section 19.4, Bus Master Interface, and section 19.9.3, Access Size and Read Data. Table 19.2 indicates the pairings of analog input channels and A/D data registers. Bit 15 to 6 5 to 0 Bit Name Initial Value R/W R R Description Bit data (10 bits) Reserved These bits are always read as 0. AD9 to AD0 All 0 All 0 Table 19.2 Analog Input Channels and A/D Data Registers Analog Input Channel Group 0 AN0 AN1 AN2 AN3 A/D Data Register ADDRA ADDRB ADDRC ADDRD Rev. 4.00, 03/04, page 498 of 660 19.3.2 A/D Control/Status Register (ADCSR) ADCSR is an 8-bit read/write register that selects the mode and controls the A/D converter. Bit 7 Bit Name ADF Initial Value R/W 0 R/(W)* 1 Description A/D End Flag Indicates the end of A/D conversion. 0: [Clearing conditions] 1. Cleared by reading ADF while ADF = 1, then writing 0 in ADF 2. Cleared when DMAC is activated by ADI interrupt and ADDR is read 1: [Setting conditions] 1. Single mode: A/D conversion ends 2. Multi mode: A/D conversion ends in all selected channels 3. Scan mode: A/D conversion ends in all selected channels. 6 ADIE 0 R/W A/D Interrupt Enable Enables or disables the interrupt (ADI) requested at the end of A/D conversion. Set the ADIE when convertion is stopped. 0: A/D end interrupt request (ADI) is disabled 1: A/D end interrupt request (ADI) is enabled 5 ADST 0 R/W A/D Start Starts or stops A/D conversion. The ADST bit remains set to 1 during A/D conversion. It can also be set to 1 by external trigger input at the ADTRG pin. 0: A/D conversion is stopped 1: 1. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when conversion ends. 2. Multi mode: A/D conversion stauts: ADST is automatically cleard to 0 when conversion ends in all selected channels. 3. Scan mode: A/D conversion starts and continues, cycling among the selected channels, until ADST is cleared to 0 by software reset, or by a transition to standby mode. Rev. 4.00, 03/04, page 499 of 660 Bit 4 Bit Name MULTI Initial Value R/W 0 R/W Description Multi Mode Selects single mode, multi mode or scan mode. For further information on operation in these modes, see section 19.6, Operation. The mode is selected by the combination of this bit (MULTI) and bit 5 (SCN) of ADCR. MULTI 0 0 1 1 SCN 0 1 0 1 : Single mode : Single mode : Multi mode : Scan mode 3 CKS 0 R/W Clock Select Selects the A/D conversion time. Clear the ADST bit to 0 before switching the conversion time. 0: Conversion time = 536 states (maximum) 1: Conversion time = 266 states (maximum)* 2 2 1 0 CH2 CH1 CH0 0 0 0 R/W R/W R/W Channel Select These bits and the MULTI bit select the analog input channels. Clear the ADST bit to 0 before changing the channel selection. Single Mode (MULTI = 0) 000: AN0 001: AN1 010: AN2 011: AN3 Multi Mode and Scan Mode (MULTI = 1) AN0 AN0, AN1 AN0 to AN2 AN0 to AN3 Notes: 1. Only 0 can be written to clear the flag. 2. The CKS value should be set so that the A/D conversion time is 16 s (minimum). Rev. 4.00, 03/04, page 500 of 660 19.3.3 A/D Control Register (ADCR) ADCR is an 8-bit read/write register that enables or disables external triggering of A/D conversion. ADCR is initialized to H'07 by a reset and in standby mode. Bit 7 6 Bit Name TRGE1 TRGE0 Initial Value 0 0 R/W R/W R/W Description Trigger Enable Enables or disables external triggering of A/D conversion. 00: When an external trigger is input, the A/D conversion does not start 01: The same as above 10: The same as above 11: The A/D conversion starts at the falling edge of an input signal from the external trigger pin (ADTRG). 5 SCN 0 R/W Scan Mode Selects multi mode or scan mode when the MULTI bit is set to 1. See the description of bit 4 in 19.3.2, A/D Control/Status Register (ADCSR). 4, 3 -- All 0 R/W Reserved These bits are always read as 0. The write value should always be 0. 2 to 0 -- All 1 R Reserved These bits are always read as 1. The write value should always be 0. 19.4 Bus Master Interface ADDRA to ADDRD are 16-bit registers, but they are connected to the bus master by the upper 8 bits of the 16-bit peripheral data bus. Therefore, although the upper byte can be accessed directly by the bus master, the lower byte is read through an 8-bit temporary register (TEMP). An A/D data register is read as follows. When the upper byte is read, the upper-byte value is transferred directly to the bus master and the lower-byte value is transferred into TEMP. Next, when the lower byte is read, the TEMP contents are transferred to the bus master. When reading an A/D data register, always read the upper byte before the lower byte. It is possible to read only the upper byte, but if only the lower byte is read, the read value is not guaranteed. Rev. 4.00, 03/04, page 501 of 660 Figure 19.2 shows the data flow for access to an A/D data register. Upper byte read CPU (H'AA) Bus interface Module internal data bus TEMP (H'40) Upper byte of A/D data register (H'AA) Lower byte read Lower byte of A/D data register (H'40) CPU (H'40) Bus interface Module internal data bus TEMP (H'40) Upper byte of A/D data register (H'AA) Lower byte of A/D data register (H'40) Figure 19.2 A/D Data Register Access Operation (Reading H'AA40) Rev. 4.00, 03/04, page 502 of 660 19.5 19.5.1 Access Size of A/D Data Register Word Access When A/D data registers (ADDRA to ADDRD) are read in word, A/D data register values are read from bits 15 to 8, and invalid data is read from bits 7 to 0. Figure 19.3 shows an example of reading ADDRAH. 15 ADDRAH 87 Invalid data 0 Figure 19.3 Word Access Example 19.5.2 Longword Access When A/D data registers are read in longword, the upper byte of the A/D data register is read from bits 31 to 24, invalid data from bits 23 to 16, the lower byte of the A/D data register from bits 15 to 8, and invalid data from bits 7 to 0. Figure 19.4 shows an example of reading ADDRAH. 31 ADDRAH 24 23 Invalid data 16 15 ADDRAL 87 Invalid data 0 Figure 19.4 Longword Access Example 19.6 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 19.6.1 Single Mode (MULTI = 0) Single mode should be selected when only one A/D conversion on one channel is required. A/D conversion starts when the ADST bit in ADCSR is set to 1 by software, or by external trigger input. The ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when conversion ends. When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF. Rev. 4.00, 03/04, page 503 of 660 When the mode or analog input channel must be switched during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST bit can be set at the same time as the mode or channel is changed. Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure 19.5 shows a timing diagram for this example. 1. Single mode is selected (MULTI = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 = 1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1). 2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle. 3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested. 4. The A/D interrupt processing routine starts. 5. The routine reads ADCSR, then writes 0 in the ADF flag. 6. The routine reads and processes the conversion result (ADDRB = 0). 7. Execution of the A/D interrupt processing routine ends. Then, when the ADST bit is set to 1, A/D conversion starts to execute 2 to 7 above. Set* ADIE Set* ADST A/D conversion starts ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Note: * Downward arrows () indicate instruction execution. Read result A/D conversion result 1 Read result A/D conversion result 2 Waiting Waiting A/D conversion 1 Waiting Waiting Waiting A/D conversion result 2 Waiting Clear* Clear Set* Figure 19.5 Example of A/D Converter Operation (Single Mode, Channel 1 Selected) Rev. 4.00, 03/04, page 504 of 660 19.6.2 Multi Mode (MULTI = 1, SCN = 0) Multi mode should be selected when performing multi channel A/D conversions on one or more channels. When the ADST bit in ADCSR is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. When A/D conversions end on the selected channels, the ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data registers corresponding to the channels. When the mode or analog input channel selection must be changed during A/D conversion, to prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are described next. Figure 19.6 shows a timing diagram for this example. 1. Multi mode is selected (MULTI = 1, SCN = 0), channel group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and ADST bit is cleared to 0. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Rev. 4.00, 03/04, page 505 of 660 A/D conversion Set* ADST ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA ADDRB ADDRC ADDRD Note: * Downward arrows () indicate instruction executed by software. Clear* Clear* Waiting A/D conversion 1 Waiting A/D conversion 2 Waiting Waiting Waiting Waiting A/D conversion 3 Waiting Transfer A/D conversion result 1 A/D conversion result 2 A/D conversion result 3 Figure 19.6 Example of A/D Converter Operation (Multi Mode, Channels AN0 to AN2 Selected) 19.6.3 Scan Mode (MULTI = 1, SCN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit in the ADCSR is set to 1 by software or external trigger input, A/D conversion starts on the first channel in the group (AN0 when CH2 = 0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately. A/D conversion continues cyclically on the selected channels until the ADST bit is cleared to 0. The conversion results are transferred for storage into the ADDRA to ADDRD corresponding to the channels. When the mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the ADST bit to 0 to halt A/D conversion. After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from the first channel in the group. The ADST bit can be set at the same time as the mode or channel selection is changed. Typical operations when three channels (AN0 to AN2) are selected in scan mode are described next. Figure 19.7 shows a timing diagram for this example. Rev. 4.00, 03/04, page 506 of 660 1. Scan mode is selected (MULTI = 1, SCN = 1), channel group 0 is selected (CH2 = 0), analog input channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST = 1). 2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into ADDRA. Next, conversion of the second channel (AN1) starts automatically. 3. Conversion proceeds in the same way through the third channel (AN2). 4. When conversion of all the selected channels (AN0 to AN2) is completed, the ADF flag is set to 1 and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI interrupt is requested at this time. 5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion starts again from the first channel (AN0). Continuous A/D conversion Set*1 ADST Clear*1 ADF Channel 0 (AN0) operating Channel 1 (AN1) operating Channel 2 (AN2) operating Channel 3 (AN3) operating ADDRA*2 ADDRB*2 Waiting A/D conversion 1 Waiting A/D conversion 2 Waiting A/D conversion 3 Waiting Transfer A/D conversion result 1 A/D conversion result 4 Waiting A/D conversion 4 Waiting A/D conversion 5 Waiting Waiting Waiting Clear*1 A/D conversion result 2 ADDRC*2 A/D conversion result 3 ADDRD*2 Notes: 1. Downward arrows indicate instruction executed by software. 2. Data is ignored during conversion. Figure 19.7 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2 Selected) Rev. 4.00, 03/04, page 507 of 660 19.6.4 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit in ADCSR is set to 1, then starts conversion. Figure 19.8 shows the A/D conversion timing. Table 19.3 indicates the A/D conversion time. As indicated in figure 19.8, the A/D conversion time includes tD and the input sampling time. The length of tD varies depending on the timing of the write access to ADCSR. The total conversion time therefore varies within the ranges indicated in table 19.3. In multi mode and scan mode, the values given in table 19.3 apply to the first conversion. In the second and subsequent conversions the conversion time is fixed at 512 states when CKS = 0 or 256 states when CKS = 1. *1 P Address Write signal Input sampling timing ADF tD tSPL tCONV *2 : A/D conversion start delay tD tSPL : Input sampling time tCONV : A/D conversion time Notes: 1. ADCSR write cycle 2. ADCSR address Figure 19.8 A/D Conversion Timing Rev. 4.00, 03/04, page 508 of 660 Table 19.3 A/D Conversion Time (Single Mode) CKS = 0 Symbol A/D conversion start delay Input sampling time A/D conversion time tD tSPL tCONV Min 17 -- 514 Typ -- 129 -- Max 28 -- 525 Min 10 -- 259 CKS = 1 Typ -- 65 -- Max 17 -- 266 Note: Values in the table are numbers of states (tcyc). 19.6.5 External Trigger Input Timing A/D conversion can be externally triggered. When the TRGE1, TRGE0 bits in ADCR are set to 1. external trigger input is enabled at the ADTRG pin. A high-to-low transition at the ADTRG pin sets the ADST bit in ADCSR to 1, starting A/D conversion. Other operations, regardless of the conversion mode, are the same as if the ADST bit had been set to 1 by software. Figure 19.9 shows the timing. P External trigger signal ADST A/D conversion Figure 19.9 External Trigger Input Timing 19.7 Interrupt Requests The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt request can be enabled or disabled by the ADIE bit in ADCSR. Rev. 4.00, 03/04, page 509 of 660 19.8 Definitions of A/D Conversion Accuracy The A/D converter compares an analog value input from an analog input channel to its analog reference value and converts it into 10-bit digital data. The absolute accuracy of this A/D conversion is the deviation between the input analog value and the output digital value. It includes the following errors: * Offset error * Full-scale error * Quantization error * Nonlinearity error These four error quantities are explained below using figure 19.10. In the figure, the 10 bits of the A/D converter have been simplified to 3 bits. Offset error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the minimum (zero voltage) 0000000000 (000 in the figure) to 000000001 (001 in the figure) (figure 19.10, item (1)). Full-scale error is the deviation between actual and ideal A/D conversion characteristics when the digital output value changes from the 1111111110 (110 in the figure) to the maximum 1111111111 (111 in the figure) (figure 19.10, item (2)). Quantization error is the intrinsic error of the A/D converter and is expressed as 1/2 LSB (figure 19.10, item (3)). Nonlinearity error is the deviation between actual and ideal A/D conversion characteristics between zero voltage and full-scale voltage (figure 19.10, item (4)). Note that it does not include offset, full-scale or quantization error. (2) Full-scale error Digital output Ideal A/D conversion characteristics Digital output Ideal A/D conversion characteristics 111 110 101 100 011 010 001 000 (4) Nonlinearity error (3) Quantization error Actual A/D convertion characteristics FS Analog input voltage 1/8 2/8 3/8 4/8 5/8 6/8 7/8 FS Analog input voltage FS: Full-scale voltage 0 (1) Offset error Figure 19.10 Definitions of A/D Conversion Accuracy Rev. 4.00, 03/04, page 510 of 660 19.9 Usage Note When using the A/D converter, note the points listed in section 19.7.1 below. 19.9.1 Setting Analog Input Voltage * Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input pins ANn should be in the range AVSS ANn AVCC (n = 0 to 3). * AVCC, AVSS, Input Voltage: AVCC and AVSS should be related as follows: AVCC = VCCQ 0.2 V and AVSS = VSS. 19.9.2 Processing of Analog Input Pins To prevent damage from voltage surges at the analog input pins (AN0 to AN3), connect an input protection circuit like the one shown in figure 19.11. The circuit shown also includes an RC filter to suppress noise. This circuit is shown as an example; The circuit constants should be selected according to actual application conditions. Table 19.4 lists the analog input pin specifications and figure 19.12 shows an equivalent circuit diagram of the analog input ports. AVCC 100 * 0.1 F SuperH microprocessor AN0 to AN3 AVSS Note: * 10 F 0.01 F Figure 19.11 Example of Analog Input Protection Circuit 1.0 k AN0 to AN3 20 pF 1 M Figure 19.12 Analog Input Pin Equivalent Circuit Rev. 4.00, 03/04, page 511 of 660 Table 19.4 Analog Input Pin Ratings Item Analog input capacitance Allowable signal-source impedance Min -- -- Max 20 5 Unit pF k 19.9.3 Access Size and Read Data Table 19.5 shows the relationship between access size and read data. Note the read data obtained with different access sizes, bus widths, and endian modes. The case is shown here in which H'3FF is obtained when AVCC is input as an analog input. FF is the data containing the upper 8 bits of the conversion result, and C0 is the data containing the lower 2 bits. Table 19.5 Relationship between Access Size and Read Data Access Size Byte access Bus Width Command Endian MOV.L MOV.B MOV.L MOV.B MOV.L MOV.W MOV.L MOV.W 32 Bits (D31 to D0) Big Little 16 Bits (D15 to D0) Big Little FFFF C0C0 FFxx C0xx 8 Bits (D7 to D0) Big FF C0 FFxx C0xx Little FF C0 xxFF xxC0 #ADDRAH,R9 FFFFFFFF FFFFFFFF FFFF @R9,R8 #ADDRAL,R9 @R9,R8 C0C0C0C0 C0C0C0C0 C0C0 #ADDRAH,R9 @R9,R8 FFxxFFxx #ADDRAL,R9 @R9,R8 C0xxC0xx #ADDRAH,R9 @R9,R8 FFxxC0xx FFxxFFxx C0xxC0xx FFxxC0xx FFxx C0xx Word access Longword MOV.L access MOV.L FFxxC0xx C0xxFFxx FFxxC0xx xxC0xxFF Note: #ADDRAH .EQU H'A4000080 #ADDRAL .EQU H'A4000082 Values are shown in hexadecimal for the case where read data is output to an external device via R8. Rev. 4.00, 03/04, page 512 of 660 Section 20 D/A Converter (DAC) This LSI includes a D/A converter with two channels. Figure 20.1 shows a block diagram of the D/A converter. Module data bus AVCC DADR0 DADR1 DA0 AVSS 8-bit D/A Control circuit Legend DACR: D/A control register DADR0: D/A data register 0 DADR1: D/A data register 1 Figure 20.1 D/A Converter Block Diagram 20.1 Feature D/A converter features are listed below. * 8-bit resolution * Two output channels * Conversion time: maximum 10 s (with 20-pF capacitive load) * Output voltage: 0 V to AVcc DACR DA1 Rev. 4.00, 03/04, page 513 of 660 Bus interface On-chip data bus 20.2 Input/Output Pin Table 20.1 summarizes the D/A converter's input and output pins. Table 20.1 D/A Converter Pins Pin Name Analog power-supply pin Analog ground pin Analog output pin 0 Analog output pin 1 Abbreviation AVcc AVss DA0 DA1 I/O Input Input Output Output Function Analog power supply Analog ground and reference voltage Analog output, channel 0 Analog output, channel 1 20.3 Register Description The D/A converter has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * D/A data register 0 (DADR0) * D/A data register 1 (DADR1) * D/A control register (DACR) 20.3.1 D/A Data Registers 0 and 1 (DADR0 and DADR1) The D/A data registers (DADR0 and DADR1) are 8-bit read/write registers that store the data to be converted. When analog output is enabled, the D/A data register values are constantly converted and output at the analog output pins. The D/A data registers are initialized to H'00 by a reset. Rev. 4.00, 03/04, page 514 of 660 20.3.2 D/A Control Register (DACR) DACR is an 8-bit read/write register that controls the operation of the D/A converter. Bit 7 Bit Name DAOE1 Initial Value 0 R/W Description R/W D/A Output Enable 1 Controls D/A conversion and analog output. 0: DA1 analog output is disabled 1: Channel-1 D/A conversion and DA1 analog output are enabled 6 DAOE0 0 R/W D/A Output Enable 0 Controls D/A conversion and analog output. 0: DA0 analog output is disabled 1: Channel-0 D/A conversion and DA0 analog output are enabled 5 DAE 0 R/W D/A Enable Controls D/A conversion, together with bits DAOE0 and DAOE1. When the DAE bit is cleared to 0, D/A conversion is controlled independently in channels 0 and 1. When this LSI enters standby mode while D/A conversion is enabled, the D/A output is held and the analog power-supply current is equivalent to that during D/A conversion. To reduce the analog powersupply current in standby mode, clear the DAOE0 and DAOE1 bits and disable the D/A output. 00x: D/A conversion is disabled in channels 0 and 1 010: D/A conversion is enabled in channel 0 D/A conversion is disabled in channel 1 011: D/A conversion is enabled in channels 0 and 1 100: D/A conversion is disabled in channel 0 D/A conversion is enabled in channel 1 101: D/A conversion is enabled in channels 0 and 1 11x: D/A conversion is enabled in channels 0 and 1 When the DAE bit is set to 1, even if bits DAOE0 and DAOE1 in DACR and the ADST bit in ADCSR are cleared to 0, the same current is drawn from the analog power supply as during A/D and D/A conversion. 4 to 0 -- All 1 R Reserved These bits are always read as 1. The write value should always be 1. Note: x: Don't care Rev. 4.00, 03/04, page 515 of 660 20.4 Operation The D/A converter has two built-in D/A conversion circuits that can perform conversion independently. D/A conversion is performed constantly while enabled in DACR. If the DADR0 or DADR1 value is modified, conversion of the new data begins immediately. The conversion results are output when bits DAOE0 and DAOE1 are set to 1. An example of D/A conversion on channel 0 is given next. Timing is indicated in figure 20.2. 1. Data to be converted is written in DADR0. 2. Bit DAOE0 is set to 1 in DACR. D/A conversion starts and DA0 becomes an output pin. The converted result is output after the conversion time. The output value is (DADR0 contents/256) x AVcc. Output of this conversion result continues until the value in DADR0 is modified or the DAOE0 bit is cleared to 0. 3. If the DADR0 value is modified, conversion starts immediately, and the result is output after the conversion time. 4. When the DAOE0 bit is cleared to 0, DA0 becomes an input pin. DADR0 write cycle DACR write cycle DADR0 write cycle DACR write cycle Address bus DADR0 Conversion data 1 Conversion data 2 DAOE0 Conversion result 2 DA0 High-impedance state tDCONV Legend tDCONV : D/A conversion time Conversion result 1 tDCONV Figure 20.2 Example of D/A Converter Operation Rev. 4.00, 03/04, page 516 of 660 Section 21 User Debugging Interface (H-UDI) The H-UDI (user debugging interface) performs on-chip debugging which is supported by the SH7706. The H-UDI described here is a serial interface which is pi-compatible with JTAG (Joint Test Action Group, IEEE Standard 1149.1 and IEEE Standard Test Access Port and BoundaryScan Architecture) specifications. The H-UDI in the SH7706 supports a boundary scan mode, and is also used for emulator connection. When using an emulator, H-UDI functions should not be used. Refer to the emulator manual for the method of connecting the emulator. Figure 21.1 shows the block diagram of the H-UDI. TDI SDBSR SDBPR Shift register SDIR TDO MUX TCK TMS TRST TAP controller Decoder Local bus Figure 21.1 H-UDI Block Diagram Rev. 4.00, 03/04, page 517 of 660 21.1 Feature The H-UDI has the following features. * Support of the E10A emulator * Standard pin arrangement of JTAG * Real-time branch trace * 1-kbyte on-chip RAM for running the high-speed emulation program 21.2 Input/Output Pin Table 21.1 lists the pin configuration of the H-UDI. Table 21.1 Pin Configuraiton Name TCK Description H-UDI serial data input/output clock pin. Data is serially supplied to the H-UDI from the data input pin (TDI), and output from the data output pin (TDO), in synchronization with this clock. Mode select input pin. The state of the TAP control circuit is determined by changing this signal in synchronization with TCK. The protocol conforms to the JTAG standard (IEEE Std. 1149.1). H-UDI reset input pin. Input is accepted asynchronously with respect to TCK, and when low, the H-UDI is reset. See section 21.4.2, Reset Configuration, for more information. H-UDI serial data input pin. Data transfer to the H-UDI is executed by changing this signal in synchronization with TCK. H-UDI serial data output pin. Data output from the H-UDI is executed by reading this signal in synchronization with TCK. ASE mode select pin. If a low level is input at the ASEMD0 pin while the RESETP pin is asserted, ASE mode is entered; if a high level is input, normal operation mode is entered. ASEMD0 pin should be high level when an emulator or H-UDI is not used. In ASE mode, boundary scan and emulator functions can be used. The input level at the ASEMD0 pin should be held for at least one cycle after RESETP negation. Dedicated emulator pin TMS TRST TDI TDO ASEMD0 ASEBRKAK Rev. 4.00, 03/04, page 518 of 660 21.3 Register Description The H-UDI has the following registers. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Bypass register (SDBPR) * Instruction register (SDIR) * Boundary register (SDBSR) 21.3.1 Bypass Register (SDBPR) The bypass register is a 1-bit register that cannot be accessed by the CPU. When the SDIR is set to the bypass mode, the SDBPR is connected between H-UDI pins TDI and TDO. 21.3.2 Instruction Register (SDIR) The instruction register (SDIR) is a 16-bit read-only register. The register is in bypass mode in its initial state. It is initialized by TRST or in the TAP test-logic-reset state, and can be written by the H-UDI irrespective of the CPU mode. Operation is not guaranteed when a reserved command is set to this register. Bit 15 14 13 12 Bit Name TI3 TI2 TI1 TI0 Initial Value 1 1 1 1 R/W Description R R R R Test Instruction Bits Cannot be written by the CPU. 0000: EXTEST 0100: SAMPLE/PRELOAD 0101: Reserved (Setting prohibited) 0110: H-UDI reset negate 0111: H-UDI reset assert 100X: Reserved (Setting prohibited) 101X: H-UDI interrupt 110X: Reserved (Setting prohibited) 1110: Reserved (Setting prohibited) 1111: Bypass mode (initial value) 0001: Recovery from sleep Reserved These bits are always read as 1. Note: X Don't care 11 to 0 -- All 1 R Rev. 4.00, 03/04, page 519 of 660 21.3.3 Boundary Scan Register (SDBSR) The boundary scan register (SDBSR) is a shift register, located on the PAD, for controlling the input/output pins of this LSI. Using the EXTEST and SAMPLE/PRELOAD commands, a boundary scan test conforming to the JTAG standard can be carried out. Table 21.2 shows the correspondence between this LSI's pins and boundary scan register bits. Table 21.2 This LSI's Pins and Boundary Scan Register Bits Bit Pin Name I/O Bit 272 IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN 271 270 269 268 267 266 265 264 263 262 261 260 259 258 257 256 255 254 253 252 251 250 249 248 247 Pin Name D6 D5 D4 D3 D2 D1 D0 D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] D25/PTB[1] D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] D19/PTA[3] D18/PTA[2] D17/PTA[1] D16/PTA[0] D15 D14 D13 I/O IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT From TDI 297 296 295 294 293 292 291 290 289 288 287 286 285 284 283 282 281 280 279 278 277 276 275 274 273 D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] D25/PTB[1] D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] D19/PTA[3] D18/PTA[2] D17/PTA[1] D16/PTA[0] D15 D14 D13 D12 D11 D10 D9 D8 D7 Rev. 4.00, 03/04, page 520 of 660 Bit 246 245 244 243 242 241 240 239 238 237 236 235 234 233 232 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 214 213 Pin Name D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 D31/PTB[7] D30/PTB[6] D29/PTB[5] D28/PTB[4] D27/PTB[3] D26/PTB[2] D25/PTB[1] D24/PTB[0] D23/PTA[7] D22/PTA[6] D21/PTA[5] D20/PTA[4] D19/PTA[3] D18/PTA[2] D17/PTA[1] D16/PTA[0] D15 D14 D13 D12 D11 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Bit 212 211 210 209 208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 Pin Name D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 BS/PTC[0] WE2/DQMUL/ICIORD/PTC[1] WE3/DQMUU/ICIOWR/PTC[2] CS2/PTC[3] CS3/PTC[4] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 I/O Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Rev. 4.00, 03/04, page 521 of 660 Bit 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157 156 155 154 153 152 151 150 149 Pin Name A18 A19 A20 A21 A22 A23 A24 A25 BS/PTC[0] RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/PTC[1] WE3/DQMUU/ICIOWR/PTC[2] RD/WR CS0 CS2/PTC[3] CS3/PTC[4] A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Bit 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 Pin Name A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 BS/PTC[0] RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/PTC[1] WE3/DQMUU/ICIOWR/PTC[2] RD/WR CS0 CS2/PTC[3] CS3/PTC[4] CS4/PTC[5] CS5/CE1A/PTC[6] CS6/CE1B/PTC[7] CE2A/PTD[6] CE2B/PTD[7] RASL/PTD[0] I/O Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control IN IN IN IN IN IN Rev. 4.00, 03/04, page 522 of 660 Bit 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 Pin Name RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] CKE/PTD[4] IOIS16/PTD[5] BREQ WAIT DACK0/PTE[0] DACK1/PTE[1] DRAK0/PTE[2] DRAK1/PTE[3] AUDATA[0]/PTF[0] AUDATA[1]/PTF[1] AUDATA[2]/PTF[2] AUDATA[3]/PTF[3] AUDSYNC/PTF[4] ASEBRKAK/PTF[6] MD1 CS4/PTC[5] CS5/CE1A/PTC[6] CS6/CE1B/PTC[7] CE2A/PTD[6] CE2B/PTD[7] RASL/PTD[0] RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] CKE/PTD[4] IOIS16/PTD[5] BACK I/O IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Bit 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 Pin Name DACK0/PTE[0] DACK1/PTE[1] DRAK0/PTE[2] DRAK1/PTTE[3] AUDATA[0]/PTF[0] AUDATA[1]/PTF[1] AUDATA[2]/PTF[2] AUDATA[3]/PTF[3] AUDSYNC/PTF[4] ASEBRKAK/PTF[6] CS4/PTC[5] CS5/CE1A/PTC[6] CS6/CE1B/PTC[7] CE2A/PTD[6] CE2B/PTD[7] RASL/PTD[0] RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] CKE/PTD[4] IOIS16/PTD[5] BACK DACK0/PTE[0] DACK1/PTE[1] DRAK0/PTE[2] DRAK1/PTTE[3] AUDATA[0]/PTF[0] AUDATA[1]/PTF[1] AUDATA[2]/PTF[2] AUDATA[3]/PTF[3] I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Rev. 4.00, 03/04, page 523 of 660 Bit 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Pin Name AUDSYNC/PTF[4] ASEBRKAK/PTF[6] STATUS0/PTE[4] STATUS1/PTE[5] TCLK/PTE[6] IRQOUT/PTE[7] SCK0/SCPT[1] SCK2/SCPT[3] RTS2/SCPT[4] RxD0/SCPT[0] RxD2/SCPT[2] CTS2/IRQ5/SCPT[5] IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] NMI AUDCK/PTG[4] DREQ0/PTH[5] DREQ1/PTH[6] ADTRG/PTG[5] MD0 MD2 MD3 MD4 MD5 STATUS0/PTE[4] STATUS1/PTE[5] TCLK/PTE[6] I/O Control Control IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN IN OUT OUT OUT Bit 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 to TDO Pin Name IRQOUT/PTE[7] TxD0/SCPT[0] SCK0/SCPT[1] TxD2/SCPT[2] SCK2/SCPT[3] RTS2/SCPT[4] IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] DREQ0/PTH[5] DREQ1/PTH[6] STATUS0/PTE[4] STATUS1/PTE[5] TCLK/PTE[6] IRQOUT/PTE[7] TxD0/SCPT[0] SCK0/SCPT[1] TxD2/SCPT[2] SCK2/SCPT[3] RTS2/SCPT[4] IRQ0/IRL0/PTH[0] IRQ1/IRL1/PTH[1] IRQ2/IRL2/PTH[2] IRQ3/IRL3/PTH[3] IRQ4/PTH[4] DREQ0/PTH[5] DREQ1/PTH[6] I/O OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT OUT Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Control Rev. 4.00, 03/04, page 524 of 660 21.4 21.4.1 H-UDI Operations TAP Controller Figure 21.2 shows the internal states of TAP controller. State transitions basically conform with the JTAG standard. 1 Test-logic-reset 0 1 Select-DR-scan 0 1 Capture-DR 0 Shift-DR 1 Exit1-DR 0 Pause-DR 1 0 Exit2-DR 1 Update-DR 1 0 0 1 Capture-IR 0 Shift-IR 1 Exit1-IR 0 Pause-IR 1 0 Exit2-IR 1 Update-IR 1 0 0 1 Select-IR-scan 0 1 0 Run-test/idle 1 1 0 0 Figure 21.2 TAP Controller State Transitions Note: The transition condition is the TMS value on the rising edge of TCK. The TDI value is sampled on the rising edge of TCK; shifting occurs on the falling edge of TCK. The TDO value changes on the TCK falling edge. The TDO is at high impedance, except with shiftDR (shift-SR) and shift-IR states. When TRST = 0, there is a transition to test-logic-reset asynchronously with TCK. Rev. 4.00, 03/04, page 525 of 660 21.4.2 Reset Configuration Table 21.3 Reset Configuration ASDMD0* ASDMD0 H 1 RESETP L TRST L H Chip State Normal reset and H-UDI reset Normal reset H-UDI reset only Normal operation Reset hold* 2 3 H L H L L L H During ASE user mode* : Normal reset During ASE break mode* : RESETP assert is masked 3 H L H H-UDI reset only Normal operation Notes: 1. Performs normal operation mode and ASE mode settings ASEMD0 = H, normal operation mode ASEMD0 = L, ASE mode ASEMD0 pin should be high level when an emulator or H-UDI is not used. 2. During ASE mode, reset hold is enabled by setting RESETP and TRST pins at low level for a constant cycle. In this state, the CPU does not start up, even if RESETP is set to high level. When TRST is set to high level, H-UDI operation is enabled, but the CPU does not start up. The reset hold state is cancelled by the following: * Boot request from H-UDI (boot sequence) * Another RESETP assert (power-on reset) 3. ASE mode can be divided by two modes: a mode to execute the firmware program of the emulator (ASE break mode) and a mode to execute the user program (ASE user mode). Rev. 4.00, 03/04, page 526 of 660 21.4.3 H-UDI Reset An H-UDI reset is executed by setting an H-UDI reset assert command in SDIR. An H-UDI reset is of the same kind as a power-on reset. An H-UDI reset is released by inputting an H-UDI reset negate command. The interval required between the H-UDI reset assert command and the H-UDI reset negate command is the same as the time for which the RESETP pin is held low in order to execute a power-on reset. SDIR H-UDI reset assert H-UDI reset negate Chip internal reset CPU state Branch to H'A0000000 Figure 21.3 H-UDI Reset 21.4.4 H-UDI Interrupt The H-UDI interrupt function generates an interrupt by setting a command from the H-UDI in the SDIR. An H-UDI interrupt is a general exception/interrupt operation, resulting in a branch to an address based on the VBR value plus offset, and return by the RTE instruction. This interrupt request has a fixed priority level of 15. H-UDI interrupts are not accepted in sleep mode or standby mode. 21.4.5 Bypass The JTAG-based bypass mode for the H-UDI pins can be selected by setting a command from the H-UDI in the SDIR. 21.4.6 Using H-UDI to Recover from Sleep Mode It is possible to recover from sleep mode by setting a command (0001) from the H-UDI in SDIR. Rev. 4.00, 03/04, page 527 of 660 21.5 Boundary Scan A command can be set in SDIR by the H-UDI to place the H-UDI pins in the boundary scan mode stipulated by JTAG. 21.5.1 Supported Instructions This LSI supports the three essential instructions defined in the JTAG standard (BYPASS, SAMPLE/PRELOAD, and EXTEST). BYPASS: The BYPASS instruction is an essential standard instruction that operates the bypass register. This instruction shortens the shift path to speed up serial data transfer involving other chips on the printed circuit board. While this instruction is executing, the test circuit has no effect on the system circuits. The instruction code is 1111. SAMPLE/PRELOAD: The SAMPLE/PRELOAD instruction inputs values from this LSI's internal circuitry to the boundary scan register, outputs values from the scan path, and loads data onto the scan path. When this instruction is executing, this LSI's input pin signals are transmitted directly to the internal circuitry, and internal circuit values are directly output externally from the output pins. This LSI's system circuits are not affected by execution of this instruction. The instruction code is 0100. In a SAMPLE operation, a snapshot of a value to be transferred from an input pin to the internal circuitry, or a value to be transferred from the internal circuitry to an output pin, is latched into the boundary scan register and read from the scan path. Snapshot latching is performed in synchronization with the rise of TCK in the Capture-DR state. Snapshot latching does not affect normal operation of this LSI. In a PRELOAD operation, an initial value is set in the parallel output latch of the boundary scan register from the scan path prior to the EXTEST instruction. Without a PRELOAD operation, when the EXTEST instruction was executed an undefined value would be output from the output pin until completion of the initial scan sequence (transfer to the output latch) (with the EXTEST instruction, the parallel output latch value is constantly output to the output pin). EXTEST: This instruction is provided to test external circuitry when this LSI is mounted on a printed circuit board. When this instruction is executed, output pins are used to output test data (previously set by the SAMPLE/PRELOAD instruction) from the boundary scan register to the printed circuit board, and input pins are used to latch test results into the boundary scan register from the printed circuit board. If testing is carried out by using the EXTEST instruction N times, the Nth test data is scanned-in when test data (N-1) is scanned out. Rev. 4.00, 03/04, page 528 of 660 Data loaded into the output pin boundary scan register in the Capture-DR state is not used for external circuit testing (it is replaced by a shift operation). The instruction code is 0000. 21.5.2 Notes for Boundary Scan 1. Boundary scan mode does not cover clock-related signals (EXTAL, EXTAL2, XTAL, XTAL2, CKIO). 2. Boundary scan mode does not cover reset-related signals (RESETP, RESETM, CA). 3. Boundary scan mode does not cover H-UDI-related signals (TCK, TDI, TDO, TMS, TRST). 4. When a boundary scan test is carried out, ensure that the CKIO clock operates constantly. The CKIO frequency range is as follows: Minimum: 1 MHz Maximum: Maximum frequency for respective clock mode specified in the CPG section Set pins MD[2:0] to the clock mode to be used. After powering on, wait for the CKIO clock to stabilize before performing a boundary scan test. 5. Fix the RESETP pin low. 6. Fix the CA pin high, and the ASEMD0 pin low. 21.6 Usage Note 1. An H-UDI command other than an H-UDI interrupt, once set, will not be modified as long as another command is not re-issued from the H-UDI. An H-UDI interrupt command, however, will be changed to a bypass command once set. 2. Because chip operations are suspended in standby mode, H-UDI commands are not accepted. However, the TAP controller remains in operation at this time. 3. The H-UDI is used for emulator connection. Therefore, H-UDI functions cannot be used when using an emulator. 21.7 Advanced User Debugger (AUD) The AUD is a function exclusively for use by an emulator. Refer to the User's Manual for the relevant emulator for details of the AUD. Rev. 4.00, 03/04, page 529 of 660 Rev. 4.00, 03/04, page 530 of 660 Section 22 Power-Down Modes In the power-down modes, all CPU and some on-chip supporting module functions are halted. This lowers power consumption. The SH7706 has four power-down modes: 1. Sleep mode 2. Software standby mode 3. Module standby function (TMU, RTC, SCI, UBC, DMAC, DAC, ADC, and SCIF on-chip supporting modules) 4. Hardware standby mode Table 22.1 shows the transition conditions for entering the modes from the program execution state, as well as the CPU and supporting module states in each mode and the procedures for canceling each mode. Table 22.1 Power-Down Modes State Transition Conditions CPU Register On-Chip On-Chip Peripheral Memory Modules Pins Held Runs Held External Memory Refresh Canceling Procedure 1. Interrupt 2. Reset Mode Sleep mode CPG CPU Execute SLEEP Runs Halts Held instruction with STBY bit cleared to 0 in STBCR Execute SLEEP Halts Halts Held instruction with STBY bit set to 1 in STBCR Set MSTP bit of STBCR to 1 Runs Runs Held *4 Software standby mode Module standby function Held Halts*1 Held Selfrefresh 1. Interrupt 2. Reset Held Specified module halts Halts*3 *2 Refresh 1. Clear MSTP bit to 0 2. Power-on reset Hardware Drive CA pin low standby mode Halts Halts Held Held Held Selfrefresh Power-on reset Notes: 1. The RTC still runs if the START bit in RCR2 is set to 1 (see section 13, Realtime Clock (RTC)). TMU still runs when output of the RTC is used as input to its counter (see section 12, Timer Unit (TMU)). 2. Depends on the on-chip supporting module. TMU external pin: Held SCI external pin: Reset 3. The RTC still runs if the START bit in RCR2 is set to 1. TMU does not run. 4. When the LSI enters sleep mode, the CPU halts. Rev. 4.00, 03/04, page 531 of 660 22.1 Input/Output Pin Table 22.2 lists the pins used for the power-down modes. Table 22.2 Pin Configuration Pin Name Symbol I/O O Description Operating state of the processor. STATUS1 High-level High-level Low-level Low-level STATUS0 High-level Low-level High-level Low-level state Reset Sleep mode Standby mode Normal operation Processing state 1 STATUS1 Processing state 0 STATUS0 22.2 Register Description These are two control registers for the power-down modes. Refer to section 23, List of Registers, for more details of the addresses and access sizes. * Standby control register (STBCR) * Standby control register 2 (STBCR2) 22.2.1 Standby Control Register (STBCR) The standby control register (STBCR) is an 8-bit read/write register that sets the power-down mode. Bit 7 Bit Name STBY Initial Value 0 R/W R/W Description Software Standby Specifies transition to software standby mode. 0: Executing SLEEP instruction puts the chip into sleep mode. 1: Executing SLEEP instruction puts the chip into software standby mode. 6, 5 -- All 0 R Reserved These bits are always read as 0. The write value should always be 0. Rev. 4.00, 03/04, page 532 of 660 Bit 4 Bit Name STBXTL Initial Value 0 R/W R/W Description Standby Crystal Specifies whether the crystal oscillator halts or oscillates in standby mode. 0: Halts the oscillation of the crystal oscillator in standby mode. 1: Continues the oscillation of the crystal oscillator even in standby mode. 3 -- 0 R Reserved These bits are always read as 0. The write value should always be 0. 2 MSTP2 0 R/W Module Stop 2 Specifies halting the clock supply to the timer unit TMU (an on-chip supporting module). When the MSTP2 bit is set to 1, the supply of the clock to the TMU is halted. 0: TMU runs. 1: Clock supply to TMU is halted. 1 MSTP1 0 R/W Module Stop 1 Specifies halting the clock supply to the realtime clock RTC (an on-chip supporting module). When the MSTP1 bit is set to 1, the supply of the clock to RTC is halted. When the clock halts, all RTC registers become inaccessible, but the counter keeps running. 0: RTC runs. 1: Clock supply to RTC is halted. 0 MSTP0 0 R/W Module Stop 0 Specifies halting the clock supply to the serial communication interface SCI (an on-chip supporting module). When the MSTP0 bit is set to 1, the supply of the clock to the SCI is halted. 0: SCI operates. 1: Clock supply to SCI is halted. Rev. 4.00, 03/04, page 533 of 660 22.2.2 Standby Control Register 2 (STBCR2) The standby control register 2 (STBCR2) is a read/write 8-bit register that sets the power-down mode. Bit 7 Bit Name -- Initial Value 0 R/W R Description Reserved This bit is always read as 0. The write value should always be 0. 6 MDCHG 0 R/W Pin MD5 to MD0 Control Specifies whether or not pins MD5 to MD0 are changed in software standby mode. When this bit is set to 1, the MD5 to MD0 pin values are latched when returning from software standby mode by means of a reset or interrupt. 0: Pins MD5 to MD0 are not changed in software standby mode 1: Pins MD5 to MD0 are changed in software standby mode 5 MSTP8 0 R/W Module Stop 8 Specifies halting the clock supply to the user break controller UBC (an on-chip supporting module). When the MSTP8 bit is set to 1, the supply of the clock to the UBC is halted. 0: UBC runs 1: Clock supply to UBC is halted 4 MSTP7 0 R/W Module Stop 7 Specifies halting of clock supply to the DMAC (an on-chip peripheral module). When the MSTP7 bit is set to 1, the supply of the clock to the DMAC is halted. 0: DMAC runs 1: Clock supply to DMAC halted 3 MSTP6 0 R/W Module Stop 6 Specifies halting of clock supply to the DAC (an on-chip peripheral module). When the MSTP6 bit is set to 1, the supply of the clock to the DAC is halted. 0: DAC runs 1: Clock supply to DAC halted Rev. 4.00, 03/04, page 534 of 660 Bit 2 Bit Name MSTP5 Initial Value 0 R/W R/W Description Module Stop 5 Specifies halting of clock supply to the ADC (an on-chip peripheral module). When the MSTP5 bit is set to 1, the supply of the clock to the ADC is halted and all registers are initialized. 0: ADC runs 1: Clock supply to ADC halted and all registers initialized 1 MSTP4 0 R/W Module Stop 4 Specifies halting the clock supply to the serial communication interface with FIFO (an on-chip peripheral module). When the MSTP1 bit is set to 1, the supply of the clock to the SCIF is halted. 0: SCIF runs 1: Clock supply to SCIF halted 0 -- 0 R Reserved This bit is always read as 0. The write value should always be 0. 22.3 22.3.1 Operation Sleep Mode * Transition to Sleep Mode Executing the SLEEP instruction when the STBY bit in STBCR is 0 causes a transition from the program execution state to sleep mode. Although the CPU halts immediately after executing the SLEEP instruction, the contents of its internal registers remain unchanged. The on-chip supporting modules continue to run during sleep mode and the clock continues to be output to the CKIO pin. In sleep mode, the STATUS1 pin is set high and the STATUS0 pin low. * Canceling Sleep Mode Sleep mode is canceled by an interrupt (NMI, IRQ, IRL, on-chip supporting module) or reset. Interrupts are accepted during sleep mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction. Canceling with an Interrupt: When an NMI, IRQ, IRL or on-chip supporting module interrupt occurs, sleep mode is canceled and interrupt exception processing is executed. A code indicating the interrupt source is set in the INTEVT and INTEVT2 registers. Canceling with a Reset: Sleep mode is canceled by a power-on reset or a manual reset. Rev. 4.00, 03/04, page 535 of 660 22.3.2 Software Standby Mode * Transition to Software Standby Mode To enter standby mode, set the STBY bit to 1 in STBCR, then execute the SLEEP instruction. The chip moves from the program execution state to software standby mode. In software standby mode, power consumption is greatly reduced by halting not only the CPU, but the clock and onchip supporting modules as well. The clock output from the CKIO pin also halts. CPU and cache register contents are held, but some on-chip supporting modules are initialized. Table 22.3 lists the states of registers in software standby mode. Table 22.3 Register States in Software Standby Mode Module Interrupt controller (INTC) On-chip clock pulse generator (CPG) User Break controller (UBC) Bus state controller (BSC) Timer unit (TMU) Realtime clock (RTC) A/D converter (ADC) D/A converter (DAC) Registers Initialized -- -- -- -- TSTR register -- All registers -- Registers Retaining Data All registers All registers All registers All registers Registers other than TSTR All registers -- All registers The procedure for moving to software standby mode is as follows: 1. Clear the TME bit in the WDT's timer control register (WTCSR) to 0 to stop the WDT. Set the WDT's timer counter (WTCNT) and the CKS2 to CKS0 bits of the WTCSR register to appropriate values to secure the specified oscillation settling time. 2. After the STBY bit in the STBCR register is set to 1, a SLEEP instruction is executed. 3. Software standby mode is entered and the clocks within the chip are halted. The STATUS1 pin output goes low and the STATUS0 pin output goes high. Rev. 4.00, 03/04, page 536 of 660 * Canceling Software Standby Mode Standby mode is canceled by an interrupt (NMI, IRQ*1, IRL*1, or on-chip supporting module)* or a reset. 2 Canceling with an Interrupt: The on-chip WDT can be used for hot starts. When the chip detects 1 1 an NMI, IRL* , IRQ* , or on-chip supporting module (except the interval timer)*2 interrupt, the clock will be supplied to the entire chip and software standby mode canceled after the time set in the WDT's timer control/status register has elapsed. The STATUS1 and STATUS0 pins both go low. Interrupt processing then begins and a code indicating the interrupt source is set in the INTEVT and INTEVT2 registers. After branching to the interrupt processing routine occurs, clear the STBY bit in the STBCR register. The WTCNT stops automatically. If the STBY bit is not 3 cleared, WTCNT continues operation and transits to the standby mode* when it reaches H'80. This function prevents the data from being destroyed due to a rising voltage under an unstable power supply. Interrupts are accepted during software standby mode even when the BL bit in the SR register is 1. If necessary, save SPC and SSR in the stack before executing the SLEEP instruction. Immediately after an interrupt is detected, the phase of the clock output of the CKIO pin may be unstable, until the processor starts interrupt processing. (The canceling condition is that the IRL3 to IRL0 level is higher than the mask level in the I3 to I0 bits in the SR register.) Notes: 1. Software Standby mode can be canceled using IRL3 to IRL0 or IRQ4 to IRQ0. 2. Software standby mode can be canceled with an RTC or TMU (only when running on the RTC clock) interrupt. 3. Standby mode should be canceled by power-on resets. Operations at manual resets or during interrupt input are not guaranted. Interrupt request Crystal oscillator settling time and PLL synchronization time WTCNT value H'FF WDT overflow and branch to interrupt handling routine Clear bit STBCR.STBY before WTCNT reaches H'80. When STBCR.STBY is cleared, WTCNT halts automatically. H'80 Time Figure 22.1 Canceling Software Standby Mode with STBCR.STBY Rev. 4.00, 03/04, page 537 of 660 Canceling with a Reset: Standby mode can be canceled with a reset (power-on or manual). Keep the RESETP pin and RESETM pin low until the clock oscillation settles. * Clock Pause Function In software standby mode, the clock input from the EXTAL pin or CKIO pin can be halted and the frequency can be changed. This function is used as follows: 1. Enter software standby mode using the appropriate procedures. 2. Once software standby mode is entered and the clock stopped within the chip, the STATUS1 pin output is low and the STATUS0 pin output is high. 3. Once the STATUS1 pin goes low and the STATUS0 pin goes high, the input clock is stopped or the frequency is changed. 4. When the frequency is changed, an NMI, IRL, IRQ or on-chip supporting module (except the internal timer) interrupt is input after the change. When the clock is stopped, the same interrupts are input after the clock is applied. 5. After the time set in the WDT has elapsed, the clock starts being applied internally within the chip, the STATUS1 and STATUS0 pins both go low, interrupts are handled, and operation resumes. Rev. 4.00, 03/04, page 538 of 660 22.3.3 Module Standby Function * Transition to Module Standby Function Setting the standby control register MSTP8 to MSTP4, MSTP2 to MSTP0 bits to 1 halts the supply of clocks to the corresponding on-chip supporting modules. This function can be used to reduce the power consumption in normal mode and sleep mode. The module standby function holds the state prior to halt of the external pins of the on-chip supporting modules. TMU external pins hold their state prior to the halt. SCI external pins go to the reset state. With a few exceptions, all registers hold their values. Bit MSTP8 Value 0 1 MSTP7 0 1 MSTP6 0 1 MSTP5 0 1 MSTP4 0 1 MSTP2 0 1 MSTP1 0 1 MSTP0 0 1 Description UBC runs. Supply of clock to UBC halted. DMAC runs. Supply of clock to DMAC halted. DAC runs. Supply of clock to DAC halted. ADC runs. Supply of clock to ADC halted, and all registers initialized. SCIF runs. Supply of clock to SCIF halted. TMU runs. Supply of clock to TMU halted. Registers initialized.* RTC runs. Supply of clock to RTC halted. Register access prohibited.* SCI runs. Supply of clock to SCI halted. 2 1 Notes: 1. The registers initialized are the same as in the software standby mode (table 22.3). 2. The counter runs. * Clearing the Module Standby Function The module standby function can be cleared by clearing the MSTP8 to MSTP4, MSTP2 to MSTP0 bits to 0, or by a power-on reset or manual reset. Rev. 4.00, 03/04, page 539 of 660 22.3.4 Timing of STATUS Pin Changes The timing of STATUS1 and STATUS0 pin changes is shown in figures 22.2 through 22.9 * Timing for Resets Power-On Reset: CKIO PLL settling time STATUS Normal*2 Reset*1 Normal*2 0 to 5 Bcyc*3 Notes: 1. 2. 3. Reset: Normal: Bcyc: HH (STATUS1 high, STATUS0 high) LL (STATUS1 low, STATUS0 low) Bus clock cycle 0 to 30 Bcyc*3 Figure 22.2 Power-On Reset STATUS Output Manual Reset: CKIO *1 STATUS Normal*3 Reset*2 Normal*3 0 Bcyc or more*4 0 to 30 Bcyc*4 Notes: 1. 2. 3. 4. During manual reset, STATUS becomes HH (reset) and the internal reset begins after waiting for the executing bus cycle to end. Reset: HH (STATUS1 high, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Figure 22.3 Manual Reset STATUS Output Rev. 4.00, 03/04, page 540 of 660 * Timing for Canceling Software Standbys Software Standby to Interrupt: Oscillation stops Interrupt request WDT overflow CKIO WDT count STATUS Normal*2 Standby*1 Normal*2 Notes: 1. 2. Standby: Normal: LH (STATUS1 low, STATUS0 high) LL (STATUS1 low, STATUS0 low) Figure 22.4 Software Standby to Interrupt STATUS Output Software Standby to Power-On Reset: Oscillation stops Reset CKIO *1 STATUS Normal*4 Standby*3 *6 Reset*2 Normal*4 0 to 10 Bcyc*5 Notes: 1. 2. 3. 4. 5. 6. 0 to 30 Bcyc*5 When software software standby mode is cleared with a power-on reset, the WDT does not count. low during the PLL's oscillation settling time. Keep Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Undefined Figure 22.5 Software Standby to Power-On Reset STATUS Output Rev. 4.00, 03/04, page 541 of 660 Software Standby to Manual Reset: Oscillation stops Reset CKIO *1 STATUS Normal*4 Standby*3 Reset*2 Normal*4 0 to 20 Bcyc*5 Notes: 1. 2. 3. 4. 5. When software standby mode is cleared with a manual reset, the WDT does not count. low during the PLL's oscillation settling time. Keep Reset: HH (STATUS1 high, STATUS0 high) Standby: LH (STATUS1 low, STATUS0 high) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Figure 22.6 Software Standby to Manual Reset STATUS Output * Timing for Canceling Sleep Mode Sleep to Interrupt: Interrupt request CKIO STATUS Normal*2 Sleep*1 Normal*2 Notes: 1. 2. Sleep: Normal: HL (STATUS1 high, STATUS0 low) LL (STATUS1 low, STATUS0 low) Figure 22.7 Sleep to Interrupt STATUS Output Rev. 4.00, 03/04, page 542 of 660 Sleep to Power-On Reset: Reset CKIO *1 STATUS Normal*4 Sleep*3 *6 0 to 10 Bcyc*5 Reset*3 Normal*4 0 to 30 Bcyc*5 low during the Notes: 1. 2. 3. 4. 5. 6. When the PLL1's multiplication ratio is changed by a power-on reset, keep PLL's oscillation settling time. Reset: HH (STATUS1 high, STATUS0 high) Sleep: HL (STATUS1 high, STATUS0 low) Normal: LL (STATUS1 low, STATUS0 low) Bcyc: Bus clock cycle Undefined Figure 22.8 Sleep to Power-On Reset STATUS Output Sleep to Manual Reset: Reset CKIO *1 STATUS Normal*4 Sleep*3 Reset*2 Normal*4 0 to 80 Bcyc*5 Notes: 1. 2. 3. 4. 5. Keep Reset: Sleep: Normal: Bcyc: low until STATUS becomes reset. HH (STATUS1 high, STATUS0 high) HL (STATUS1 high, STATUS0 low) LL (STATUS1 low, STATUS0 low) Bus clock cycle 0 to 30 Bcyc*5 Figure 22.9 Sleep to Manual Reset STATUS Output Rev. 4.00, 03/04, page 543 of 660 22.3.5 Hardware Standby Function * Transition to Hardware Standby Mode Driving the CA pin low causes a transition to hardware standby mode. In hardware standby mode, all modules except those operating on an RTC clock are halted, as in the software standby mode entered on execution of a SLEEP instruction ((software) standby mode). Hardware standby mode differs from software standby mode as follows. 1. Interrupts and manual resets are not accepted. 2. The TMU does not operate. Operation when a low-level signal is input at the CA pin depends on the CPG state, as follows. 1. In software standby mode The clock remains stopped and the chip enters the hardware standby state. Acceptance of interrupts and manual resets is disabled, TCLK output is fixed low, and the TMU halts. 2. During WDT operation when software standby mode is canceled by an interrupt The chip enters hardware standby mode after standby mode is canceled and the CPU resumes operation. 3. In sleep mode The chip enters hardware standby mode after sleep mode is canceled and the CPU resumes operation. Hold the CA pin low in hardware standby mode. In hardware standby mode, the LSI can supply power only to the RTC power-supply pin. * Canceling Hardware Standby Mode Hardware standby mode can only be canceled by a power-on reset. When the CA pin is driven high while the RESETP pin is low, clock oscillation is started. Hold the RESETP pin low until clock oscillation stabilizes. When the RESETP pin is driven high, the CPU begins power-on reset processing. If an interrupt or manual reset is input, correct operation cannot be guaranteed. Rev. 4.00, 03/04, page 544 of 660 * Hardware Standby Mode Timing Figures 22.10 and 22.11 show examples of pin timing in hardware standby mode. The CA pin is sampled using EXTAL2 (32.768 kHz), and a hardware standby request is only recognized when the pin is low for two consecutive clock cycles. The CA pin must be held low while the chip is in hardware standby mode. Clock oscillation starts when the CA pin is driven high after the RESETP pin is driven low. CKIO CA STATUS Normal*3 Standby*2 Undefined Reset*1 Normal*3 2 Rcyc or more*5 Notes: 1. 2. 3. 4. 5. Reset: Standby: Normal: Bcyc: Rcyc: HH (STATUS1 high, STATUS0 high) LH (STATUS1 low, STATUS0 high) LL (STATUS1 low, STATUS0 low) Bus clock cycle EXTAL2 (32.768 kHz) cycle 0 to 10Bcyc*4 0 to 30Bcyc*4 Figure 22.10 Hardware Standby Mode (When CA Goes Low in Normal Operation) Rev. 4.00, 03/04, page 545 of 660 CKIO CA 4-5-62 STATUS Standby*2 Normal*3 Standby*2 Undefined Reset*1 WDT operation 0 to 10 Bcyc*4 2 Rcyc or more*5 Notes: 1. 2. 3. 4. 5. Reset: Standby: Normal: Bcyc: Rcyc: HH (STATUS1 high, STATUS0 high) LH (STATUS1 low, STATUS0 high) LL (STATUS1 low, STATUS0 low) Bus clock cycle EXTAL2 (32.768 kHz) cycle Figure 22.11 Hardware Standby Mode Timing (When CA Goes Low during WDT Operation on Standby Mode Cancellation) Rev. 4.00, 03/04, page 546 of 660 Section 23 List of Registers 23.1 PTEH PTEL TTB TEA MMUCR BASRA BASRB CCR CCR2 TRA EXPEVT INTEVT BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR BETR BRSR BRDR FRQCR STBCR STBCR2 WTCNT WTCSR BCR1 BCR2 BSC CPG UBC Register Address Map Module* CCN 1 Control Register Bus* L L L L L L L L I L L L L L L L L L L L L L L L I I I I I I I 2 Address H'FFFFFFF0 H'FFFFFFF4 H'FFFFFFF8 H'FFFFFFFC H'FFFFFFE0 H'FFFFFFE4 H'FFFFFFE8 H'FFFFFFEC H'A40000B0 H'FFFFFFD0 H'FFFFFFD4 H'FFFFFFD8 H'FFFFFFB0 H'FFFFFFB4 H'FFFFFFB8 H'FFFFFFA0 H'FFFFFFA4 H'FFFFFFA8 H'FFFFFF90 H'FFFFFF94 H'FFFFFF98 H'FFFFFF9C H'FFFFFFAC H'FFFFFFBC H'FFFFFF80 H'FFFFFF82 H'FFFFFF88 H'FFFFFF84 H'FFFFFF86 H'FFFFFF60 H'FFFFFF62 Size (Bits) 32 32 32 32 32 8 8 32 32 32 32 32 32 32 16 32 32 16 32 32 32 16 32 32 16 8 8 8 8 16 16 Access Size (Bits)* 32 32 32 32 32 8 8 32 32 32 32 32 32 32 16 32 32 16 32 32 32 16 32 32 16 8 8 8, 16 8, 16 16 16 3 Rev. 4.00, 03/04, page 547 of 660 Control Register WCR1 WCR2 MCR PCR RTCSR RTCNT RTCOR RFCR SDMR R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 ICR0 IPRA IPRB Module* BSC 1 Bus* I I I I I I I I I 2 Address H'FFFFFF64 H'FFFFFF66 H'FFFFFF68 H'FFFFFF6C H'FFFFFF6E H'FFFFFF70 H'FFFFFF72 H'FFFFFF74 Size (Bits) 16 16 16 16 16 16 16 16 Access Size (Bits)* 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 3 H'FFFFD000 to -- H'FFFFEFFF H'FFFFFEC0 H'FFFFFEC2 H'FFFFFEC4 H'FFFFFEC6 H'FFFFFEC8 H'FFFFFECA H'FFFFFECC H'FFFFFECE H'FFFFFED0 H'FFFFFED2 H'FFFFFED4 H'FFFFFED6 H'FFFFFED8 H'FFFFFEDA H'FFFFFEDC H'FFFFFEDE H'FFFFFEE0 H'FFFFFEE2 H'FFFFFEE4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 16 16 RTC P P P P P P P P P P P P P P P P INTC I I I Rev. 4.00, 03/04, page 548 of 660 Control Register TOCR TSTR TCOR_0 TCNT_0 TCR_0 TCOR_1 TCNT_1 TCR_1 TCOR_2 TCNT_2 TCR_2 TCPR_2 SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR INTEVT2 IRR0 IRR1 IRR2 ICR1 IPRC IPRD IPRE SAR_0 DAR_0 DMATCR_0 CHCR_0 Module* TMU 1 Bus* P P P P P P P P P P P P 2 Address H'FFFFFE90 H'FFFFFE92 H'FFFFFE94 H'FFFFFE98 H'FFFFFE9C H'FFFFFEA0 H'FFFFFEA4 H'FFFFFEA8 H'FFFFFEAC H'FFFFFEB0 H'FFFFFEB4 H'FFFFFEB8 H'FFFFFE80 H'FFFFFE82 H'FFFFFE84 H'FFFFFE86 H'FFFFFE88 H'FFFFFE8A H'FFFFFE8C H'04000000 H'A4000004 H'A4000006 H'A4000008 H'A4000010 H'A4000016 H'A4000018 H'A400001A H'A4000020 H'A4000024 H'A4000028 H'A400002C Size (Bits) 8 8 32 32 16 32 32 16 32 32 16 32 8 8 8 8 8 8 8 32 16 16 16 16 16 16 16 32 32 32 32 Access Size (Bits)* 8 8 32 32 16 32 32 16 32 32 16 32 8 8 8 8 8 8 8 32 8 8 8 16 16 16 16 16,32 16,32 16,32 8,16,32 3 SCI P P P P P P P INTC I I I I I I I I DMAC P P P P Rev. 4.00, 03/04, page 549 of 660 Control Register SAR_1 DAR_1 DMATCR_1 CHCR_1 SAR_2 DAR_2 DMATCR_2 CHCR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 DMAOR CMSTR CMCSR CMCNT CMCOR ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR DADR0 DADR1 DACR Module* DMAC 1 Bus* P P P P P P P P P P P P P 2 Address H'A4000030 H'A4000034 H'A4000038 H'A400003C H'A4000040 H'A4000044 H'A4000048 H'A400004C H'A4000050 H'A4000054 H'A4000058 H'A400005C H'A4000060 H'A4000070 H'A4000072 H'A4000074 H'A4000076 H'A4000080 H'A4000082 H'A4000084 H'A4000086 H'A4000088 H'A400008A H'A400008C H'A400008E H'A4000090 H'A4000092 H'A40000A0 H'A40000A2 H'A40000A4 Size (Bits) 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 Access Size (Bits)* 16,32 16,32 16,32 8,16,32 16,32 16,32 16,32 8,16,32 16,32 16,32 16,32 8,16,32 8,16 8,16,32 8,16,32 8,16,32 8,16,32 8,16,32* * 8,16* 4 45 45 3 CMT P P P P A/D P P P P P P P P P P 8,16,32* * 8,16* 4 8,16,32* * 8,16* 4 45 8,16,32* * 8,16* 4 45 8,16,32* * 8,16 8,16,32* * 8,16* 4 45 D/A P P P 45 8,16,32 Rev. 4.00, 03/04, page 550 of 660 Control Register PACR PBCR PCCR PDCR PECR PFCR PGCR PHCR PJCR SCPCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR SCPDR SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCSSR2 SCFRDR2 SCFCR2 SCFDR2 SDIR Module* PORT 1 Bus* P P P P P P P P P P P P P P P P P P P P 2 Address H'A4000100 H'A4000102 H'A4000104 H'A4000106 H'A4000108 H'A400010A H'A400010C H'A400010E H'A4000110 H'A4000116 H'A4000120 H'A4000122 H'A4000124 H'A4000126 H'A4000128 H'A400012A H'A400012C H'A400012E H'A4000130 H'A4000136 H'A4000150 H'A4000152 H'A4000154 H'A4000156 H'A4000158 H'A400015A H'A400015C H'A400015E H'A4000200 Size (Bits) 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 16 16 Access Size (Bits)* 16 16 16 16 16 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 8 16 8 8 16 16 3 SCIF P P P P P P P P UDI I Rev. 4.00, 03/04, page 551 of 660 Notes: 1. Modules: CCN: Cache controller UBC: User break controller CPG: Clock pulse generator BSC: Bus state controller RTC: Realtime clock INTC: Interrupt controller TMU: Timer unit SCI: Serial communication interface 2. Internal buses: L: CPU, CCN, cache, and TLB connected I: BSC, cache, DMAC, INTC, CPG, and H-UDI connected P: BSC and peripheral modules (RTC, TMU, SCI, SCIF, A/D, D/A, DMAC, ports, CMT) connected 3. The access size shown is for control register access (read/write). An incorrect result will be obtained if a different size from that shown is used for access. 4. With 16-bit access, it is not possible to read data in two registers simultaneously. 5. With 32-bit access, it is not possible to read data in the register at [accessed address + 2] simultaneously. Rev. 4.00, 03/04, page 552 of 660 23.2 Register Bits The following are the bit-name of each registers. The 16-bit and 32-bit registers are shown by two and four 8-bit rows, respectively. Register SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR SCFRDR2 -- -- -- -- SDIR SINV -- SMIF SCIF TDRE RDRF ORER FER/ERS PER TEND MPB MPBT TIE RIE TE RE MPIE TEIE CKE1 CKE0 Bit 7 C/A Bit 6 CHR Bit 5 PE Bit 4 O/E Bit 3 STOP Bit 2 MP Bit 1 CKS1 Bit 0 CKS0 Module SCI SCFTDR2 SCSMR2 SCSCR2 SCSSR2 SCBRR2 SCFCR2 SCFDR2 -- TIE ER CHR RIE TEND PE TE TDFE O/E RE BRK STOP -- FER -- -- PER CKS1 CKE1 RDF CKS0 CKE0 DR RTRG1 RTRG0 TTRG1 TTRG0 MCE TFRST RFRST LOOP TOCR TSTR TCOR_0 -- -- -- -- -- -- -- -- -- -- -- STR2 -- STR1 TCOE STR0 TMU TCNT_0 TCR_0 -- -- -- -- -- UNIE -- CKEG1 -- CKEG0 -- TPSC2 -- TPSC1 UNF TPSC0 Rev. 4.00, 03/04, page 553 of 660 Register TCOR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module TMU TCNT_1 TCR_1 -- -- -- -- -- UNIE -- CKEG1 -- CKEG0 -- TPSC2 -- TPSC1 UNF TPSC0 TCOR_2 TCNT_2 TCR_2 -- ICPE1 -- ICPE0 -- UNIE -- CKEG1 -- CKEG0 -- TPSC2 ICPF TPSC1 UNF TPSC0 TCPR_2 R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT -- -- -- -- -- -- -- 1 Hz 10 sec 10 min -- -- -- -- 2 Hz 4 Hz 8 Hz 1 sec 1 min 16 Hz 32 Hz 64 Hz RTC 10 hours -- 10 days -- -- 1 hour -- 1 day 10 months 1 month day of week Rev. 4.00, 03/04, page 554 of 660 Register RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 ICR0 Bit 7 10 years ENB ENB ENB ENB ENB ENB CF PEF NML -- Bit 6 Bit 5 Bit 4 Bit 3 1 year Bit 2 Bit 1 Bit 0 Module RTC 10 sec 10 min -- -- -- -- -- PES2 -- -- 10 hours -- 10 days -- -- PES1 -- -- -- 1 sec 1 min 1 hour -- 1 day 10 months 1 month CIE PES0 -- -- AIE -- -- RESET -- -- AF START NMIE -- INTC day of week RTCEN ADJ -- -- TMU1 RTC REF -- -- -- -- IPRA TMU0 TMU2 IPRB WDT SCI -- -- BCR1 PULA PULD HIZMEM HIZCNT ENDIAN A0BST1 A0BST0 A5BST1 BSC A6PCM A4SZ0 -- A4IW0 A0IW0 A4W1 A0W0 TRAS0 A5BST0 A6BST1 A6BST0 DRAMTP2 DRAMTP1 DRAMTP0 A5PCM BCR2 -- A3SZ1 WCR1 -- A3SZ0 A6SZ1 A2SZ1 A6IW1 A2IW1 A6W0 A3W0 RCD1 AMX2 -- A6SZ0 A2SZ0 A6IW0 A2IW0 A5W2 A2W1 RCD0 AMX1 -- A5SZ1 -- A5IW1 -- A5W1 A2W0 TRWL1 AMX0 A5SZ0 -- A5IW0 -- A5W0 A0W2 TRWL0 RFSH A4SZ1 -- A4IW1 A0IW1 A4W2 A0W1 TRAS1 WAITSEL -- A3IW1 A3IW0 A6W1 A3W1 TPC0 AMX3 A5W3 WCR2 A6W2 A4W0 MCR TPC1 RASD RMODE -- PCR A6W3 A5TED2 A6TED2 A5THE2 A6THE2 A5THE1 A5THE0 A6THE1 A6THE0 -- CKS0 -- -- OVF -- -- OVIE -- -- LMTS -- A5TED1 A5TED0 A6TED1 A6TED0 RTCSR -- CMF RTCNT -- -- CMIE -- -- CKS2 -- -- CKS1 -- Rev. 4.00, 03/04, page 555 of 660 Register RTCOR Bit 7 -- Bit 6 -- Bit 5 -- Bit 4 -- Bit 3 -- Bit 2 -- Bit 1 -- Bit 0 -- Module BSC RFCR -- -- -- -- -- -- -- -- SDMR FRQCR STC2 -- STBCR STBCR2 WTCNT WTCSR BDRB TME BDB31 BDB23 BDB15 BDB7 BDMRB WT/IT BDB30 BDB22 BDB14 BDB6 RSTS BDB29 BDB21 BDB13 BDB5 WOVF BDB28 BDB20 BDB12 BDB4 IOVF BDB27 BDB19 BDB11 BDB3 CKS2 BDB26 BDB18 BDB10 BDB2 CKS1 BDB25 BDB17 BDB9 BDB1 CKS0 BDB24 BDB16 BDB8 BDB0 UBC STBY -- IFC2 -- -- PFC2 STC1 -- -- STC0 -- IFC1 -- IFC0 MSTP2 MSTP5 -- PFC1 MSTP1 MSTP4 -- PFC0 MSTP0 -- CPG STBYTL -- MSTP7 MSTP6 MDCHG MSTP8 BDMB31 BDMB30 BDMB29 BDMB28 BDMB27 BDMB26 BDMB25 BDMB24 BDMB23 BDMB22 BDMB21 BDMB20 BDMB19 BDMB18 BDMB17 BDMB16 BDMB15 BDMB14 BDMB13 BDMB12 BDMB11 BDMB10 BDMB9 BDMB7 BDMB6 BDMB5 -- -- -- BASMA BDMB4 -- BASMB BDMB3 -- -- BDMB2 -- -- PCBA -- BAB26 BAB18 BAB10 BAB2 BDMB1 -- -- -- -- BAB25 BAB17 BAB9 BAB1 BDMB8 BDMB0 -- -- -- ETBE BAB24 BAB16 BAB8 BAB0 BRCR -- -- SCMFCA SCMFCB SCMFDA SCMFDB PCTE DBEB BARB BAB31 BAB23 BAB15 BAB7 BAMRB PCBB BAB30 BAB22 BAB14 BAB6 -- BAB29 BAB21 BAB13 BAB5 -- BAB28 BAB20 BAB12 BAB4 SEQ BAB27 BAB19 BAB11 BAB3 BAMB31 BAMB30 BAMB29 BAMB28 BAMB27 BAMB26 BAMB25 BAMB24 BAMB23 BAMB22 BAMB21 BAMB20 BAMB19 BAMB18 BAMB17 BAMB16 BAMB15 BAMB14 BAMB13 BAMB12 BAMB11 BAMB10 BAMB9 BAMB7 BAMB6 BAMB5 BAMB4 BAMB3 BAMB2 BAMB1 BAMB8 BAMB0 Rev. 4.00, 03/04, page 556 of 660 Register BBRB Bit 7 -- CDB1 Bit 6 -- CDB0 BAA30 BAA22 BAA14 BAA6 Bit 5 -- IDB1 BAA29 BAA21 BAA13 BAA5 Bit 4 -- IDB0 BAA28 BAA20 BAA12 BAA4 Bit 3 -- RWB1 BAA27 BAA19 BAA11 BAA3 Bit 2 -- RWB0 BAA26 BAA18 BAA10 BAA2 Bit 1 -- SZB1 BAA25 BAA17 BAA9 BAA1 Bit 0 -- SZB0 BAA24 BAA16 BAA8 BAA0 Module UBC BARA BAA31 BAA23 BAA15 BAA7 BAMRA BAMA31 BAMA30 BAMA29 BAMA28 BAMA27 BAMA26 BAMA25 BAMA24 BAMA23 BAMA22 BAMA21 BAMA20 BAMA19 BAMA18 BAMA17 BAMA16 BAMA15 BAMA14 BAMA13 BAMA12 BAMA11 BAMA10 BAMA9 BAMA7 BAMA6 BAMA5 -- CDA0 -- -- IDA1 -- BAMA4 -- IDA0 -- BAMA3 -- RWA1 BAMA2 -- RWA0 BAMA1 -- SZA1 BAMA8 BAMA0 -- SZA0 BBRA -- CDA1 BETR -- BRSR SVF BSA23 BSA15 BSA7 PID2 BSA22 BSA14 BSA6 -- BDA22 BDA14 BDA6 BASA6 BASB6 -- -- -- PID1 BSA21 BSA13 BSA5 -- BDA21 BDA13 BDA5 BASA5 BASB5 -- -- -- PID0 BSA20 BSA12 BSA4 -- BDA20 BDA12 BDA4 BASA4 BASB4 -- -- -- BSA27 BSA19 BSA11 BSA3 BDA27 BDA19 BDA11 BDA3 BASA3 BASB3 -- -- -- BSA26 BSA18 BSA10 BSA2 BDA26 BDA18 BDA10 BDA2 BASA2 BASB2 -- -- -- BSA25 BSA17 BSA9 BSA1 BDA25 BDA17 BDA9 BDA1 BASA1 BASB1 -- -- imm -- BSA24 BSA16 BSA8 BSA0 BDA24 BDA16 BDA8 BDA0 BASA0 BASB0 -- -- CCN BRDR DVF BDA23 BDA15 BDA7 BASRA BASRB TRA BASA7 BASB7 -- -- -- -- -- -- EXPEVT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Rev. 4.00, 03/04, page 557 of 660 Register INTEVT Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 -- -- -- Bit 3 -- -- Bit 2 -- -- Bit 1 -- -- Bit 0 -- -- Module CCN MMUCR -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RC -- -- -- -- -- -- -- -- -- -- -- RC -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- CF -- -- -- -- -- -- -- TF -- -- -- CB -- -- -- -- -- -- -- IX -- -- -- WT -- -- -- -- SV AT -- -- -- CE -- -- CCR -- -- -- -- CCR2 -- -- -- -- W3LOAD W3LOCK W2LOAD W2LOCK PTEH VPN -- ASID PTEL PPN -- -- -- TTB PR PR SZ C D SH V -- TEA Rev. 4.00, 03/04, page 558 of 660 Register INTEVT2 Bit 7 -- -- -- Bit 6 -- -- -- Bit 5 -- -- -- Bit 4 -- -- -- Bit 3 -- -- Bit 2 -- -- Bit 1 -- -- Bit 0 -- -- Module INTC IRR0 IRR1 IRR2 ICR1 -- -- -- MAI IRQ31S -- -- -- IRQLVL IRQ30S IRQ5R -- -- BLMSK IRQ21S IRQ4R -- ADIR -- IRQ20S IRQ3R DEI3R TXI2R IRQ51S IRQ11S IRQ2 IRQ0 IRQ2R DEI2R BRI2R IRQ50S IRQ10S IRQ1R DEI1R RXI2R IRQ41S IRQ01S IRQ0R DEI0R ERI2R IRQ40S IRQ00S IPRC IRQ3 IRQ1 IPRD -- IRQ5 -- -- -- -- IRQ4 -- A/D -- -- -- IPRE DMAC SCIF -- -- -- SAR_0 DMAC DAR_0 DMATCR_0 -- -- -- -- -- -- -- -- CHCR_0 -- -- DM1 -- -- -- DM0 DS -- -- SM1 TM -- DI SM0 TS1 -- RO RS3 TS0 -- RL RS2 IE -- AM RS1 TE -- AL RS0 DE Rev. 4.00, 03/04, page 559 of 660 Register SAR_1 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMAC DAR_1 DMATCR_1 -- -- -- -- -- -- -- -- CHCR_1 -- -- DM1 -- -- -- DM0 DS -- -- SM1 TM -- DI SM0 TS1 -- RO RS3 TS0 -- RL RS2 IE -- AM RS1 TE -- AL RS0 DE SAR_2 DAR_2 DMATCR_2 -- -- -- -- -- -- -- -- CHCR_2 -- -- DM1 -- -- -- DM0 DS -- -- SM1 TM -- DI SM0 TS1 -- RO RS3 TS0 -- RL RS2 IE -- AM RS1 TE -- AL RS0 DE Rev. 4.00, 03/04, page 560 of 660 Register SAR_3 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module DMAC DAR_3 DMATCR_3 -- -- -- -- -- -- -- -- CHCR_3 -- -- DM1 -- -- -- DM0 DS -- -- -- -- -- -- -- -- SM1 TM -- -- -- -- -- -- -- DI SM0 TS1 -- -- -- -- -- -- -- RO RS3 TS0 -- -- -- -- -- -- -- RL RS2 IE -- AE -- -- -- -- -- AM RS1 TE PR1 NMIF -- -- -- CKS1 -- AL RS0 DE PR0 DME -- STR0 -- CKS0 CMT DMAOR -- -- CMSTR -- -- CMCSR -- CMF CMCNT CMCOR Rev. 4.00, 03/04, page 561 of 660 Register ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR DADR0 DADR1 DACR PACR Bit 7 AD9 AD1 AD9 AD1 AD9 AD1 AD9 AD1 ADF TRGE Bit 6 AD8 AD0 AD8 AD0 AD8 AD0 AD8 AD0 ADIE TRGE0 Bit 5 AD7 -- AD7 -- AD7 -- AD7 -- ADST SCN Bit 4 AD6 -- AD6 -- AD6 -- AD6 -- MULTI -- Bit 3 AD5 -- AD5 -- AD5 -- AD5 -- CKS -- Bit 2 AD4 -- AD4 -- AD4 -- AD4 -- CH2 -- Bit 1 AD3 -- AD3 -- AD3 -- AD3 -- CH1 -- Bit 0 AD2 -- AD2 -- AD2 -- AD2 -- CH0 -- Module A/D D/A DAOE1 DAOE0 DAE -- -- -- -- -- PA7MD1 PA7MD0 PA6MD1 PA6MD0 PA5MD1 PA5MD0 PA4MD1 PA4MD0 PORT PA3MD1 PA3MD0 PA2MD1 PA2MD0 PA1MD1 PA1MD0 PA0MD1 PA0MD0 PBCR PB7MD1 PB7MD0 PB6MD1 PB6MD0 PB5MD1 PB5MD0 PB4MD1 PB4MD0 PB3MD1 PB3MD0 PB2MD1 PB2MD0 PB1MD1 PB1MD0 PB0MD1 PB0MD0 PCDR PC7MD1 PC7MD0 PC6MD1 PC6MD0 PC5MD1 PC5MD0 PC4MD1 PC4MD0 PC3MD1 PC3MD0 PC2MD1 PC2MD0 PC1MD1 PC1MD0 PC0MD1 PC0MD0 PDCR PD7MD1 PD7MD0 PD6MD1 PD6MD0 PD5MD1 PD5MD0 PD4MD1 PD4MD0 PD3MD1 PD3MD0 PD2MD1 PD2D0 PD1MD1 PD1MD0 PD0MD1 PD0MD0 PECR PE7MD1 PE7MD0 PE6MD1 PE6MD0 PE5MD1 PE5MD0 PE4MD1 PE4MD0 PE3MD1 PE3MD0 PE2MD1 PE2MD0 PE1MD1 PE1MD0 PE0MD1 PE0MD0 PFCR -- -- PF6MD1 PF6MD0 PF5MD1 PF5MD0 PF4MD1 PF4MD0 PF3MD1 PF3MD0 PF2MD1 PF2MD0 PF1MD1 PF1MD0 PF0MD1 PF0MD0 PGCR -- -- -- -- PG5MD1 PG5MD0 PG4MD1 PG4MD0 PG3MD1 PG3MD0 PG2MD1 PG2MD0 PG1MD1 PG1MD0 PG0MD1 PG0MD0 PHCR -- -- PH6MD1 PH6MD0 PH5MD1 PH5MD0 PH4MD1 PH4MD0 PH3MD1 PH3MD0 PH2MD1 PH2MD0 PH1MD1 PH1MD0 PH0MD1 PH0MD0 PJCR -- -- -- -- -- -- -- -- PJ3MD1 PJ3MD0 PJ2MD1 PJ2MD0 PJ1MD1 PJ1MD0 PJ0MD1 PJ0MD0 SCPCR -- -- -- -- SCP5MD1 SCP5MD0 SCP4MD1 SCP4MD0 SCP3MD1 SCP3MD0 SCP2MD1 SCP2MD0 SCP1MD1 SCP1MD0 SCP0MD1 SCP0MD0 Rev. 4.00, 03/04, page 562 of 660 Register PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR SCPDR SDIR Bit 7 PA7DT PB7DT PC7DT PD7DT PE7DT -- -- -- -- -- TI3 -- Bit 6 PA6DT PB6DT PC6DT PD6DT PE6DT PF6DT -- PH6DT -- -- TI2 -- Bit 5 PA5DT PB5DT PC5DT PD5DT PE5DT PF5DT PG5DT PH5DT -- Bit 4 PA4DT PB4DT PC4DT PD4DT PE4DT PF4DT PG4DT PH4DT -- Bit 3 PA3DT PB3DT PC3DT PD3DT PE3DT PF3DT PG3DT PH3DT PJ3DT Bit 2 PA2DT PB2DT PC2DT PD2DT PE2DT PF2DT PG2DT PH2DT PJ2DT Bit 1 PA1DT PB1DT PC1DT PD1DT PE1DT PF1DT PG1DT PH1DT PJ1DT Bit 0 PA0DT PB0DT PC0DT PD0DT PE0DT PF0DT PG0DT PH0DT PJ0DT Module PORT SCP5DT SCP4DT SCP3DT SCP2DT SCP1DT SCP0DT TI1 -- TI0 -- -- -- -- -- -- -- -- -- UDI Rev. 4.00, 03/04, page 563 of 660 23.3 Register Name PTEH PTEL TTB TEA MMUCR BASRA BASRB CCR CCR2 TRA EXPEVT INTEVT BARA BAMRA BBRA BARB BAMRB BBRB BDRB BDMRB BRCR BETR BRSR BRDR FRQCR STBCR STBCR2 WTCNT WTCSR Register States in Processing Mode Power-on Reset Undefined Undefined Undefined Undefined Initialized* Undefined Undefined Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized*1 Initialized*1 Initialized* Initialized Initialized Initialized* Initialized* 2 2 2 1 Manual Reset Undefined Undefined Undefined Undefined Initialized* Undefined Undefined Initialized Initialized Undefined Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized*1 Initialized*1 Held Held Held Held Held 1 Hardware Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module CCN UBC CPG Rev. 4.00, 03/04, page 564 of 660 Register Name BCR1 BCR2 WCR1 WCR2 MCR PCR RTCSR RTCNT RTCOR RFCR R64CNT RSECCNT RMINCNT RHRCNT RWKCNT RDAYCNT RMONCNT RYRCNT RSECAR RMINAR RHRAR RWKAR RDAYAR RMONAR RCR1 RCR2 ICR0 IPRA IPRB TOCR TSTR TCOR_0 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held* Held* Held* Held* Held* Held* 3 3 3 3 3 3 Manual Reset Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held* Held* Held* Held* Held* Held* 3 3 3 3 3 3 Hardware Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module BSC RTC Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized INTC TMU Rev. 4.00, 03/04, page 565 of 660 Register Name TCNT_0 TCR_0 TCOR_1 TCNT_1 TCR_1 TCOR_2 TCNT_2 TCR_2 TCPR_2 SCSMR SCBRR SCSCR SCTDR SCSSR SCRDR SCSCMR INTEVT2 IRR0 IRR1 IRR2 ICR1 IPRC IPRD IPRE SAR_0 DAR_0 DMATCR_0 CHCR_0 SAR_1 DAR_1 DMATCR_1 CHCR_1 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Undefined Initialized Undefined Undefined Undefined Initialized Manual Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Undefined Undefined Initialized Undefined Undefined Undefined Initialized Hardware Standby Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Software Standby Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module Standby Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module TMU SCI INTC DMAC Rev. 4.00, 03/04, page 566 of 660 Register Name SAR_2 DAR_2 DMATCR_2 CHCR_2 SAR_3 DAR_3 DMATCR_3 CHCR_3 DMAOR CMSTR CMCSR CMCNT CMCOR ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL ADCSR ADCR DADR0 DADR1 DACR PACR PBCR PCCR PDCR PECR PFCR Power-on Reset Undefined Undefined Undefined Initialized Undefined Undefined Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Manual Reset Undefined Undefined Undefined Initialized Undefined Undefined Undefined Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Hardware Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Software Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Module Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Held Held Held Held Held Held Held Held Held Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module DMAC CMT ADC DAC PORT Rev. 4.00, 03/04, page 567 of 660 Register Name PGCR PHCR PJCR SCPCR PADR PBDR PCDR PDDR PEDR PFDR PGDR PHDR PJDR SCPDR SCSMR2 SCBRR2 SCSCR2 SCFTDR2 SCSSR2 SCFRDR2 SCFCR2 SCFDR2 SDIR* 4 Power-on Reset Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Held Manual Reset Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Held Hardware Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Held Software Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Held Module Standby Held Held Held Held Held Held Held Held Held Held Held Held Held Held Initialized Initialized Initialized Undefined Initialized Undefined Initialized Initialized Held Sleep Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Held Module PORT SCIF UDI Notes: 1. 2. 3. 4. Some bits are not initialized. These bits are not initialized at a power-on reset by the WDT. Some bits are initialized. Initialized on asserting state of TRST or on Test-Logic-Reset state of TAP. Rev. 4.00, 03/04, page 568 of 660 Section 24 Electrical Characteristics 24.1 Absolute Maximum Ratings Table 24.1 shows the absolute maximum ratings. Table 24.1 Absolute Maximum Ratings Item Power supply voltage (I/O) Symbol VccQ Rating -0.3 to 4.2 -0.3 to 2.5 Unit V V Power supply voltage (internal) Vcc Vcc - PLL1 Vcc - PLL2 Vcc - RTC Input voltage (except port J) Input voltage (port J) Analog power-supply voltage Analog input voltage Operating temperature Storage temperature Vin Vin AVcc VAN Topr Tstr -0.3 to VccQ + 0.3 -0.3 to AVcc + 0.3 -0.3 to 4.6 -0.3 to AVcc + 0.3 -20 to 75 -55 to 125 V V V V C C Cautions: * Operating the chip in excess of the absolute maximum rating may result in permanent damage. * Order of turning on or off 1.9 V power (Vcc, Vcc-PLL1, Vcc-PLL2, Vcc-RTC) and 3.3 V power (VccQ, AVcc): 1. The voltage of 1.9 V power should not be higher than that of 3.3 V power. The period when only 3.3 V power is turned on should be less than 1 ms. This period should be as short as possible. 2. Until voltage is applied to all power supplies, a high level is input at the CA pin, and a low level is input at the RESETP pin, and CKIO clocks are equal to or below 4 clocks, internal circuits remain unsettled, and so pin states are also undefined. The system design must ensure that these undefined states do not cause erroneous system operation. When the CA pin is at a low level, the low level of the RESETP pin is not accepted. Rev. 4.00, 03/04, page 569 of 660 Waveforms at power-on are shown in the following figure. (Max. 1ms) 3.3 V 3.3 V power 1.9 V 1.9 V power 4-5-62 Pin states undefined All other pins* Pin states undefined Power-on reset state Note: * Except power/GND, clock related, and analog pins Power-On Sequence Rev. 4.00, 03/04, page 570 of 660 24.2 DC Characteristics Table 24.2 lists DC characteristics. Table 24.2 DC Characteristics (Ta = -20 to 75C) Item Power supply voltage Symbol VccQ Vcc, Vcc-PLL1, Vcc-PLL2, Vcc-RTC Current Normal dissipation operation In sleep mode* 1 Min 3.0 1.75 Typ 3.3 1.90 Max 3.6 2.05 Unit V Measurement Conditions Icc* 2 3 -- -- -- 3 250 20 15 10 40 10 35 10 -- -- 400 40 30 20 125 25 110 25 15 mA Vcc = 1.9 V, I = 133 MHz VccQ = 3.3 V, B = 33 MHz B = 33 MHz VccQ = 3.3 V, Vcc = 1.9 V IccQ* Icc* 2 IccQ* Icc* 2 -- -- In standby mode A IccQ* Icc* 2 3 -- -- Ta = 25C (RTC on) VccQ = 3.3 V, Vcc = 1.9 V Ta = 25C (RTC off)* VccQ = 3.3 V, Vcc = 1.9 V Vcc-RTC = 1.9 V 5 IccQ* Input high RESETP, voltage RESETM, NMI, IRQ5 to IRQ0, MD5 to MD0, ASEMD0, CA, TRST, ADTRG, EXTAL, CKIO Port J Other input pins 3 4 -- -- VccQ x 0.9 RTC current Icc-RTC* VIH VccQ + V 0.3 2.0 2.0 -- -- AVcc + 0.3 VccQ + 0.3 Rev. 4.00, 03/04, page 571 of 660 Item Input low RESETP, RESETM, voltage NMI, IRQ5 to IRQ0, MD5 to MD0, ASEMD0, CA, TRST, ADTRG, EXTAL, CKIO Port J Other input pins Symbol Min VIL -0.3 Typ -- Max Unit Measurement Conditions VccQ x V 0.1 -0.3 -0.3 -- -- -- -- -- -- AVcc x 0.2 VccQ x 0.2 1.0 1.0 A A Vin = 0.5 to VccQ-0.5 V Vin = 0.5 to VccQ-0.5 V Input leak All input pins I Iin I current ThreeI/O, all state leak output pins current (off condition) Output high voltage All output pins I Isti I VOH 2.4 2.0 -- -- -- 60 -- 3.3 -- -- 0.55 120 10 3.6 V VccQ = 3.0 V, IOH = -200 A VccQ = 3.0 V, IOH = -2 mA VccQ = 3.6 V, IOL = 1.6 mA Output low All output voltage pins Pull-up Port pin resistance Pin capacity Analog powersupply voltage All pins VOL Ppull C AVcc -- 30 -- 3.0 k PF V Rev. 4.00, 03/04, page 572 of 660 Item Analog powersupply current Symbol During A/D AIcc conversion During A/D and D/A conversion Idle Min -- -- Typ 0.8 2.4 Max 2 6 Unit mA mA Measurement Conditions -- 0.01 5.0 A Ta = 25C Notes: Regardless of whether PLL or RTC is used, connect Vcc - PLL and Vcc - RTC to Vcc, and Vss - PLL and Vss - RTC to Vss. AVcc must be under condition of VccQ - 0.3 V AVcc VccQ + 0.3 V. If the A/D and D/A converters are not used, do not leave the AVcc and AVss pins open. Connect AVcc to VccQ, and connect AVss to VssQ. Current dissipation values shown are the values at which all output pins are without load under conditions of VIHmin = VccQ - 0.5 V, VILmax = 0.5 V. 1. No external bus cycles except refresh cycles. 2. Total current of Vcc, Vcc - PLL1, and Vcc - PLL2 3. Current of VccQ 4. Current of Vcc - RTC 5. Only in software standby mode Table 24.3 Permitted Output Current Values (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C) Item Output low-level permissible current (per pin) Output low-level permissible current (total) Output high-level permissible current (per pin) Output high-level permissible current (total) Symbol IOL IOL -IOH (-IOH) Min -- -- -- -- Typ -- -- -- -- Max 2.0 120 2.0 40 Unit mA mA mA mA Caution: To ensure LSI reliability, do not exceed the value for output current given in Table 24.3. Rev. 4.00, 03/04, page 573 of 660 24.3 AC Characteristics In general, inputting for this LSI should be clock synchronous. Keep the setup and hold times for each input signal unless otherwise specified. Operating conditons are as follows: VccQ = 3.3 0.3V Vcc = 1.9 0.15V Avcc = 3.3 0.3V Ta = -20 to 75C Table 24.4 Operating Frequency Range Item Operating frequency CPU, cache, TLB External bus Peripheral module Symbol f Min 25 25 6.25 Typ -- -- -- Max 133.34 66.67 33.34 Unit MHz Remarks 24.3.1 Clock Timing Table 24.5 Clock Timing Item EXTAL clock input frequency (clock mode 0) EXTAL clock input cycle time (clock mode 0) EXTAL clock input frequency (clock mode 1) EXTAL clock input cycle time (clock mode 1) EXTAL clock input low pulse width EXTAL clock input high pulse width EXTAL clock input rise time EXTAL clock input fall time Symbol fEX tEXcyc fEX tEXcyc tEXL tEXH tEXR tEXF Min 25 15 6.25 60 1.5 1.5 -- -- Max Unit Figure 24.1 66.67 MHz 40 ns 16.67 MHz 160 -- -- 6 6 ns ns ns ns ns Rev. 4.00, 03/04, page 574 of 660 Item CKIO clock input frequency CKIO clock input cycle time CKIO clock input low pulse width CKIO clock input high pulse width CKIO clock input rise time CKIO clock input fall time CKIO clock output frequency CKIO clock output cycle time CKIO clock output low pulse width CKIO clock output high pulse width CKIO clock output rise time CKIO clock output fall time Power-on oscillation settling time Symbol fCKI tCKIcyc tCKIL tCKIH tCKIR tCKIF fOP tcyc tCKOL tCKOH tCKOR tCKOF tOSC1 Min 25 15 1.5 1.5 -- -- 25 15 3 3 -- -- 10 20 0 20 20 10 10 11 100 100 100 Max Unit Figure 24.2 66.67 MHz 40 -- -- 6 6 ns ns ns ns ns 66.67 MHz 40 -- -- 5 5 -- -- -- -- -- -- -- -- -- -- -- ns ns ns ns ns ms ns ns tcyc tcyc ms ms ms s s s 24.3 24.4 24.4, 24.5 RESETP setup time (at the power-on or tRESPS at the release from standby mode) RESETM setup time (at the release from tRESMS standby mode) RESETP assert time (at the power-on or tRESPW at the release from standby mode) RESETM assert time (at the release from standby mode) tRESMW Standby return oscillation settling time 1 tOSC2 Standby return oscillation settling time 2 tOSC3 Standby return oscillation settling time 3 tOSC4 PLL synchronization settling time 1 (at the release from standby mode) tPLL1 24.5 24.6 24.7 24.8, 24.9 24.10 24.10 PLL synchronization settling time 2 tPLL2 (at the modification of multiplication rate) IRQ/IRL interrupt determination time (RTC is used in the standby mode) tIRLSTB Rev. 4.00, 03/04, page 575 of 660 tEXcyc tEXH EXTAL* (input) 1/2 VCCQ VIH VIH VIL tEXF VIL VIH 1/2 VCCQ tEXR tEXL Note: * The clock input from the EXTAL pin. Figure 24.1 EXTAL Clock Input Timing tCKIcyc tCKIH CKIO (input) 1/2 VCCQ VIH VIH VIL tCKIF VIH VIL 1/2 VCCQ tCKIR tCKIL Figure 24.2 CKIO Clock Input Timing tcyc tCKOH CKIO (output) 1/2VCCQ tCKOL VIH VOH VOL tCKOF VOH VOL 1/2VCCQ tCKOR Figure 24.3 CKIO Clock Output Timing Rev. 4.00, 03/04, page 576 of 660 Stable oscillation CKIO, internal clock VCC VCC min tOSC1 tRESPW tRESPS Note: Oscillation settling time in clock mode 2. Oscillation settling time becomes tOSC1 = tPLL1 (min. 100 s) except in clock mode 2. Figure 24.4 Power-On Oscillation Settling Time Standby CKIO, internal clock tRESPW/MW tOSC2 tRESPS/MS Stable oscillation RESETP, RESETM Note: Oscillation settling time in the Clock-mode-2 and Oscillation-halt-mode Figure 24.5 Oscillation Settling Time at Standby Return (Return by Reset) Standby CKIO, internal clock tOSC3 Stable oscillation NMI Note: Oscillation settling time in the Clock-mode-2 and Oscillation-halt-mode Figure 24.6 Oscillation Settling Time at Standby Return (Return by NMI) Rev. 4.00, 03/04, page 577 of 660 Standby CKIO, internal clock tOSC4 Stable oscillation IRQ4 to IRQ0 Note: Oscillation settling time in the Clock-mode-2 and Oscillation-halt-mode Figure 24.7 Oscillation Settling Time at Standby Return (Return by IRQ or IRL) Reset or NMI interrupt request Stable input clock EXTAL input or CKIO input PLL synchronization PLL output, CKIO output tPLL1 PLL synchronization Stable input clock Internal clock STATUS 0 STATUS 1 Normal Standby Normal Note: Oscillation settling time in the Clock-mode-0, 1, 7 and Oscillation-halt-mode Figure 24.8 PLL Synchronization Settling Time by Reset or NMI at the returning from Standby mode (Return by Reset or NMI) Rev. 4.00, 03/04, page 578 of 660 IRQ4 to IRQ0/ Stable input clock EXTAL input or CKIO input PLL synchronization PLL output, CKIO output to interrupt request Stable input clock tIRLSTB tPLL1 PLL synchronization Internal clock STATUS 0 STATUS 1 Normal Standby Normal Note: Oscillation settling time in the Clock-mode-0, 1, 7 and Oscillation-halt-mode Figure 24.9 PLL Synchronization Settling Time at the returning from Standby mode (Return by IRQ/IRL Interrupt) Multiplication rate modified EXTAL input*1 tPLL2 PLL output, CKIO output*2 Internal clock Notes: 1. 2. CKIO input in clock mode 7 PLL output in clock mode 7 Figure 24.10 PLL Synchronization Settling Time when Frequency Multiplication Rate Modified Rev. 4.00, 03/04, page 579 of 660 24.3.2 Control Signal Timing Table 24.6 Control Signal Timing Item RESETP pulse width RESETP setup time* RESETP hold time RESETM pulse width RESETM setup time RESETM hold time BREQ setup time BREQ hold time NMI setup time * NMI hold time IRQ5 to IRQ0 setup time * IRQ5 to IRQ0 hold time IRQOUT delay time BACK delay time STATUS1, STATUS0 delay time Bus tri-state delay time 1 Bus tri-state delay time 2 Bus buffer-on time 1 Bus buffer-on time 2 1 1 1 Symbol tRESPW tRESPS tRESPH tRESMW tRESMS tRESMH tBREQS tBREQH tNMIS tNMIH tIRQS tIRQH tIRQOD tBACKD tSTD tBOFF1 tBOFF2 tBON1 tBON2 Min 20* 20 2 12* 6 34 6 4 10 4 10 4 -- -- -- 0 0 0 0 4 3 Max -- -- -- -- -- -- -- -- -- -- -- -- 10 10 10 15 15 15 15 Unit tcyc ns ns tcyc ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 24.11, 24.12 24.14 24.12, 24.13 24.14, 24.15 Notes: 1. RESETP, NMI, and IRQ5 to IRQ0 are asynchronous. Changes are detected at the clock fall when the setup shown is used. When the setup cannot be used, detection can be delayed until the next clock falls. 2. The upper limit of the external bus clock is 66 MHz. 3. In the standby mode, when XTAL oscillation continues, tRESPn = tOSC1 (100s), when XTAL oscillation stops, tRESPW = tOSC2 (10 ms). In the sleep mode, tRESPW = tPLL1 (100 s). When the clock multiplication ratio is changed, tRESPW = tPLL1 (100 s). 4. In the standby mode, tRESMW = tOSC2 (10 ms). In the sleep mode, RESETM must be kept low until STATUS (0-1) changes to reset (HH). When the clock multiplication ratio is changed, RESETM must be kept low until STATUS (0-1) changes to reset (HH). Rev. 4.00, 03/04, page 580 of 660 CKIO tRESPS/MS tRESPW/MW tRESPS/MS RESETP, RESETM Figure 24.11 Reset Input Timing CKIO tRESPH/MH tRESPS/MS VIH VIL tNMIH tNMIS VIH NMI VIL tIRQH tIRQS VIH IRQ5 to IRQ0 VIL RESETP, RESETM Figure 24.12 Interrupt Signal Input Timing CKIO tIRQOD tIRQOD Figure 24.13 IRQOUT Timing Rev. 4.00, 03/04, page 581 of 660 CKIO t BREQH t BREQS t BREQH t BREQS BREQ t BACKD t BACKD BACK t BOFF2 t BON2 RD, RD/WR, CAS, CAS, CSn, WEn, BS A25 to A0, D31 to D0 t BOFF1 t BON1 Figure 24.14 Bus Release Timing Normal mode Standby mode Normal mode CKIO tSTD STATUS 0, STATUS 1 tBOFF2 tBON2 tSTD RD, RD/WR, RAS, CAS, CSn, WEn, BS A25 to A0, D31 to D0 tBOFF1 tBON1 Figure 24.15 Pin Drive Timing at Standby Rev. 4.00, 03/04, page 582 of 660 24.3.3 AC Bus Timing Table 24.7 Bus Timing (Clock Modes 0/1/2/7) Item Address delay time Address setup time Address hold time BS delay time CS delay time 1 CS delay time 2 CS delay time 3 Read/write delay time Read/write hold time Read strobe delay time Read data setup time 1 Read data setup time 2 Read data hold time 1 Read data hold time 2 Write enable delay time Write data delay time 1 Write data delay time 2 Write data hold time 1 Write data hold time 2 Write data hold time 3 Write data hold time 4 WAIT setup time WAIT hold time RAS delay time CAS delay time DQM delay time Symbol tAD tAS tAH tBSD tCSD1 tCSD2 tCSD3 tRWD tRWH tRSD tRDS1 tRDS2 tRDH1 tRDH2 tWED tWDD1 tWDD2 tWDH1 tWDH2 tWDH3 tWDH4 tWTS tWTH tRASD tCASD tDQMD Min 1.5 0 4 -- -- -- 1.5 1.5 0 -- 6 5 0 2 -- -- 1.5 1.5 1.5 2 2 5 0 1.5 1.5 1.5 Max 12 -- -- 10 10 10 10 10 -- 10 -- -- -- -- 10 12 12 -- -- -- -- -- -- 10 10 10 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Figure 24.16 to 24.36, 24.39 to 24.46 24.16 to 24.18 24.16 to 24.21 24.16 to 24.36, 24.40 to 24.46 24.16 to 24.21, 24.40 to 24.46 24.16 to 24.21 24.24 to 24.39 24.16 to 24.46 24.16 to 24.21 24.16 to 24.21 24.40 to 24.43 24.16 to 24.21, 24.40 to 24.46 24.22 to 24.25, 24.30 to 24.33 24.16 to 24.21, 24.40 to 24.46 24.22 to 24.25, 24.30 to 24.33 24.16 to 22.18, 24.40 to 24.41 24.16 to 24.18, 24.40 to 24.41, 24.44 to 24.46 24.20 to 24.29 24.16 to 24.18, 24.40 to 24.41, 24.44 to 24.46 24.26 to 24.29 24.16 to 24.18 24.40 to 24.41, 24.44 to 24.46 24.17 to 24.21, 24.41, 24.43, 24.45, 24.46 24.17 to 24.21, 24.41, 24.43, 24.45, 24.46 24.22 to 24.39 24.22 to 24.39 24.22 to 24.36 Rev. 4.00, 03/04, page 583 of 660 Item CKE delay time ICIORD delay time ICIOWR delay time IOIS16 setup time IOIS16 hold time DACK delay time 1 DACK delay time 2 Symbol tCKED tICRSD tICWSD tIO16S tIO16H tDAKD1 tDAKD2 Min 1.5 -- -- 6 4 -- -- Max 10 10 10 -- -- 12 10 Unit ns ns ns ns ns ns ns Figure 24.38 24.44 to 24.46 24.44 to 24.46 24.45, 24.46 24.45, 24.46 24.16 to 24.36, 24.39 to 24.46 24.16 to 24.18, 24.20 to 24.21 Rev. 4.00, 03/04, page 584 of 660 24.3.4 Basic Timing T1 CKIO tAD A25 to A0 tAH tCSD1 tCSD2 tRWH tAS tAD T2 CSn tRWD RD/WR tRDH1 tRWD tAH tRSD (read) tRDS1 D31 to D0 (read) tAH tWED tWED tRWH tWDH3 tWDD1 D31 to D0 (write) tBSD tBSD tWDH1 tRSD tRWH RD tRDH1 WEn (write) BS tDAKD1 DACKn tDAKD2 Note: tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.16 Basic Bus Cycle (No Wait) Rev. 4.00, 03/04, page 585 of 660 T1 Tw T2 CKIO tAD A25 to A0 tAH tCSD1 tCSD2 tRWH tAS tAD tRWD RD/ tRDH1 tRWD tAH tRSD (read) tRDS1 D31 to D0 (read) tWED (write) tWDD1 D31 to D0 (write) tBSD tBSD tWED tAH tRWH tWDH3 tWDH1 tRSD tRWH tRDH1 tDAKD1 DACKn tWTS tWTH tDAKD2 Figure 24.17 Basic Bus Cycle (One Wait) Rev. 4.00, 03/04, page 586 of 660 T1 Tw Tw T2 CKIO tAD A25 to A0 tAH tCSD1 tCSD2 tRWH tAS tAD CSn tRWD RD/WR tAH tRSD tRSD tRWH tRDH1 tRWD RD (read) tRDS1 D31 to D0 (read) tAH tWED tWED tRWH tWDH3 tWDD1 D31 to D0 (write) tBSD tBSD tWDH1 tRDH1 WEn (write) BS tDAKD1 DACKn tWTS tWTH tWTS tWTH tDAKD2 WAIT Note: tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.18 Basic Bus Cycle (External Wait) Rev. 4.00, 03/04, page 587 of 660 24.3.5 Burst ROM Timing T1 TB2 TB1 TB2 TB1 TB2 TB1 T2 CKIO tAD A25 to A4 tAD A3 to A0 tAH tCSD1 tCSD2 tRWH tAD tAD CSn tRDH1 tRWD RD/WR tRSD tRSD tAH tRSD tRSD tRWD tAH tRWH RD tRDH1 tRDS D31 to D0 tBSD tBSD tBSD tBSD tRDS1 tRDH1 BS tDAKD1 DACKn tWTS tWTH tDAKD2 WAIT Note: In the write cycle, the basic bus cycle, the basic bus cycle is performed. tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.19 Burst ROM Bus Cycle (No Wait) Rev. 4.00, 03/04, page 588 of 660 T1 Tw Tw TB2 TB1 Tw TB2 T2 T2 CKIO tAD A25 to A4 tAD A3 to A0 tAH tCSD1 tCSD2 tRWH tAD CSn tRDH1 tRWD RD/WR tRSD tRSD tAH tRSD tRSD tRSD tRWD tAH tRWH RD tRDH1 tRDS1 D31 to D0 tBSD tBSD tBSD tBSD tRDS1 tRDH1 tRDH1 BS tDAKD1 DACKn tDAKD2 tWTS tWTH tWTS tWTH WAIT Note: In the write cycle, the basic bus cycle is performed. Figure 24.20 Burst ROM Bus Cycle (Two Waits) Rev. 4.00, 03/04, page 589 of 660 T1 CKIO tAD A25 to A4 Tw Tw TB2 TB1 TBw T2 tAD tAD A3 to A0 tAH tCSD1 tCSD2 tRWH CSn tRDH1 tRWD RD/WR tRSD tRSD1 tAH tRSD1 tAH tRSD tRWH tRWD RD tRDS1 D31 to D0 tBSD tBSD tRDH1 tRDS tRDH1 tBSD tBSD BS tDAKD1 DACKn tWTS tWTH tWTS tWTH tWTS tWTH tWTS tWTH tDAKD2 WAIT Note: In the write cycle, the basec bus cycle is performed. tRDH1: Stipulated from the faster negate timing of CSn or RD tAH: Stipulated from the slower negate timing of CSn, RD, or WEn Figure 24.21 Burst ROM Bus Cycle (External Wait) Rev. 4.00, 03/04, page 590 of 660 24.3.6 Synchronous DRAM Timing Tr CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 Row address Tc1 Tc2 (Tpc) tAD Row address Read A command tAD Row address Column address tCSD3 ;; ;; tAD tAD tAD tCSD3 tRWD tCASD tDQMD tRDS2 tRDH2 tBSD tBSD tRWD RD/ tRASD tRASD tCASD tDQMD DQMxx D31 to D0 CKE tDAKD1 DACKn (High) tDAKD1 Figure 24.22 Synchronous DRAM Read Bus Cycle (RCD = 0, CAS Latency = 1, TPC = 0) Rev. 4.00, 03/04, page 591 of 660 Tr CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 tCSD3 Trw Trw Tc1 Tcw Td1 (Tpc) (Tpc) Row address tAD Row address tAD Row address ;;; ;;; tAD tAD Read A command tAD Column address tCSD3 tRWD RD/ tRASD tRASD tRWD tCASD tCASD tDQMD DQMxx tDQMD tRDS2 tRDH2 D31 to D0 tBSD tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 24.23 Synchronous DRAM Read Bus Cycle (RCD = 2, CAS Latency = 2, TPC = 1) Rev. 4.00, 03/04, page 592 of 660 Tr CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 (Tpc) (Tpc) Row address tAD Row address tAD Read command Read A command tAD Row address Column address (1-4) tCSD3 tRWD RD/ tRASD tRASD ;; ;; tAD tAD tAD tCSD3 tRWD tCASD tDQMD tRDS2 tRDH2 tBSD tCASD tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD CKE tDAKD1 DACKn (High) tDAKD1 Figure 24.24 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 0, CAS Latency = 1, TPC = 1) Rev. 4.00, 03/04, page 593 of 660 Tr CKIO tAD A25 to A16 tAD A12 or A11 Trw Tc1 Tc2 Tc3 Tc4/Td1 Td2 Td3 Td4 (Tpc) Row address A15 to A0 Row address tCSD3 tRWD RD/ tRASD ; ;; ; ;; ; ;; tAD Row address tAD tAD tAD tAD Read command tAD tAD tAD Column address (1-4) tRASD tCASD tCASD tRDS2 tRDH2 tBSD tBSD (High) tCSD3 tRWD tDQMD DQMxx tDQMD tRDS2 tRDH2 D31 to D0 (read) CKE tDAKD1 DACKn tDAKD1 Figure 24.25 Synchronous DRAM Read Bus Cycle (Burst Read (Single Read x 4), RCD = 1, CAS Latency = 3, TPC = 0) Rev. 4.00, 03/04, page 594 of 660 Tr CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 tCSD3 Row address Tc1 (Trwl) (Tpc) tAD tAD Row address Write A command tAD tAD Row address Column address tAD tCSD3 tRWD RD/ tRASD tRWD tRWD tRASD DQMxx D31 to D0 ;;; ;;; tCASD tDQMD tWDD2 tBSD (High) tDAKD1 tCASD tDQMD tWDH2 tBSD CKE tDAKD1 DACKn Figure 24.26 Synchronous DRAM Write Bus Cycle (RCD = 0, TPC = 0, TRWL = 0) Rev. 4.00, 03/04, page 595 of 660 Tr CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 Trw Trw Tc1 (Trwl) (Trwl) (Tpc) (Tpc) tCSD3 ;;; ;;; tAD Row address tAD tAD tAD Row address Write A command tAD tAD tAD Row address Column address tCSD3 tRWD RD/ tRASD tRASD tRWD tRWD DQMxx D31 to D0 ;;;; ;;;; tCASD tDQMD tWDD2 tBSD (High) tDAKD1 tCASD tDQMD tWDH2 tBSD CKE tDAKD1 DACKn Figure 24.27 Synchronous DRAM Write Bus Cycle (RCD = 2, TPC = 1, TRWL = 1) Rev. 4.00, 03/04, page 596 of 660 Tr CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 Tc1 Tc2 Tc3 Tc4 (Trwl) (Tpc) (Tpc) tAD Row address tAD Row address tAD Write command tAD Write A command tAD Row address tAD Column address (1-4) tCSD3 tCSD3 tRWD RD/ tRASD tRWD tRWD tRASD DQMxx D31 to D0 ;; ;; tCASD tWDD2 tBSD tDAKD1 tCASD tDQMD tDQMD tWDD2 tWDH2 tBSD CKE (High) tDAKD1 DACKn Figure 24.28 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 0, TPC = 1, TRWL = 0) Rev. 4.00, 03/04, page 597 of 660 Tr CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 Trw Tc1 Tc2 Tc3 Td4 (Trwl) (Tpc) Row address tAD Row address Row address tCSD3 tRWD RD/ tRASD ;; ; tAD tRWD tRASD tCASD tDQMD tWDD2 tWDD2 tBSD (High) tAD tAD tAD Write A command Write command tAD Column address (1-4) tCSD3 tRWD DQMxx D31 to D0 ;;; tDAKD1 tCASD tDQMD tWDH2 tBSD CKE tDAKD1 DACKn Figure 24.29 Synchronous DRAM Write Bus Cycle (Burst Mode (Single Write x 4), RCD = 1, TPC = 0, TRWL = 0) Rev. 4.00, 03/04, page 598 of 660 Tnop Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 tCSD3 Column address tCSD3 Read command tAD Row address tAD tAD CSn tRWD RD/WR tRASD2 tRWD RAS tCASD2 tCASD2 CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD tRDS2 tRDH2 tDQMD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 24.30 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 1) Rev. 4.00, 03/04, page 599 of 660 Tc1 Tc2 Tc3/Td1 Tc4/Td2 Td3 Td4 CKIO tAD A25 to A16 tAD A12 or A11 tAD A15 to A0 tCSD3 Column address tCSD3 Read command tAD Row address tAD tAD CSn tRWD RD/WR tRASD tRWD RAS tCASD tCASD CAS tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD tRDS2 tRDH2 tDQMD BS CKE (High) tDAKD1 tDAKD1 DACKn Figure 24.31 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Same Row Address, CAS Latency = 2) Rev. 4.00, 03/04, page 600 of 660 Tp Tr Tc1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 CKIO tAD tAD A25 to A16 tAD tAD tAD Row address tAD tAD Row address tCSD3 Row address tAD A12 or A11 Read command tAD Column address tCSD3 A15 to A0 tRWD tRWD tRWD RD/ tRASD tRASD tCASD tCASD tDQMD tDQMD tDQMD DQMxx tRDS2 tRDH2 D31 to D0 tBSD tBSD tRDS2 tRDH2 CKE (HIGH) tDAKD1 tDAKD1 DACKn Figure 24.32 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0, CAS Latency = 1) Rev. 4.00, 03/04, page 601 of 660 ; Tp Tpw Tr Tc1 CKIO tAD A25 to A16 tAD tAD tAD A12 or A11 Row address tAD tAD A15 to A0 Row address tCSD3 tRWD tRWD RD/ tRASD tRASD tRASD tRASD tCASD tDQMD tDQMD DQMxx D31 to D0 CKE (HIGH) tDAKD1 Tc2/Td1 Tc3/Td2 Tc4/Td3 Td4 tAD Row address tAD Read command tAD Column address tCSD3 tRWD tCASD tDQMD tRDS2 tRDH2 tRDS2 tRDH2 tBSD tBSD tDAKD1 DACKn Figure 24.33 Synchronous DRAM Burst Read Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 0, CAS Latency = 1) Rev. 4.00, 03/04, page 602 of 660 Tc1 Tc2 Tc3 Tc4 CKIO tAD tAD A25 to A16 tAD Row address tAD A12 or A11 tAD Write command tAD Column address tCSD3 tCSD3 A15 to A0 tRWD RD/ tRASD tRWD tRASD tCASD tCASD tDQMD tDQMD DQMxx tWDD2 tWDD2 D31 to D0 tBSD tBSD CKE (HIGH) tDAKD1 tDAKD1 DACKn Figure 24.34 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Same Row Address) Rev. 4.00, 03/04, page 603 of 660 ; Tp Tr Tc1 Tc2 CKIO tAD A25 to A16 Row address tAD tAD tAD A12 or A11 Row address tAD tAD A15 to A0 Row address tCSD3 tRWD tRWD tRWD RD/ tRASD tRASD tCASD tDQMD tDQMD DQMxx tWDD2 D31 to D0 tBSD CKE (HIGH) tDAKD1 Tc3 Tc4 tAD tAD Write command tAD Column address tCSD3 tRWD tCASD tDQMD tWDD2 tBSD tDAKD1 DACKn Figure 24.35 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 0, RCD = 0) Rev. 4.00, 03/04, page 604 of 660 ; ; Tp Tpw Tr Trw Tc1 Tc2 CKIO tAD A25 to A16 Row address tAD tAD tAD A12 or A11 Row address tAD tAD tAD A15 to A0 Row address tCSD3 tRWD tRWD tRWD RD/ tRASD tRASD tRASD tRASD tCASD tDQMD tDQMD DQMxx tWDD2 D31 to D0 tBSD CKE (HIGH) tDAKD1 Tc3 Td4 tAD tAD Write command tAD Column address tCSD3 tRWD tCASD tDQMD tWDD2 tBSD tDAKD1 DACKn Figure 24.36 Synchronous DRAM Burst Write Bus Cycle (RAS Down, Different Row Address, TPC = 1, RCD = 1) Rev. 4.00, 03/04, page 605 of 660 Tp Tpc TRr TRrw TRrw TRrw (Tpc) (Tpc) CKIO CKE tCSD3 (High) tCSD3 tRASD tRASD tRASD tRASD tCASD tCASD tRWD RD/ tRWD Figure 24.37 Synchronous DRAM Auto-Refresh Timing (TRAS = 1, TPC = 1) Tp CKIO Tpc TRa1 (TRs2) (TRs2) TRs3 (Tpc) (Tpc) tCKED CKE tCKED tCSD3 tCSD3 tRASD tRASD tRASD tRASD tCASD tCASD tRWD RD/ tRWD tRWD Figure 24.38 Synchronous DRAM Self-Refresh Cycle (TPC = 0) Rev. 4.00, 03/04, page 606 of 660 TRp1 CKIO TRp2 TRp3 TRp4 TMw1 TMw2 TMw3 TMw4 A13 or A10 A12 or A11 A10 to A2 or A9 to A2 RD/ D31 to D0 CKE DACKn ;;;;; ;;;;;; ;;;;;; ;;;;; ;;;; ;;;;;; ;;;;;; tAD tAD tAD tAD tAD tAD tAD tAD tCSD3 tRWD tRWD tRWD tRASD tRASD tRASD tRASD tCASD tCASD tDAKD1 (High) tAD tAD tAD tCSD3 tDAKD1 Figure 24.39 Synchronous DRAM Mode Register Write Cycle Rev. 4.00, 03/04, page 607 of 660 24.3.7 PCMCIA Timing Tpcm1 Tpcm2 CKIO tAD A25 to A0 tCSD1 tCSD1 tAD +-NN tRWD RD/94 tRSD (read) tRDS1 D15 to D0 (read) tWED (write) tWDD1 D15 to D0 (write) tBSD tBSD tWED tWDH4 tWDH1 tRSD tRWD 4, tRDH1 9- *5 tDAKD1 DACKn tDAKD1 Figure 24.40 PCMCIA Memory Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 4.00, 03/04, page 608 of 660 Tpcm0 CKIO tAD A25 to A0 tCSD1 Tpcm0w Tpcm1 Tpcm1w Tpcm1w Tpcm2 Tpcm2w tAD tCSD1 tRWD RD/ tRSD (read) tRWD tRSD tRDH1 tRDS1 D15 to D0 (read) tWED (write) tWED tWDH4 tWDD1 tWDH1 D15 to D0 (write) tBSD tBSD tDAKD1 DACKn tWTS tWTH tWTS tWTH tDAKD1 Figure 24.41 PCMCIA Memory Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) Rev. 4.00, 03/04, page 609 of 660 Tpcm1 CKIO tAD A25 to A4 tAD A3 to A0 tCSD1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 Tpcm1 Tpcm2 tAD tAD tAD tAD tCSD1 +-NN tRWD RD/94 tRSD (read) tRDS1 D15 to D0 (read) tBSD tBSD tBSD tBSD tRSD tRSD tRSD tRWD 4, tRDH1 tRDS1 tRDH1 *5 tDAKD1 DACKn tDAKD1 Note: Even though burst mode is set, write cycle operation is the same as in normal mode. Figure 24.42 PCMCIA Memory Bus Cycle (Burst Read, TED = 0, TEH = 0, No Wait) Rev. 4.00, 03/04, page 610 of 660 Tpcm0 Tpcm1 Tpcm1w Tpcm1w Tpcm1w Tpcm2 Tpcm1 Tpcm1w Tpcm2 Tpcm2w CKIO tAD A25 to A4 tAD A3 to A0 tCSD1 tCSD1 tAD tAD tAD +-NN tRWD RD/94 tRSD tRSD tRSD tRSD tRWD (read) tRDS1 D15 to D0 (read) tBSD tBSD 4, tRDH1 tRDS1 tRDH1 tBSD tBSD *5 tDAKD1 DACKn tWTS tWTH tWTS tWTH tWTS tWTH tDAKD1 9)16 Note: Even though burst mode is set, the write cycle operation is the same as in normal mode. Figure 24.43 PCMCIA Memory Bus Cycle (Burst Read, TED = 1, TEH = 1, Two Waits, Burst Pitch = 3) Rev. 4.00, 03/04, page 611 of 660 Tpci1 Tpci2 CKIO tAD A25 to A0 tCSD1 tCSD1 tAD CExx tRWD RD/WR tICRSD tICRSD tRWD ICIORD (read) tRDS1 D15 to D0 (read) tICWSD tICWSD tRDH1 ICIOWR (write) tWDD1 D15 to D0 (write) tBSD tBSD tWDH4 tWDH1 BS tDAKD1 DACKn tDAKD1 Figure 24.44 PCMCIA I/O Bus Cycle (TED = 0, TEH = 0, No Wait) Rev. 4.00, 03/04, page 612 of 660 Tpci0 CKIO tAD A25 to A0 tCSD1 Tpci0w Tpci1 Tpci1w Tpci1w Tpci2 Tpci2w tAD tCSD1 CExx tRWD RD/WR tRWD ICIORD (read) tICRSD tICRSD tRDH1 tRDS1 D15 to D0 (read) tICWSD tICWSD tWDH4 tWDD1 D15 to D0 (write) tBSD tBSD tWDH1 ICIOWR (write) BS tDAKD1 DACKn tWTS tWTH tWTS tWTH tDAKD1 WAIT tIO16S tIO16H IOIS16 Figure 24.45 PCMCIA I/O Bus Cycle (TED = 2, TEH = 1, One Wait, External Wait) Rev. 4.00, 03/04, page 613 of 660 Tpci0 CKIO tAD A25 to A4 tAD A0 tCSD1 Tpci1 Tpci1w Tpci2 Tpci1 Tpci1w Tpci2 Tpci2w tAD tAD tAD tCSD1 tCSD1 CExx tRWD RD/WR tICRSD tICRSD tICRSD tICRSD tRWD ICIORD (read) tRDS1 D15 to D0 (read) tICWSD tICWSD tICWSD tICWSD tRDH1 tRDS1 tRDH1 ICIOWR (write) tWDH3 tWDD1 D15 to D0 (write) tBSD tBSD tBSD tBSD tWDD2 tWDH4 tWDH1 BS tDAKD1 DACKn tWTS tWTH tWTS tWTH tDAKD1 WAIT tIO16S tIO16H IOIS16 Figure 24.46 PCMCIA I/O Bus Cycle (TED = 1, TEH = 1, One Wait, Bus Sizing) Rev. 4.00, 03/04, page 614 of 660 24.3.8 Peripheral Module Signal Timing Table 24.8 Peripheral Module Signal Timing Module TMU, RTC Item Timer input setup time Timer clock input setup time Timer clock pulse width Edge specification Both edge specification Symbol tTCLKS tTCKS tTCKWH tTCKWL tROSC tSCYC tSCKR tSCKF tSCKW tTXD tRXS tRXH tRTSD tCTSS tCTSH tPORTD tPORTS1 tPORTH1 tPORTS2 tPORTH2 tPORTS3 tPORTH3 tDREQ tDREQH tDRAKD Min 15 15 1.5 2.5 -- 4 6 -- -- 0.4 -- 100 100 -- 100 100 -- 15 8 tcyc+ 15 8 Max -- -- -- -- 3 -- -- 1.5 1.5 0.6 100 -- -- 100 -- -- 17 -- -- -- -- ns 24.52 tscyc ns 24.51 s tcyc 24.44 24.50, 24.51 24.50 tcyc Unit ns Figure 24.47 24.48 Oscillation settling time SCI Input clock cycle Asynchronization Clock synchronization Input clock rise time Input clock fall time Input clock pulse width Transmission data delay time Receive data setup time (clock synchronization) Receive data hold time (clock synchronization) RTS delay time CTS setup time (clock synchronization) CTS hold time (clock synchronization) Port Output data delay time Input data setup time 1 Input data hold time 1 Input data setup time 2 Input data hold time 2 Input data setup time 3 Input data hold time 3 DMAC DREQ setup time DREQ hold time DRAK delay time 3xtcyc -- +15 8 6 4 -- -- -- -- 10 22.54 ns 24.53 Rev. 4.00, 03/04, page 615 of 660 CKIO tTCLKS TCLK (input) Figure 24.47 TCLK Input Timing tTCKS CKIO tTCKS TCLK (input) tTCKWL tTCKWH Figure 24.48 TCLK Clock Input Timing Stable oscillation RTC crystal oscillator VCC VCCmin tROSC Figure 24.49 Oscillation Settling Time at RTC Crystal Oscillator Power-on tSCKW SCK tScyc tSCKR tSCKF Figure 24.50 SCK Input Clock Timing Rev. 4.00, 03/04, page 616 of 660 tScyc SCK tTXD TxD (data transmissiion) RxD (data reception) tRXS tRXH tRTSD tCTSS tCTSH Figure 24.51 SCI I/O Timing in Clock Synchronous Mode CKIO tPORTS1 PORT 7 to 0 (read) (B:P clock ratio = 1:1) PORT 7 to 0 (read) (B:P clock ratio = 2:1) PORT 7 to 0 (read) (B:P clock ratio = 4:1) tPORTH1 tPORTS2 tPORTH2 tPORTS3 tPORTH3 tPORTD PORT 7 to 0 (write) Figure 24.52 I/O Port Timing CKIO tDRQS tDRQH Figure 24.53 DREQ Input Timing Rev. 4.00, 03/04, page 617 of 660 CKIO tDRAKD tDRAKD DRAK0/1 Figure 24.54 DRAK Output Timing 24.3.9 H-UDI, AUD Related Pin Timing Table 24.9 H-UDI, AUD Related Pin Timing Item TCK cycle time TCK high pulse width TCK low pulse width TCK rise/fall time TRST setup time TRST hold time TDI setup time TDI hold time TMS setup time TMS hold time TDO delay time ASEMD0 setup time ASEMD0 hold time AUDCK cycle time AUDATA delay time AUDSYNC delay time Symbol tTCKcyc tTCKH tTCKL tTCKf tTRSTS tTRSTH tTDIS tTDIH tTMSS tTMSH tTDOD tASEMDH tASEMDS tAUDCYC tAUDD tAUSYD Min 50 12 12 -- 12 50 10 10 10 10 -- 12 12 -- -- -- Max -- -- -- 4 -- -- -- -- -- -- 16 -- -- 66 12 12 Unit ns ns ns ns ns tcyc ns ns ns ns ns ns ns ms ns ns 24.59 24.58 24.57 24.56 Figure 24.55 Rev. 4.00, 03/04, page 618 of 660 tTCKcyc tTCKH VIH 1/2VccQ VIH VIL VIL tTCKf Note: When clock is input from TCK pin 1/2VccQ tTCKL VIH tTCKf Figure 24.55 TCK Input Timing RESETP tTRSTS TRST tTRSTH Figure 24.56 TRST Input Timing (Reset Hold) TCK tTCKcyc tTDIS tTDIH TDI tTMSS tTMSH TMS tTDOD TDO Figure 24.57 H-UDI Data Transfer Timing Rev. 4.00, 03/04, page 619 of 660 RESETP tASEMDOS tASEMDOH ASEMD0 Figure 24.58 ASEMD0 Input Timing tAUDCYC AUDCK tAUDD AUDATA tAUSYD tAUDD AUDSYNC Figure 24.59 AUD Timing 24.3.10 A/D Converter Timing Table 24.10 A/D Converter Timing Item External trigger input pulse width External trigger input start delay time Input sampling time Symbol tTRGW tTRGS Min 2 50 -- -- 17 10 514 259 Typ -- -- 129 65 -- -- -- -- Max -- -- -- -- 28 17 525 266 tcyc tcyc Unit tcyc ns tcyc 24.61 Figure 24.60 (CKS = 0) tSPL (CKS = 1) A/D conversion start delay time (CKS = 0) tD (CKS = 1) A/D conversion time tcyc: P cycle (CKS = 0) tCONV (CKS = 1) Rev. 4.00, 03/04, page 620 of 660 1 state CK tTRGW input tTRGS ADCR Figure 24.60 External Trigger Input Timing *1 P Address *2 Write signal Input sampling timing ADF tD tSPL tCONV : A/D conversion start delay tD tSPL : Input sampling time tCONV: A/D conversion time Notes: 1. ADCSR write cycle 2. ADCSR address Figure 24.61 A/D Conversion Timing Rev. 4.00, 03/04, page 621 of 660 24.3.11 AC Characteristics Measurement Conditions * I/O signal reference level: VccQ/2 (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V) * Input pulse level: VssQ to 3.0 V (where RESETP, RESETM, ASEMD0, ADTRG, TRST, CA, NMI, IRQ5 to IRQ0, CKIO, and MD5 to MD0 are within VssQ to VccQ) * Input rise and fall times: 1 ns IOL LSI output pin CL DUT output VREF IOH Notes: 1. CL is the total value that includes the capacitance of measurement instruments, etc., and is set as follows for each pin. 30 pF: CKIO, RASx, CASxx, CS0, CS2 to CS6, CE2A, CE2B, BACK 50 pF: All other pins IOL and IOH are the values shown in table 23.3. 2. Figure 24.62 Output Load Circuit Rev. 4.00, 03/04, page 622 of 660 24.3.12 Delay Time Variation Due to Load Capacitance A graph (reference data) of the variation in delay time when a load capacitance greater than that stipulated (30 pF) is connected to this LSI's pins is shown below. The graph shown in figure 24.63 should be taken into consideration in the design process if the stipulated capacitance is exceeded in connecting an external device. If the connected load capacitance exceeds the range shown in figure 24.63 the graph will not be a straight line. +3 Delay Time [ns] +2 +1 +0 +0 +10 +20 +30 +40 +50 Load Capacitance [pF] Figure 24.63 Load Capacitance vs. Delay Time Rev. 4.00, 03/04, page 623 of 660 24.4 A/D Converter Characteristics Table 24.11 lists the A/D converter characteristics. Table 24.11 A/D Converter Characteristics (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C) Item Resolution Conversion time Analog input capacitance Permissible signal-source (singlesource) impedance Nonlinearity error Offset error Full-scale error Quantization error Absolute accuracy Min 10 15 -- -- -- -- -- -- -- Typ 10 -- -- -- -- -- -- -- -- Max 10 -- 20 5 3.0 2.0 2.0 0.5 4.0 Unit bits s pF k LSB LSB LSB LSB LSB 24.5 D/A Converter Characteristics Table 24.12 lists the D/A converter characteristics. Table 24.12 D/A Converter Characteristics (VccQ = 3.3 0.3 V, Vcc = 1.9 0.15 V, AVcc = 3.3 0.3 V, Ta = -20 to 75C) Item Resolution Conversion time Absolute accuracy Min 8 -- -- Typ 8 -- 2.5 Max 8 10.0 4.0 Unit bits s LSB 20-pF capacitive load 2-M resistance load Test Conditions Rev. 4.00, 03/04, page 624 of 660 Appendix A. Circuit Equivalent Circuits of I/O Buffer for Each Pin Function Input with enable input data input enable Pin Name WAIT BREQ VccQ pull-up enable Input with enable Pull-up with enable RxD0/SCPT[0] RxD2/SCPT[2] AUDCK/PTG[4] input data input enable Schmitt trigger input input data ASEMD0 MD[5:0] RESERM NMI RESETP CA VccQ pull-up enable Input with enable Schmitt trigger input Pull-up with enable CTS2/IRQ5/SCPT[5] ADTRG/PTG[5] input data input data input enable Rev. 4.00, 03/04, page 625 of 660 Circuit input data input enable input enable input analog data Function Input with enable Analog input with enable Pin Name AN[1:0]/PTJ[1:0] Input with enable input data input enable input enable input analog data output enable output analog data AN[3:2]/DA[0:1]/PTJ[3:2] Analog input with enable Analog output with enable VccQ 3-state output RD WE0/DQMLL WE1/DQMLU/WE CS0 BACK TxD0/SCPT[0] TxD2/SCPT[2] output enable output data VssQ VccQ 3-state output Pull-up with enable output enable output data VccQ A[25:12] VssQ pull-up enable Rev. 4.00, 03/04, page 626 of 660 Circuit VccQ Function 3-state output Input with enable output enable output data VccQ pull-up enable input data input enable Pin Name D[31:24]/PTB[7:0] D[23:16]/PTA[7:0] D[15:0] A[11:0] BS/PTC[0] WE2/DQMUL/ICIORD/PTC[1] WE3/DQMUU/ICIOWR/PTC[2] CS[4:2]/PTC[5:3] CS5/CE1A/PTC[6] CS6/CE1B/PTC[7] CE2A/PTD[6] CE2B/PTD[7] RASL/PTD[0] RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] CKE/PTD[4] IOIS16/PTD[5] DACK[1:0]/PTE[1:0] DRAK[1:0]/PTE[3:2] AUDATA[3:0]/PTF[3:0] AUDSYNC/PTF[4] TDO/PTF[5] ASEBRKAK/PTF[6] STATUS[1:0]/PTE[5:4] TCLK/PTE[6] IRQOUT/PTE[7] SCK0/SCPT[1] SCK2/SCPT[3] RTS2/SCPT[4] DREQ[1:0]/PTH[6:5] Pull-up with enable VssQ VccQ 3-state output Input with enable output enable output data RD/WR CKIO VssQ input data input enable Rev. 4.00, 03/04, page 627 of 660 Circuit VccQ Function 3-state output output enable output data VccQ pull-up enable input data input enable input data Pin Name TDI/PTG[0] TCK/PTG[1] TMS/PTG[2] TRST/PTG[3] IRQ[3:0]/IRL[3:0]/PTH[3:0] IRQ4/PTH[4] Input with enable Schmitt trigger input Pull-up with enable VssQ clock out XTAL2 32-kHz crystal oscillation EXTAL2 input EXTAL2 clock enable XTAL clock out Switch between crystal resonator and crystal oscillator input (input from EXTAL) EXTAL clock enable EXTAL select Rev. 4.00, 03/04, page 628 of 660 B. B.1 Pin Functions Pin Functions Table B.1 shows pin states during resets, power-down states, and the bus-released states. Table B.1 Category Pin States during Resets, Power-Down States, and Bus-Released State Reset Pin Power-On Manual Reset Reset I O* 1 1 Power-Down Standby I 1 1 1 1 Sleep I O* 1 1 Bus Released I O* 1 1 Clock EXTAL XTAL CKIO EXTAL2 XTAL2 CAP1, CAP2 RESETP RESETM BREQ BACK MD[5:0] CA STATUS[1:0]/PTE[5:4] I O* O* IO* I O -- I I I O I I O I* I* I IV IV IV IV H Z 8 IO* I O -- I I I O I I IO* I O -- I I I O I I 3 IO* I O -- I I I O I I 3 IO* I O -- I I System control L I 3 3 OP* I I I I I I I OP* O OP* I I I IZ IZ IZ IZ OP* I I I I I I I OP* I I I I I I I Interrupt IRQ[3:0]/IRL[3:0]/ PTH[3:0] IRQ4/ PTH[4] NMI TCK/PTG[1] TDI/PTG[0] TMS/PTG[2] TRST/PTG[3] IRQOUT/PTE[7] 8 3 ZK* ZL* 3 OP* O 3 OP* Z 3 Address bus A[25:0] 10 Rev. 4.00, 03/04, page 629 of 660 Reset Category Data bus Pin D[15:0] D[23:16]/PTA[7:0] D[31:24]/PTB[7:0] Bus control CS0 CS[2:4]/PTC[5:3] CS5/CE1A/PTC[6] CS6/CE1B/PTC[7] BS/PTC[0] RASL/PTD[0] RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ICIORD/ PTC[1] Power-On Manual Reset Reset Z Z Z H H H H H H H H H H H H I IP* IP* O OP* OP* OP* OP* OP* OP* OP* OP* O O OP* 3 3 3 3 3 3 3 3 3 3 3 Power-Down Standby Z ZK* ZK* 3 3 11 11 11 11 11 3 3 Sleep IO IOP* IOP* O OP* OP* OP* OP* OP* OP* OP* OP* O O 3 3 3 3 3 3 3 3 3 3 Bus Released Z ZP* ZP* Z ZP* ZP* ZP* ZP* 3 3 3 3 4 4 4 4 3 3 ZH* ZH* K* ZH* K* ZH* K* 4 4 4 4 3 3 ZH* K* ZOK* ZOK* ZOK* ZOK* ZH* ZH* 11 11 11 ZOP* ZOP* ZOP* ZOP* Z Z ZH* K* ZH* K* ZH* ZH* 11 11 3 11 3 OP* OP* O O OP* I I 3 ZP* ZP* Z Z 3 WE3/DQMUU/ICIOWR/ H PTC[2] RD/WR RD CKE/PTD[4] WAIT DMAC DREQ0/PTH[5] DACK0/PTE[0] DRAK0/PTE[2] DREQ1/PTH[6] DACK1/PTE[1] DRAK1/PTE[3] Timer TCLK/PTE[6] H H H Z I O O I O O I OP* O O OP* I ZI* 7 3 3 3 3 3 OK* Z Z 3 OP* Z I 3 OP* OP* ZI* 7 3 3 ZK* 3 11 3 OP* OP* I 3 3 OP* OP* I 3 3 ZH* K* Z 3 11 OP* OP* ZI* 7 3 3 ZK* OP* 3 3 3 5 OP* OP* 3 3 5 ZH* K* IOP* 5 OP* IOP* IOP* Rev. 4.00, 03/04, page 630 of 660 Reset Category Pin Power-On Manual Reset Reset Z Z V Z Z V V V* 8 Power-Down Standby Z 7 3 3 Sleep IZ* 6 6 5 Bus Released IZ* 6 6 5 SCI/Smart card RxD0/SCPT[0] without FIFO TxD0/SCPT[0] SCK0/SCPT[1] SCIF with FIFO RxD2/SCPT[2] TxD2/SCPT[2] SCK2/SCPT[3] RTS2/SCPT[4] CTS2/IRQ5/SCPT[5] Port AUDSYNC/PTF[4] CE2B/PTD[7] CE2A/PTD[6] TDO/PTF[5] IOIS16/PTD[5] AUDCK/PTG[4] ADTRG/PTG[5] ASEBRKAK/PTF[6] ASEMD0 Analog AN[1:0]/PTJ[1:0] AN[3:2]/DA[0:1]/ PTJ[3:2] ZI* 7 ZO* ZP* ZI* 7 ZK* ZK* Z OZ* 6 OZ* 6 3 IOP* IZ* IOP* IZ* ZO* ZP* 7 7 ZK* ZK* ZK* I 3 3 3 OZ* 6 5 OZ* 6 5 3 3 IOP* OP* I IOP* OP* I OP* ZI* 3 3 OV H H OV I IV V* 8 OP* OP* OP* OP* I I I I OP* I ZI* 7 7 3 3 3 3 OK* 3 3 3 OP* OP* OP* OP* I I I I 3 3 3 3 OP* ZP* ZP* 3 ZH* K* ZH* K* OK* Z IZ IZ IZ 3 11 11 3 3 3 OP* I I I I AUDATA[3:0]/PTF[3:0] IV OV I Z Z 3 OP* Z Z OZ* 3 OP* I I 3 OP* I I 3 ZI* 2 IO* 9 IO* 9 Legend I: Input O: Output H: High-level output L: Low-level output Z: High impedance P: Input or output depending on register setting K: Input pin is high impedance, output pin holds the state V: I/O buffer off, pullup MOS on Notes: 1. 2. 3. 4. Depending on the clock mode (MD2 to MD0 setting) 0 when DA output is enabled: otheruise Z. K or P when the port function is used. K or P when the port function is used. Z or O when the port function is not used depending on register setting. Rev. 4.00, 03/04, page 631 of 660 K or P when the port function is used. I or O when the port function is not used depending on register setting. 6. Depending on register setting 7. I or O when the port function is used. 8. Input Schmitt buffers of IRQ[5:0] and ADTRG are on. Input Schmitt buffers of the other inputs (e.g. PTH, CTS2) that are shared with these pins are off. 9. O when DA output is enabled; otherwise depends on a register setting. 10. In the standby mode, Z or L depending on register setting. 11. In the standby mode, Z or H depending on register setting. 5. Rev. 4.00, 03/04, page 632 of 660 B.2 Pin Specifications Table B.2 shows the pin specifications. Table B.2 Pin Specifications Number of Pins Pin MD0 MD1 MD2 MD3 MD4 MD5 D31 to D24/ PTB[7] to PTB[0] D23 to D16/ PTA[7] to PTA[0] D15 to D0 FP-176C 163 129 164 167 168 169 5, 6, 7, 8, 9, 10, 12, 14 TBP-208A D8 C17 B7 C6 D6 A5 F4, F3, F2, F1, G4, G3, G1, H3 I/O Data bus / input/output port A I/O I I I I I I I/O Function Clock mode setting Clock mode setting Clock mode setting Area 0 bus width setting Area 0 bus width setting Endian setting Data bus / input/output port B 15, 16, 17, 18, H2, H1, J4, J2, 20, 22, 23, 24 J3, K2, K3, K4 26, 28, 29, 30, L2, L4, M1, M2, 31, 32, 33, 34, M3, M4, N1, N2, 35, 36, 38, 40, N3, N4, P2, R1, 41, 42, 43, 44 R2, P4, T1, T2 I/O Data bus A25 to A0 76, 75, 74, 72, T11, P10, T10, 70, 69, 68, 67, R9, T9, P9, U8, 66, 65, 64, 62, T8, R8, P8, U7, 60, 59, 58, 57, R7, U6, T6, R6, 56, 55, 54, 53, P6, U5, T5, R5, 52, 50, 48, 47, P5, U4, R4, T3, 46, 45 R3, U2, U1 R11 P11 U12 T12 O Address bus BS/PTC[0] RD WE0/DQMLL WE1/DQMLU/WE WE2/DQMUL/ ICIORD/PTC[1] WE3/DQMUU/ ICIOWR/PTC[2] RD/WR CS0 77 78 79 80 O / I/O O O O Bus cycle start signal / input/output port C Read strobe D7 to D0 select signal / DQM (SDRAM) D15 to D8 select signal / DQM (SDRAM) / write strobe (PCMCIA) 81 R12 O/O/ O / I/O D23 to D16 select signal / DQM (SDRAM) / PCMCIA input/output read / input/output port C D31 to D24 select signal / DQM (SDRAM) / PCMCIA input/output write / input/output port C Read/write Chip select 82 P12 O/O/ O / I/O 83 85 U13 P13 O O Rev. 4.00, 03/04, page 633 of 660 Number of Pins Pin CS2/PTC[3] CS3/PTC[4] CS4/PTC[5] CS5/CE1A/PTC[6] CS6/CE1B/PTC7] CE2A/PTD[6] CE2B/PTD[7] RASL/PTD[0] RASU/PTD[1] CASL/PTD[2] CASU/PTD[3] CKE/PTD[4] IOIS16/PTD[5] BACK BREQ WAIT DACK0/PTE[0] DACK1/PTE[1] DRAK0/PTE[2] DRAK1/PTE[3] AUDATA[0]/PTF[0] AUDATA[1]/PTF[1] AUDATA[2]/PTF[2] AUDATA[3]/PTF[3] AUDSYNC/PTF[4] TDI/PTG[0] TCK/PTG[1] TMS/PTG[2] TRST/PTG[3] TDO/PTF[5] FP-176C 87 88 89 90 91 92 94 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 116 118 119 120 TBP-208A T14 R14 U17 T17 R15 R16 P15 P17 N14 N15 N16 N17 M14 M15 M16 M17 L14 L15 L16 L17 K15 K16 K17 J14 J16 J17 H17 G16 G15 G14 I/O O / I/O O / I/O O / I/O O / O / I/O O / O / I/O O / I/O O / I/O O / I/O O / I/O O / I/O O / I/O O / I/O I / I/O O I I O / I/O O / I/O O / I/O O / I/O I/O I/O I/O I/O O / I/O I I I I O / I/O Function Chip select 2 / input/output port C Chip select 3 / input/output port C Chip select 4 / input/output port C Chip select 5 / CE1 (area 5 PCMCIA) / input/output port C Chip select 6 / CE1 (area 6 PCMCIA) / input/output port C Area 5 PCMCIA CE2 / input/output port D Area 6 PCMCIA CE2 / input/output port D Lower 32 Mbytes address RAS (SDRAM) / input/output port D Upper 32 Mbytes address RAS (SDRAM) / input/output port D Lower 32 Mbytes address CAS (SDRAM) / input/output port D Upper 32 Mbytes address CAS (SDRAM) / input/output port D CK enable (SDRAM) / input/output port D IOIS16 (PCMCIA) / input port D Bus acknowledge Bus request Hardware wait request DMA acknowledge 0 / input/output port E DMA acknowledge 1 / input/output port E DMA request acknowledge / input/output port E DMA request acknowledge / input/output port E AUD data / input/output port F AUD data / input/output port F AUD data / input/output port F AUD data / input/output port F AUD synchronous / input/output port F Data input (H-UDI) / input port G Clock (H-UDI) / input port G Mode select (H-UDI) / input port G Reset (H-UDI) / input port G Data output (H-UDI) / input/output port F Rev. 4.00, 03/04, page 634 of 660 Number of Pins Pin ASEBRKAK/PTF[6] ASEMDO CAP1 CAP2 XTAL EXTAL XTAL EXTAL2 STATUS0/PTE[4] STATUS1/PTE[5] TCLK/PTE[6] IRQOUT/PTE[7] CKIO TxD0/SCPT[0] TxD2/SCPT[2] SCK0/SCPT[1] SCK2/SCPT[3] RxD0/SCPT[0] RxD2/SCPT[2] RTS2/SCPT[4] CTS2/IRQ5/ SCPT[5] RESETM IRQ[3:0]/IRL[3:0]/ PTH[[3:0]] IRQ4/PTH[4] NMI AUDCK/PTG[4] RESETP CA AN[0]/PTJ[0] AN[1]/PTJ[1] AN2[2]/DA[1]/PTJ[2] AN3[3]/DA[0]/PTJ[3] FP-176C 121 122 124 127 131 132 2 3 133 134 135 136 138 140 142 141 143 145 146 144 147 TBP-208A F16 F15 E16 D17 B17 B16 C2 C1 A17 A16 C15 B15 C14 A14 C13 D13 B13 D12 C12 A13 B12 I/O O / I/O I -- -- O I O I O / I/O O / I/O I/O O / I/O I/O O O I/O I/O I I O / I/O I Function ASE break acknowledge (H-UDI) / input/output port F ASE mode (H-UDI) PLL1 external capacitance pin PLL2 external capacitance pin Clock oscillator pin External clock / crystal oscillator pin On-chip RTC crystal oscillator pin On-chip RTC crystal oscillator pin Processor status / input/output port E Processor status / input/output port E TMU or RTC clock input/output / input/output port E Interrupt request notification / input/output port E System clock input/output SCI transmit data 0 / SC port SCIF transmit data 2 / SC port SCI clock 0 / SC port SCIF clock 2 / SC port SCI receive data 0 / SC port SCIF receive data 2 / SC port SCIF transmit request 2 / SC port SCIF transmit clear / external interruption request / SC port Manual reset request External interrupt request / input/output port H 149 151, 152, 153, 154 155 157 159 165 166 171 172 173 174 C11 A11, D10, C10, B10 A10 B9 C9 A6 B6 C5 D5 A4 B4 I I / I / I/O I / I/O I I I I I I I/O/I I/O/I External interrupt request / input/output port H Nonmaskable interrupt request AUD clock / input port G Power-on reset request Chip activate / hardware standby request A/D converter input / input port J A/D converter input / input port J A/D converter input / D/A converter output / input port J A/D converter input / D/A converter output / input port J Rev. 4.00, 03/04, page 635 of 660 Number of Pins Pin ADTRG/PTG[5] DREQ0/PTH[5] DREQ1/PTH[6] VCCQ FP-176C 162 160 161 13, 27, 39, 51, 63, 86, 95, 139, 158 21, 73, 117, 150 1 TBP-208A C8 A8 B8 I/O I I / I/O I / I/O Function Analog trigger / input port G DMA request / input/output port H DMA request / input/output port H Input/output power supply (3.3 V) H4, L3, P3, Power T4, T7, U14, supply P16, B14, A9 K1, U10, H16, B11 C3 Power supply Power supply Power supply Power supply Power supply Power supply VCC Internal power supply (1.9 V) VCC-RTC RTC power supply (1.9 V) VCC-PLL1 123 E17 PLL1 power supply (1.9 V) VCC-PLL2 128 D16 PLL2 power supply (1.9 V) AVCC 175 B3 Analog power supply (3.3 V) VSSQ 11, 25, 37, 49, 61, 84, 93, 137, 156 G2, L1, P1,U3, P7, R13, R17, A15, D9 J1, U9, J15, C16, D11 D3 Input/output power supply (0 V) VSS 19, 71, 115, 130, 148 4 Power supply Power supply Power supply Power supply Power supply Internal power supply (0 V) VSS-RTC RTC power supply (0 V) VSS-PLL1 125 E15 PLL1 power supply (0 V) VSS-PLL2 126 E14 PLL2 power supply (0 V) AVSS 170, 176 B5, B2 Analog power supply (0 V) Rev. 4.00, 03/04, page 636 of 660 B.3 Processing of Unused Pins * When RTC is not used EXTAL2: XTAL2: VCC - RTC: VSS - RTC: CAP1: Pull up to (VCC -RTC) Leave unconnected Power supply (1.9) Power supply (0 V) * When PLL1 is not used Leave unconnected Power supply (1.9) Power supply (0 V) VCC - PLL1: VSS - PLL1: CAP2: * When PLL2 is not used Leave unconnected Power supply (1.9 V) Power supply (0 V) Leave unconnected Pull up to VCCQ or VSS Leave unconnected Power supply (3.3 V) Power supply (0 V) Pull up to VCCQ VCC - PLL2: VSS - PLL2: XTAL: EXTAL: AN[3:0]: AVCC: AVSS: CA: * When on-chip crystal oscillator is not used * When EXTAL pin is not used * When A/D converter is not used * When hardware standby is not used Rev. 4.00, 03/04, page 637 of 660 B.4 Pin States in Access to Each Address Space Pin States (Normal Memory/Little Endian) 8-Bit Bus Width Byte/Word/Longword Access Enabled R W Low High High Low Enabled High High High High R W High Low High High High High High High High High Disabled Enabled* Disabled Address Valid data High-Z* High-Z* 2 1 Table B.3 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High Low High High High High High High High High Disabled Enabled* Disabled Address Valid data Invalid data High-Z* 2 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 2n + 1) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled* Disabled Address Invalid data Valid data High-Z* 2 1 Word/Longword Access Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Enabled* Disabled Address Valid data Valid data High-Z* 2 1 RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 R W R W 2 Rev. 4.00, 03/04, page 638 of 660 32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL R W WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 R W R W Low High High Low Enabled High High High High High Low High High High High High High High High Disabled Enabled* Disabled Address Valid data Invalid data Invalid data Invalid data 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 4n + 1) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled* Disabled Address Invalid data Valid data Invalid data Invalid data 1 Byte Access (Address 4n + 2) Enabled Low High High Low Enabled High High High High High High High High High Low High High High High Disabled Enabled* Disabled Address Invalid data Invalid data Valid data Invalid data 1 Byte Access (Address 4n + 3) Enabled Low High High Low Enabled High High High High High High High High High High High Low High High Disabled Enabled* Disabled Address Invalid data Invalid data Invalid data Valid data 1 Word Access (Address 4n) Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Enabled* Disabled Address Valid data Valid data Invalid data Invalid data 1 Word Access (Address 4n + 2) Enabled Low High High Low Enabled High High High High High High High High High Low High Low High High Disabled Enabled* Disabled Address Invalid data Invalid data Valid data Valid data 1 Longword Access Enabled Low High High Low Enabled High High High High High Low High Low High Low High Low High High Disabled Enabled* Disabled Address Valid data Valid data Valid data Valid data 1 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up or down. Rev. 4.00, 03/04, page 639 of 660 Table B.4 Pin States (Normal Memory/Big Endian) 8-Bit Bus Width Byte/Word/Longword Access Enabled R W Low High High Low Enabled High High High High R W High Low High High High High High High High High Disabled Enabled* Disabled Address Valid data High-Z* 2 1 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled* Disabled Address Invalid data Valid data High-Z*2 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 2n + 1) Enabled Low High High Low Enabled High High High High High Low High High High High High High High High Disabled Enabled* Disabled Address Valid data Invalid data High-Z*2 1 Word/Longword Access Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Enabled* Disabled Address Valid data Valid data High-Z*2 1 RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 R W R W High-Z*2 Rev. 4.00, 03/04, page 640 of 660 32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL R W WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 R W R W Low High High Low Enabled High High High High High High High High High High High Low High High Disabled Enabled*1 Disabled Address Invalid data Invalid data Invalid data Valid data Byte Access (Address 4n + 1) Enabled Low High High Low Enabled High High High High High High High High High Low High High High High Disabled Enabled*1 Disabled Address Invalid data Invalid data Valid data Invalid data Byte Access (Address 4n + 2) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled*1 Disabled Address Invalid data Valid data Invalid data Invalid data Byte Access (Address 4n + 3) Enabled Low High High Low Enabled High High High High High Low High High High High High High High High Disabled Enabled*1 Disabled Address Valid data Invalid data Invalid data Invalid data Word Access (Address 4n) Enabled Low High High Low Enabled High High High High High High High High High Low High Low High High Disabled Enabled*1 Disabled Address Invalid data Invalid data Valid data Valid data Word Access (Address 4n + 2) Enabled Low High High Low Enabled High High High High High Low High Low High High High High High High Disabled Enabled*1 Disabled Address Valid data Valid data Invalid data Invalid data Pin CS6 to CS2, CS0 RD Longword Access Enabled Low High High Low Enabled High High High High High Low High Low High Low High Low High High Disabled Enabled*1 Disabled Address Valid data Valid data Valid data Valid data Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up or down. Rev. 4.00, 03/04, page 641 of 660 Table B.5 Pin States (Burst ROM/Little Endian) 8-Bit Bus Width Byte/Word/Longword Access Enabled R W Low -- High -- Enabled High High High High R W High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Valid data High-Z* 2 1 16-Bit Bus Width Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Valid data Invalid data High-Z*2 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 2n + 1) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Invalid data Valid data High-Z*2 1 Word/Longword Access Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Valid data Valid data High-Z*2 1 RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 R W R W High-Z*2 Rev. 4.00, 03/04, page 642 of 660 32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL R W WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 R W R W Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Invalid data Invalid data Invalid data Byte Access (Address 4n + 1) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Valid data Invalid data Invalid data Byte Access (Address 4n + 2) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Invalid data Valid data Invalid data Byte Access (Address 4n + 3) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Invalid data Invalid data Valid data Word Access (Address 4n) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data Invalid data Invalid data Word Access (Address 4n + 2) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Invalid data Valid data Valid data Pin CS6 to CS2, CS0 RD Longword Access Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data Valid data Valid data Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up or down. Rev. 4.00, 03/04, page 643 of 660 Table B.6 Pin States (Burst ROM/Big Endian) 8-Bit Bus Width Byte/Word/Longword Access Enabled R W Low -- High -- Enabled High High High High R W High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data High-Z* High-Z* 2 2 16-Bit Bus Width Byte Access (Address 2n) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Invalid data Valid data High-Z* 2 Pin CS6 to CS2, CS0 RD Byte Access (Address 2n + 1) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Invalid data High-Z* 2 Word/Longword Access Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data High-Z* 2 RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 R W R W Rev. 4.00, 03/04, page 644 of 660 32-Bit Bus Width Byte Access (Address 4n) Enabled R W RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL R W WE1/WE/DQMLU R W WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 R W R W Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Invalid data Invalid data Invalid data Valid data 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 4n + 1) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Invalid data Invalid data Valid data Invalid data 1 Byte Access (Address 4n + 2) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Invalid data Valid data Invalid data Invalid data 1 Byte Access (Address 4n + 3) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Valid data Invalid data Invalid data Invalid data 1 Word Access (Address 4n) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Invalid data Invalid data Valid data Valid data 1 Word Access (Address 4n + 2) Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled* Disabled Address Valid data Valid data Invalid data Invalid data 1 Longword Access Enabled Low -- High -- Enabled High High High High High -- High -- High -- High -- High High Disabled Enabled*1 Disabled Address Valid data Valid data Valid data Valid data Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up or down. Rev. 4.00, 03/04, page 645 of 660 Table B.7 Pin States (Synchronous DRAM/Little Endian) 32-Bit Bus Width Byte Access (Address 4n) Enabled R W High High High Low Enabled High/Low* 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 4n + 1) Enabled High High High Low Enabled High/Low* 1 Byte Access (Address 4n + 2) Enabled High High High Low Enabled High/Low* 1 Byte Access (Address 4n + 3) Enabled High High High Low Enabled High/Low* 1 Word Access (Address 4n) Enabled High High High Low Enabled High/Low* 1 Word Access (Address 4n + 2) Enabled High High High Low Enabled High/Low* 1 Longword Access Enabled High High High Low Enabled High/Low* 1 RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] DQMLL/WE0 R W DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 Low/High*1 Low/High*1 Low/High*1 Low/High*1 Low/High*1 Low/High*1 Low/High*1 High/Low* Low/High* Low Low High High High High High High High High High* 2 1 1 High/Low* Low/High* High High Low Low High High High High High High High* 2 1 1 High/Low* Low/High* High High High High Low Low High High High High High* 2 1 1 High/Low* Low/High* High High High High High High Low Low High High High* 2 1 1 High/Low* Low/High* Low Low Low Low High High High High High High High* 2 1 1 High/Low* Low/High* High High High High Low Low Low Low High High High* 2 1 1 High/Low* 1 Low/High*1 Low Low Low Low Low Low Low Low High High High*2 Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command D7 to D0 D15 to D8 D23 to D16 D31 to D24 Valid data Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Valid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Invalid data Valid data Notes: 1. Lower 32-Mbyte access/Upper 32-Mbyte access 2. Normally high. Low in self-refreshing. Rev. 4.00, 03/04, page 646 of 660 Table B.8 Pin States (Synchronous DRAM/Big Endian) 32-Bit Bus Width Byte Access (Address 4n) Enabled R W High High High Low Enabled High/Low* Low/High* High/Low* Low/High* R W High High High High High High Low Low High High High* 2 1 1 1 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 4n + 1) Enabled High High High Low Enabled High/Low* Low/High* High/Low* Low/High* High High High High Low Low High High High High High* 2 1 1 1 1 Byte Access (Address 4n + 2) Enabled High High High Low Enabled High/Low* Low/High* High/Low* Low/High* High High Low Low High High High High High High High* 2 1 1 1 1 Byte Access (Address 4n + 3) Enabled High High High Low Enabled High/Low* Low/High* High/Low* Low/High* Low Low High High High High High High High High High* 2 1 1 1 1 Word Access (Address 4n) Enabled High High High Low Enabled High/Low* Low/High* High/Low* Low/High* High High High High Low Low Low Low High High High* 2 1 1 1 1 Word Access (Address 4n + 2) Enabled High High High Low Enabled High/Low* Low/High* High/Low* Low/High* Low Low Low Low High High High High High High High* 2 1 1 1 1 Longword Access Enabled High High High Low Enabled High/Low* 1 RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] DQMLL/WE0 Low/High*1 High/Low*1 Low/High* Low Low Low Low Low Low Low* Low High High High*2 Disabled Disabled Address command Valid data Valid data 1 1 DQMLU/WE1 R W DQMUL/WE2/ICIORD R W DQMUU/WE3/ICIOWR R W CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D23 to D16 D31 to D24 Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Disabled Disabled Address command Invalid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Valid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Invalid data Valid data Invalid data Valid data Invalid data Valid data Invalid data Invalid data Invalid data Valid data Notes: 1. Lower 32-Mbyte access/ Upper 32-Mbyte access 2. Normally high. Low in self-refreshing. Rev. 4.00, 03/04, page 647 of 660 Table B.9 Pin States (PCMCIA/Little Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled R W Low High High Low Enabled High High High High R W High High High Low High High High High High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 PCMCIA/IO Interface (Area 5) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled 16-Bit Bus Width Byte Access (Ad-dress 2n) Byte Access Word/ (Ad-dress Long2n + 1) word Access High Low High High Low Enabled High High High High High High High Low High High High High Low High Disabled Enabled Low High High Low Enabled High High High High High High High Low High High High High Low High Disabled 16-Bit Bus Width Byte Access (Ad-dress 2n) Byte Access Word/ (Ad-dress Long-word 2n + 1) Access Pin CS6 to CS2, CS0 RD Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled*1 Disabled Address Valid data Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled High High High High Low Enabled High High High High High High High High Low High High Low Low High Disabled Enabled High High High Low Enabled High High High High High High High High Low High High Low Low High Disabled RD/WR R W BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/WE/DQMLU R W WE2/ICIORD/ DQMUL/PTC[1] WE3/ICIOWR/ DQMUU/PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 R W R W Enabled*1 Enabled*1 Disabled Address Disabled Address Enabled*1 Enabled*1 Enabled*1 Enabled*1 Disabled Address Disabled Address Enabled Address Enabled Address Invalid data Valid data Valid data Valid data Invalid data Valid data High-Z*2 High-Z*2 Invalid data Valid data Valid data High-Z*2 High-Z*2 High-Z*2 Invalid data Valid data Valid data High-Z*2 High-Z*2 High-Z*2 Rev. 4.00, 03/04, page 648 of 660 PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled R W RD/WR BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/WE/DQMLU WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 R W R W R W R W R W Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled * 1 PCMCIA/IO Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled Enabled * 1 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled * 1 16-Bit Bus Width Byte Access (Address 2n) Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled Enabled * 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High Low High High High High High Low Disabled Enabled * 1 Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High Low High High High High High Low Disabled Enabled * 1 Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High High High Low High High Low High Low Disabled Enabled * 1 Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High Low Disabled Enabled * 1 Disabled Address Valid data High-Z*2 High-Z*2 Disabled Address Valid data Invalid data High-Z*2 Disabled Address Invalid data Valid data High-Z*2 Disabled Address Valid data Valid data High-Z*2 Disabled Address Valid data High-Z*2 High-Z*2 Disabled Address Valid data Invalid data High-Z*2 Enabled Address Invalid data Valid data High-Z*2 Enabled Address Valid data Valid data High-Z*2 D15 to D8 D31 to D16 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up or down. Rev. 4.00, 03/04, page 649 of 660 Table B.10 Pin States (PCMCIA/Big Endian) PCMCIA Memory Interface (Area 5) 8-Bit Bus Width PCMCIA/IO Interface (Area 5) 8-Bit Bus Width 16-Bit Bus Width Byte Access (Ad-dress 2n + 1) High Low High High Low Enabled High High High High High High High Low High High High Low Low High Disabled Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High Low High High High Low Low High Disabled Enabled*1 Disabled Address Valid data 16-Bit Bus Width Byte Access (Ad-dress 2n + 1) High High High High Low Enabled High High High High High High High High Low High High Low Low High Disabled Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low Low High Disabled 1 Pin CS6 to CS2, CS0 RD R Byte/Word/ Byte Long-word Access Access (Ad-dress 2n) Enabled Low Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Byte/Word/ Byte Long-word Access Access (Ad-dress 2n) Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled W High RD/WR R High W Low BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL R Enabled High High High High High W High WE1/WE/DQMLU R High W Low WE2/ICIORD/ DQMUL/PTC[1] WE3/ICIOWR/ DQMUU/PTC[2] CE2A/PTD[6] CE2B/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 R High W High R High W High High High Disabled Enabled*1 Disabled Address Valid data High-Z*2 High-Z*2 Enabled*1 Enabled*1 Disabled Address Disabled Address Enabled*1 Enabled*1 Enabled* Disabled Address Disabled Address Disabled Address Invalid data Valid data Invalid data Valid data Valid data Valid data High-Z*2 Invalid data Valid data High-Z*2 High-Z*2 Valid data Invalid data Valid data High-Z*2 High-Z*2 High-Z*2 Rev. 4.00, 03/04, page 650 of 660 PCMCIA Memory Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled R W RD/WR BS RASU/PTD[1] RASL/PTD[0] CASL/PTD[2] CASU/PTD[3] WE0/DQMLL WE1/WE/DQMLU WE2/ICIORD/DQMUL/ PTC[1] WE3/ICIOWR/DQMUU/ PTC[2] CE2A*3/PTD[6] CE2B*3/PTD[7] CKE WAIT IOIS16 A25 to A0 D7 to D0 D15 to D8 D31 to D16 R W R W R W R W R W Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled * 1 PCMCIA/IO Interface (Area 6) 8-Bit Bus Width Byte/ Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled Enabled * 1 16-Bit Bus Width Byte Access (Address 2n) Enabled Low High High Low Enabled High High High High High High High Low High High High High High High Disabled Enabled * 1 16-Bit Bus Width Byte Access (Address 2n) Enabled High High High Low Enabled High High High High High High High High Low High High Low High High Disabled Enabled * 1 Pin CS6 to CS2, CS0 RD Byte Access (Address 2n + 1) High Low High High Low Enabled High High High High High High High Low High High High High High Low Disabled Enabled * 1 Word/ Longword Access Enabled Low High High Low Enabled High High High High High High High Low High High High High High Low Disabled Enabled * 1 Byte Access (Address 2n+1) High High High High Low Enabled High High High High High High High High Low High High Low High Low Disabled Enabled * 1 Word/ Longword Access Enabled High High High Low Enabled High High High High High High High High Low High High Low High Low Disabled Enabled * 1 Disabled Address Valid data High-Z* High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Valid data Invalid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 Disabled Address Valid data High-Z* 2 Disabled Address Invalid data Valid data High-Z* 2 Disabled Address Invalid data Invalid data High-Z* 2 Disabled Address Valid data Valid data High-Z* 2 2 High-Z* 2 Notes: 1. Disabled when WCR2 register wait setting is 0. 2. Unused data pins should be switched to the port function, or pulled up or down. 3. The behavior of the CE pin in the big endian is the same as that in the little endian. Rev. 4.00, 03/04, page 651 of 660 Rev. 4.00, 03/04, page 652 of 660 C. Product Lineup Package 176-pin plastic LQFP (FP-176C) 208-pin TFBGA (TBP-208A) Model Marking HD6417706F133 HD6417706BP133 Rev. 4.00, 03/04, page 653 of 660 D. Package Dimensions Figures D.1 and D.2 show the SH7706 package dimensions. 26.0 0.2 24 132 133 89 88 As of January, 2003 Unit: mm 26.0 0.2 176 1 *0.22 0.05 0.20 0.04 44 45 1.70 Max *0.17 0.05 0.15 0.04 1.40 0.08 M 0.5 1.25 1.0 0 - 8 0.10 0.05 0.08 0.5 0.1 *Dimension including the plating thickness Base material dimension Package Code JEDEC JEITA Mass (reference value) FP-176C -- Conforms 1.9 g Figure D.1 Package Dimensions (FP-176C) Rev. 4.00, 03/04, page 654 of 660 As of January, 2003 Unit: mm 0.20 C B 12.00 0.65 0.20 C A 16 14 12 10 8 6 4 2 17 15 13 11 9 7 5 3 1 A C E B D F H K M P T B 12.00 G J L N R U A 0.80 0.65 4x 0.15 0.80 208 x 0.40 0.05 0.08 M C A B 0.2 C C 0.31 0.05 1.20Max 0.10 C Package Code JEDEC JEITA Mass (reference value) TBP-208A - - 0.26 g Figure D.2 Package Dimensions (TBP-208A) Rev. 4.00, 03/04, page 655 of 660 Rev. 4.00, 03/04, page 656 of 660 Index ADCR ............................. 501, 550, 562, 567 ADCSR........................... 499, 550, 562, 567 ADDRA .................................................. 498 ADDRAH ....................... 497, 550, 562, 567 ADDRAL........................ 497, 550, 562, 567 ADDRB .................................................. 498 ADDRBH ....................... 497, 550, 562, 567 ADDRBL........................ 497, 550, 562, 567 ADDRC .................................................. 498 ADDRCH ....................... 497, 550, 562, 567 ADDRCL........................ 497, 550, 562, 567 ADDRD .................................................. 498 ADDRDH ....................... 497, 550, 562, 567 ADDRDL........................ 497, 550, 562, 567 Address Array......................................... 100 Address Translation .................................. 55 Addressing Modes .................................... 23 Area 0 ..................................................... 197 Area 1 ..................................................... 197 Area 2 ..................................................... 197 Area 3 ..................................................... 198 Area 4 ..................................................... 198 Area 5 ..................................................... 198 Area 6 ..................................................... 199 Auto-Request Mode................................ 257 Avoiding Synonym Problems ................... 67 BAMRA.......................... 138, 547, 557, 564 BAMRB.......................... 140, 547, 556, 564 BARA ............................. 137, 547, 557, 564 BARB ............................. 139, 547, 556, 564 BASRA........................... 147, 547, 557, 564 BASRB ........................... 148, 547, 557, 564 BBRA ............................. 138, 547, 557, 564 BBRB ............................. 141, 547, 557, 564 BCR1 .............................. 169, 547, 555, 565 BCR2 .............................. 172, 547, 555, 565 BDMRB.......................... 140, 547, 556, 564 BDRB ............................. 140, 547, 556, 564 BETR .............................. 145, 547, 557, 564 Big-endian................................................. 20 BRCR.............................. 142, 547, 556, 564 BRDR.............................. 147, 547, 557, 564 BRSR .............................. 146, 547, 557, 564 Burst Mode..............................................272 Bus Modes ..............................................271 CCR ................................ 101, 547, 558, 564 CCR2 .............................. 102, 547, 558, 564 Changing the Division Ratio ...................300 Changing the Multiplication Rate ...........300 Channel Priority ......................................259 CHCR_0.......................... 247, 549, 559, 566 CHCR_1.......................... 247, 550, 560, 566 CHCR_2.......................... 247, 550, 560, 567 CHCR_3.......................... 247, 550, 561, 567 Clock Synchronous Operation ................389 CMCNT .......................... 284, 550, 561, 567 CMCOR .......................... 284, 550, 561, 567 CMCSR........................... 283, 550, 561, 567 CMSTR ........................... 283, 550, 561, 567 Control Registers.......................................17 Cycle-Steal Mode....................................271 DACR ............................. 515, 550, 562, 567 DADR0 ........................... 514, 550, 562, 567 DADR1 ........................... 514, 550, 562, 567 DAR_0 ............................ 246, 549, 559, 566 DAR_1 ............................ 246, 550, 560, 566 DAR_2 ............................ 246, 550, 560, 567 DAR_3 ............................ 246, 550, 561, 567 Data Array...............................................108 Delayed Branching....................................21 DMA Transfer Requests .........................257 DMAOR.......................... 253, 550, 561, 567 DMATCR_0 ................... 247, 549, 559, 566 DMATCR_1 ................... 247, 550, 560, 566 DMATCR_2 ................... 247, 550, 560, 567 DMATCR_3 ................... 247, 550, 561, 567 Dual Address Mode ................................263 Exception Codes .......................................85 EXPEVT ........................... 87, 547, 557, 564 External Request Mode...........................257 Rev. 4.00, 03/04, page 657 of 660 Fixed Mode............................................. 259 FRQCR ........................... 298, 547, 556, 564 GBR.......................................................... 17 General Exceptions................................... 91 General Registers...................................... 15 ICR0 ............................... 122, 548, 555, 565 ICR1 ............................... 123, 549, 559, 566 Instruction Code Map ............................... 46 Instruction Formats................................... 27 Instruction Set........................................... 30 Interrupt Response Time......................... 132 Interrupts................................................... 94 INTEVT............................ 87, 547, 558, 564 INTEVT2.......................... 87, 549, 559, 566 IPRA ............................... 121, 548, 555, 565 IPRB ............................... 121, 548, 555, 565 IPRC ............................... 121, 549, 559, 566 IPRD ............................... 121, 549, 559, 566 IPRE ............................... 121, 549, 559, 566 IRR0 ............................... 125, 549, 559, 566 IRR1 ............................... 127, 549, 559, 566 IRR2 ............................... 128, 549, 559, 566 little-endian............................................... 20 MAC ......................................................... 16 MCR ............................... 180, 548, 555, 565 MMUCR........................... 58, 547, 558, 564 Mode 0.................................................... 295 Mode 1.................................................... 295 Mode 2.................................................... 295 Mode 7.................................................... 295 Multiple Virtual Memory Mode ............... 55 On-Chip Peripheral Module Request...... 258 PACR.............................. 463, 551, 562, 567 PADR ............................. 479, 551, 563, 568 PBCR.............................. 464, 551, 562, 567 PBDR.............................. 481, 551, 563, 568 PC ............................................................. 16 PCCR...................................... 466, 551, 567 PCDR.......................482, 551, 562, 563, 568 PCMCIA................................................. 165 PCR................................. 185, 548, 555, 565 PDCR.............................. 467, 551, 562, 567 PDDR ............................. 484, 551, 563, 568 Rev. 4.00, 03/04, page 658 of 660 PECR .............................. 469, 551, 562, 567 PEDR .............................. 485, 551, 563, 568 PFCR............................... 470, 551, 562, 567 PFDR .............................. 487, 551, 563, 568 PGCR .............................. 472, 551, 562, 568 PGDR.............................. 488, 551, 563, 568 PHCR .............................. 473, 551, 562, 568 PHDR.............................. 490, 551, 563, 568 PJCR ............................... 475, 551, 562, 568 PJDR ............................... 492, 551, 563, 568 PR ............................................................. 16 Processor Modes ....................................... 50 PTEH ................................ 56, 547, 558, 564 PTEL................................. 57, 547, 558, 564 R64CNT.......................... 328, 548, 554, 565 RCR1 .............................. 338, 548, 555, 565 RCR2 .............................. 339, 548, 555, 565 RDAYAR........................ 336, 548, 555, 565 RDAYCNT ..................... 331, 548, 554, 565 Resets ........................................................ 90 RFCR .............................. 192, 548, 556, 565 RHRAR........................... 334, 548, 555, 565 RHRCNT ........................ 329, 548, 554, 565 RMINAR ........................ 333, 548, 555, 565 RMINCNT ...................... 329, 548, 554, 565 RMONAR....................... 337, 548, 555, 565 RMONCNT .................... 331, 548, 554, 565 Round-Robin Mode ................................ 259 RSECAR......................... 332, 548, 555, 565 RSECCNT ...................... 328, 548, 554, 565 RTCNT ........................... 191, 548, 555, 565 RTCOR ........................... 191, 548, 556, 565 RTCSR............................ 188, 548, 555, 565 RWKAR.......................... 335, 548, 555, 565 RWKCNT ....................... 330, 548, 554, 565 RYRCNT ........................ 332, 548, 555, 565 SAR_0............................. 246, 549, 559, 566 SAR_1............................. 246, 550, 560, 566 SAR_2............................. 246, 550, 560, 567 SAR_3............................. 246, 550, 561, 567 SCBRR............................ 366, 549, 553, 566 SCBRR2.......................... 439, 551, 553, 568 SCFCR2 .......................... 443, 551, 553, 568 SCFDR2.......................... 445, 551, 553, 568 SCFRDR2 ....................... 426, 551, 553, 568 SCFTDR2 ....................... 426, 551, 553, 568 SCPCR.................... 364, 476, 551, 562, 568 SCPDR.................... 365, 493, 551, 563, 568 SCRDR ........................... 352, 549, 553, 566 SCRSR.................................................... 352 SCRSR2.................................................. 426 SCSCMR ........................ 403, 549, 553, 566 SCSCR............................ 355, 549, 553, 566 SCSCR2.......................... 429, 551, 553, 568 SCSMR........................... 353, 549, 553, 566 SCSMR2 ......................... 426, 551, 553, 568 SCSSR .................... 359, 404, 549, 553, 566 SCSSR2 .......................... 431, 551, 553, 568 SCTDR ........................... 352, 549, 553, 566 SCTSR .................................................... 352 SCTSR2 .................................................. 426 SDBPR.................................................... 519 SDBSR.................................................... 520 SDIR ............................... 519, 551, 563, 568 SDMR..................................... 188, 548, 556 Self-Refreshing ....................................... 223 Single Address Mode.............................. 269 Single Virtual Memory Mode................... 55 Space Allocation..................................... 162 SPC ........................................................... 17 SR..............................................................17 SSR ...........................................................17 STBCR............................ 532, 547, 556, 564 STBCR2.......................... 534, 547, 556, 564 System Registers .......................................16 TCNT_0 .................................. 549, 553, 566 TCNT_1 .................................. 549, 554, 566 TCNT_2 .......................... 318, 549, 554, 566 TCOR_0.......... 314, 317, 318, 549, 553, 565 TCOR_1.......... 314, 317, 318, 549, 554, 566 TCOR_2.......................... 317, 549, 554, 566 TCPR_2 .......................... 318, 549, 554, 566 TCR_0............................. 314, 549, 553, 566 TCR_1............................. 314, 549, 554, 566 TCR_2............................. 314, 549, 554, 566 TEA................................... 57, 547, 558, 564 TOCR.............................. 312, 549, 553, 565 TRA .................................. 87, 547, 557, 564 TSTR............................... 313, 549, 553, 565 TTB................................... 57, 547, 558, 564 VBR ..........................................................17 Virtual Address Map .................................53 virtual memory system..............................51 WCR1 ............................. 174, 548, 555, 565 WCR2 ............................. 177, 548, 555, 565 WTCNT .......................... 304, 547, 556, 564 WTCSR................................... 304, 547, 556 Rev. 4.00, 03/04, page 659 of 660 Rev. 4.00, 03/04, page 660 of 660 Renesas 32-Bit RISC Microcomputer Hardware Manual SH7706 Group Publication Date: 1st Edition, September 2001 Rev.4.00, March 22, 2004 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Technical Documentation & Information Department Renesas Kodaira Semiconductor Co., Ltd. (c) 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. 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